JP5243958B2 - マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム - Google Patents
マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム Download PDFInfo
- Publication number
- JP5243958B2 JP5243958B2 JP2008535640A JP2008535640A JP5243958B2 JP 5243958 B2 JP5243958 B2 JP 5243958B2 JP 2008535640 A JP2008535640 A JP 2008535640A JP 2008535640 A JP2008535640 A JP 2008535640A JP 5243958 B2 JP5243958 B2 JP 5243958B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- design
- band
- tolerance
- constraint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
Claims (7)
- マスク・レイアウトを設計する方法であって、
二次元平面上に配置された構造体を含み、第3の次元に沿って互いに位置あわせされた、複数の設計層を含む回路設計を準備するステップと、
基板上に形成される重要な構造体を含む前記複数の設計層のうちの選択された1つの設計層を特定するステップと、
前記選択された設計層とは異なる前記複数の設計層のうちの1つの設計層における前記重要な構造体に影響を与える構造体と関連する制約バンドを決定するステップであって、前記影響を与える構造体は前記重要な構造体と相互作用し、前記制約バンドは1つ又は複数の制約と関連する、ステップと、
前記重要な構造体と関連する許容バンドを決定するステップであって、前記許容バンドは、前記重要な構造体が基板上に形成されたときに所定の基準を満たす領域を定めるものであり、前記制約バンドと関連する前記1つ又は複数の制約に従って制約される縁部を含む、ステップと、
を含む方法。 - 前記複数の設計層のうちの前記選択された1つの設計層における前記重要な構造体が、前記選択された設計層とは異なる設計層における構造体に影響を与える構造体となる場合には、前記許容バンドを制約バンドとして用いるステップをさらに含む、請求項1に記載の方法。
- 前記制約バンドは、
前記選択された設計層とは異なる前記複数の設計層のうちの前記1つの設計層における前記重要な構造体に影響を与える構造体のCD許容領域と、
前記複数の設計層のうちの前記選択された1つの設計層における前記重要な構造体に関する前記重要な構造体に影響を与える構造体の重なり許容領域と、
をさらに含む、請求項1に記載の方法。 - 前記制約バンドは、
前記選択された設計層とは異なる前記複数の設計層のうちの前記1つの設計層における前記重要な構造体に影響を与える構造体についての許容バンドと、
前記複数の設計層のうちの前記選択された1つの設計層における前記重要な構造体に関する前記重要な構造体に影響を与える構造体の重なり許容領域と、
をさらに含む、請求項1に記載の方法。 - 前記複数の設計層のサブセットを、その各々が重要な構造体を含むように予め選択するステップと、
選択された1つの設計層を特定する前記ステップの前に、所定の基準に従って前記サブセットの順位付けを行うステップと、
選択された1つの設計層を特定するステップ、制約バンドを決定するステップ、及び、前記サブセットの各々についての許容バンドを前記順位付けの順番に決定するステップを実施するステップと、
をさらに含む、請求項1に記載の方法。 - 請求項1乃至5のいずれかに記載の方法の各ステップをコンピュータに実行させる、プログラム。
- 請求項1乃至5のいずれかに記載の方法の各ステップを実行するための手段を備える、システム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/163,264 US7266798B2 (en) | 2005-10-12 | 2005-10-12 | Designer's intent tolerance bands for proximity correction and checking |
US11/163,264 | 2005-10-12 | ||
PCT/US2006/039701 WO2007047298A1 (en) | 2005-10-12 | 2006-10-11 | Designer's intent tolerance bands for proximity correction and checking |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009511988A JP2009511988A (ja) | 2009-03-19 |
JP2009511988A5 JP2009511988A5 (ja) | 2009-04-30 |
JP5243958B2 true JP5243958B2 (ja) | 2013-07-24 |
Family
ID=37912233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008535640A Expired - Fee Related JP5243958B2 (ja) | 2005-10-12 | 2006-10-11 | マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム |
Country Status (7)
Country | Link |
---|---|
US (2) | US7266798B2 (ja) |
EP (1) | EP1952289A4 (ja) |
JP (1) | JP5243958B2 (ja) |
KR (1) | KR101006264B1 (ja) |
CN (1) | CN101288080B (ja) |
TW (1) | TW200725348A (ja) |
WO (1) | WO2007047298A1 (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
US7506277B1 (en) * | 2005-07-28 | 2009-03-17 | Cadence Design Systems, Inc. | Method and mechanism for implementing DFM aware cells for an electronic design |
US7491594B2 (en) * | 2005-10-26 | 2009-02-17 | Freescale Semiconductor, Inc. | Methods of generating planar double gate transistor shapes |
US7530037B2 (en) * | 2005-10-26 | 2009-05-05 | Freescale Semiconductor, Inc. | Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods |
US7458060B2 (en) * | 2005-12-30 | 2008-11-25 | Lsi Logic Corporation | Yield-limiting design-rules-compliant pattern library generation and layout inspection |
US7503028B2 (en) * | 2006-01-10 | 2009-03-10 | International Business Machines Corporation | Multilayer OPC for design aware manufacturing |
US7448008B2 (en) * | 2006-08-29 | 2008-11-04 | International Business Machines Corporation | Method, system, and program product for automated verification of gating logic using formal verification |
US7448018B2 (en) * | 2006-09-12 | 2008-11-04 | International Business Machines Corporation | System and method for employing patterning process statistics for ground rules waivers and optimization |
US7765518B2 (en) * | 2008-03-20 | 2010-07-27 | International Business Machines Corporation | System and method for implementing optical rule checking to identify and quantify corner rounding errors |
US8136054B2 (en) * | 2009-01-29 | 2012-03-13 | Synopsys, Inc. | Compact abbe's kernel generation using principal component analysis |
US20110047519A1 (en) | 2009-05-11 | 2011-02-24 | Juan Andres Torres Robles | Layout Content Analysis for Source Mask Optimization Acceleration |
US8281263B2 (en) * | 2009-12-17 | 2012-10-02 | International Business Machines Corporation | Propagating design tolerances to shape tolerances for lithography |
US8331646B2 (en) | 2009-12-23 | 2012-12-11 | International Business Machines Corporation | Optical proximity correction for transistors using harmonic mean of gate length |
US8631379B2 (en) * | 2010-02-09 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Decomposing integrated circuit layout |
US8392871B2 (en) | 2010-04-30 | 2013-03-05 | International Business Machines Corporation | Decomposition with multiple exposures in a process window based OPC flow using tolerance bands |
US8415077B2 (en) | 2010-08-13 | 2013-04-09 | International Business Machines Corporation | Simultaneous optical proximity correction and decomposition for double exposure lithography |
US8875063B2 (en) | 2010-10-11 | 2014-10-28 | International Business Machines Corporation | Mask layout formation |
US8381141B2 (en) * | 2010-10-28 | 2013-02-19 | International Business Machines Corporation | Method and system for comparing lithographic processing conditions and or data preparation processes |
US8298953B2 (en) | 2010-12-20 | 2012-10-30 | Infineon Technologies Ag | Method for defining a separating structure within a semiconductor device |
US8365108B2 (en) | 2011-01-06 | 2013-01-29 | International Business Machines Corporation | Generating cut mask for double-patterning process |
US9330223B2 (en) | 2012-09-28 | 2016-05-03 | International Business Machines Corporation | Optical rule checking for detecting at risk structures for overlay issues |
US9250535B2 (en) | 2013-03-15 | 2016-02-02 | International Business Machines Corporation | Source, target and mask optimization by incorporating countour based assessments and integration over process variations |
US9262578B2 (en) | 2014-04-25 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit manufacturing |
CN108009352A (zh) * | 2017-11-30 | 2018-05-08 | 上海华力微电子有限公司 | 一种光刻版图的填充流程及光刻掩膜的设计方法 |
CN113050389B (zh) * | 2021-03-30 | 2022-12-02 | 长鑫存储技术有限公司 | 光刻工艺条件添加方法及装置、设计系统、介质和设备 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0126640B1 (ko) * | 1994-05-07 | 1998-04-02 | 김주용 | 반도체소자 및 그 제조방법 |
KR970003508A (ko) * | 1995-06-30 | 1997-01-28 | 김주용 | 반도체소자의 제조방법 |
JP3466852B2 (ja) * | 1997-02-18 | 2003-11-17 | 株式会社東芝 | 半導体装置の製造方法 |
US5958635A (en) * | 1997-10-20 | 1999-09-28 | Motorola, Inc. | Lithographic proximity correction through subset feature modification |
US6557162B1 (en) * | 2000-09-29 | 2003-04-29 | Numerical Technologies, Inc. | Method for high yield reticle formation |
US6553559B2 (en) * | 2001-01-05 | 2003-04-22 | International Business Machines Corporation | Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions |
US6578190B2 (en) * | 2001-01-11 | 2003-06-10 | International Business Machines Corporation | Process window based optical proximity correction of lithographic images |
JP2003043666A (ja) * | 2001-08-03 | 2003-02-13 | Matsushita Electric Ind Co Ltd | 回路設計パターンの評価方法 |
JP2003142584A (ja) * | 2001-11-05 | 2003-05-16 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置の設計方法 |
JP2003322945A (ja) * | 2002-05-01 | 2003-11-14 | Mitsubishi Electric Corp | レイアウトパターンデータの補正装置 |
US7302672B2 (en) * | 2002-07-12 | 2007-11-27 | Cadence Design Systems, Inc. | Method and system for context-specific mask writing |
CN100403518C (zh) * | 2002-08-06 | 2008-07-16 | 松下电器产业株式会社 | 半导体装置及其制造方法、生成该装置图案的装置和方法 |
US7313508B2 (en) * | 2002-12-27 | 2007-12-25 | Lsi Corporation | Process window compliant corrections of design layout |
US6928634B2 (en) * | 2003-01-02 | 2005-08-09 | Yuri Granik | Matrix optical process correction |
US7550235B2 (en) * | 2003-09-05 | 2009-06-23 | Asml Masktools B.V. | Method and apparatus for performing model based placement of phase-balanced scattering bars for sub-wavelength optical lithography |
JP4068541B2 (ja) * | 2003-09-25 | 2008-03-26 | 株式会社東芝 | 集積回路パターン検証装置と検証方法 |
US7155689B2 (en) * | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
US7269817B2 (en) * | 2004-02-10 | 2007-09-11 | International Business Machines Corporation | Lithographic process window optimization under complex constraints on edge placement |
EP1747520B1 (en) * | 2004-05-07 | 2018-10-24 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US7908572B2 (en) * | 2004-10-15 | 2011-03-15 | Takumi Technology Corporation | Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity |
US7260814B2 (en) * | 2004-12-14 | 2007-08-21 | Lsi Corporation | OPC edge correction based on a smoothed mask design |
US7284231B2 (en) * | 2004-12-21 | 2007-10-16 | Freescale Semiconductor, Inc. | Layout modification using multilayer-based constraints |
US7914949B2 (en) * | 2005-02-24 | 2011-03-29 | International Business Machines Corporation | Method for testing a photomask |
JP2007102207A (ja) * | 2005-09-08 | 2007-04-19 | Takumi Technology Corp | 複雑度低減のためのルールベース光学近接効果補正における可変バイアス・ルールの作成および適用 |
-
2005
- 2005-10-12 US US11/163,264 patent/US7266798B2/en not_active Expired - Fee Related
-
2006
- 2006-10-03 TW TW095136676A patent/TW200725348A/zh unknown
- 2006-10-11 KR KR1020087009578A patent/KR101006264B1/ko not_active IP Right Cessation
- 2006-10-11 EP EP06816698A patent/EP1952289A4/en not_active Withdrawn
- 2006-10-11 WO PCT/US2006/039701 patent/WO2007047298A1/en active Application Filing
- 2006-10-11 CN CN2006800379581A patent/CN101288080B/zh not_active Expired - Fee Related
- 2006-10-11 JP JP2008535640A patent/JP5243958B2/ja not_active Expired - Fee Related
-
2007
- 2007-07-16 US US11/778,302 patent/US7607114B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2007047298A1 (en) | 2007-04-26 |
US7266798B2 (en) | 2007-09-04 |
KR20080067624A (ko) | 2008-07-21 |
JP2009511988A (ja) | 2009-03-19 |
US20070261013A1 (en) | 2007-11-08 |
CN101288080A (zh) | 2008-10-15 |
KR101006264B1 (ko) | 2011-01-06 |
US20070083847A1 (en) | 2007-04-12 |
CN101288080B (zh) | 2012-05-23 |
TW200725348A (en) | 2007-07-01 |
EP1952289A4 (en) | 2009-07-29 |
US7607114B2 (en) | 2009-10-20 |
EP1952289A1 (en) | 2008-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5243958B2 (ja) | マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム | |
US20080082952A1 (en) | Method of inclusion of sub-resolution assist feature(s) | |
US8438506B2 (en) | Method and system for implementing controlled breaks between features using sub-resolution assist features | |
US8572533B2 (en) | Waiving density violations | |
US20120047479A1 (en) | Incremental Layout Analysis | |
US20100257496A1 (en) | Design-Rule-Check Waiver | |
US8788982B2 (en) | Layout design defect repair using inverse lithography | |
US10732499B2 (en) | Method and system for cross-tile OPC consistency | |
US8910094B2 (en) | Retargeting semiconductor device shapes for multiple patterning processes | |
US10089432B2 (en) | Rule-check waiver | |
US20150143317A1 (en) | Determination Of Electromigration Features | |
US20080134129A1 (en) | Design rule checking for alternating phase shift lithography | |
US20130263074A1 (en) | Analog Rule Check Waiver | |
US9811615B2 (en) | Simultaneous retargeting of layout features based on process window simulation | |
US20120198394A1 (en) | Method For Improving Circuit Design Robustness | |
JP5340534B2 (ja) | 集積回路のためのマスク・レイアウト設計方法およびプログラムならびに集積回路のマスク・レイアウトの最適化方法 | |
US20230408901A1 (en) | Optical proximity correction for free form shapes | |
US7926005B1 (en) | Pattern-driven routing | |
US20110265054A1 (en) | Design-Rule-Check Waiver | |
US20240193338A1 (en) | Free-form layout feature retargeting | |
US10210302B2 (en) | Electrostatic damage protection circuitry verification | |
Wu et al. | Optical Proximity Correction Using a New Hyper Error Estimation Method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090213 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090722 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110906 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111108 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111115 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120130 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120403 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120712 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120720 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20120810 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130222 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130405 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160412 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |