CN101288080B - 设计掩模版图的方法、系统及传递光刻工艺设计参数的方法 - Google Patents

设计掩模版图的方法、系统及传递光刻工艺设计参数的方法 Download PDF

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Publication number
CN101288080B
CN101288080B CN2006800379581A CN200680037958A CN101288080B CN 101288080 B CN101288080 B CN 101288080B CN 2006800379581 A CN2006800379581 A CN 2006800379581A CN 200680037958 A CN200680037958 A CN 200680037958A CN 101288080 B CN101288080 B CN 101288080B
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tolerance
feature
design
layers
layer
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Chinese (zh)
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CN101288080A (zh
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S·M·曼斯费尔德
L·W·利布曼
I·格罗尔
A·克拉斯诺佩罗瓦
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International Business Machines Corp
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International Business Machines Corp
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18Manufacturability analysis or optimisation for manufacturability
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN2006800379581A 2005-10-12 2006-10-11 设计掩模版图的方法、系统及传递光刻工艺设计参数的方法 Expired - Fee Related CN101288080B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/163,264 US7266798B2 (en) 2005-10-12 2005-10-12 Designer's intent tolerance bands for proximity correction and checking
US11/163,264 2005-10-12
PCT/US2006/039701 WO2007047298A1 (en) 2005-10-12 2006-10-11 Designer's intent tolerance bands for proximity correction and checking

Publications (2)

Publication Number Publication Date
CN101288080A CN101288080A (zh) 2008-10-15
CN101288080B true CN101288080B (zh) 2012-05-23

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Country Status (7)

Country Link
US (2) US7266798B2 (enExample)
EP (1) EP1952289A4 (enExample)
JP (1) JP5243958B2 (enExample)
KR (1) KR101006264B1 (enExample)
CN (1) CN101288080B (enExample)
TW (1) TW200725348A (enExample)
WO (1) WO2007047298A1 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US7506277B1 (en) * 2005-07-28 2009-03-17 Cadence Design Systems, Inc. Method and mechanism for implementing DFM aware cells for an electronic design
US7530037B2 (en) * 2005-10-26 2009-05-05 Freescale Semiconductor, Inc. Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods
US7491594B2 (en) * 2005-10-26 2009-02-17 Freescale Semiconductor, Inc. Methods of generating planar double gate transistor shapes
US7458060B2 (en) * 2005-12-30 2008-11-25 Lsi Logic Corporation Yield-limiting design-rules-compliant pattern library generation and layout inspection
US7503028B2 (en) * 2006-01-10 2009-03-10 International Business Machines Corporation Multilayer OPC for design aware manufacturing
US7448008B2 (en) * 2006-08-29 2008-11-04 International Business Machines Corporation Method, system, and program product for automated verification of gating logic using formal verification
US7448018B2 (en) * 2006-09-12 2008-11-04 International Business Machines Corporation System and method for employing patterning process statistics for ground rules waivers and optimization
US7765518B2 (en) * 2008-03-20 2010-07-27 International Business Machines Corporation System and method for implementing optical rule checking to identify and quantify corner rounding errors
US8136054B2 (en) * 2009-01-29 2012-03-13 Synopsys, Inc. Compact abbe's kernel generation using principal component analysis
US20110047519A1 (en) * 2009-05-11 2011-02-24 Juan Andres Torres Robles Layout Content Analysis for Source Mask Optimization Acceleration
US8281263B2 (en) * 2009-12-17 2012-10-02 International Business Machines Corporation Propagating design tolerances to shape tolerances for lithography
US8331646B2 (en) 2009-12-23 2012-12-11 International Business Machines Corporation Optical proximity correction for transistors using harmonic mean of gate length
US8631379B2 (en) * 2010-02-09 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Decomposing integrated circuit layout
US8392871B2 (en) 2010-04-30 2013-03-05 International Business Machines Corporation Decomposition with multiple exposures in a process window based OPC flow using tolerance bands
US8415077B2 (en) 2010-08-13 2013-04-09 International Business Machines Corporation Simultaneous optical proximity correction and decomposition for double exposure lithography
US8875063B2 (en) 2010-10-11 2014-10-28 International Business Machines Corporation Mask layout formation
US8381141B2 (en) * 2010-10-28 2013-02-19 International Business Machines Corporation Method and system for comparing lithographic processing conditions and or data preparation processes
US8298953B2 (en) 2010-12-20 2012-10-30 Infineon Technologies Ag Method for defining a separating structure within a semiconductor device
US8365108B2 (en) 2011-01-06 2013-01-29 International Business Machines Corporation Generating cut mask for double-patterning process
US9330223B2 (en) 2012-09-28 2016-05-03 International Business Machines Corporation Optical rule checking for detecting at risk structures for overlay issues
US9250535B2 (en) 2013-03-15 2016-02-02 International Business Machines Corporation Source, target and mask optimization by incorporating countour based assessments and integration over process variations
US9262578B2 (en) 2014-04-25 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit manufacturing
CN108009352A (zh) * 2017-11-30 2018-05-08 上海华力微电子有限公司 一种光刻版图的填充流程及光刻掩膜的设计方法
CN113050389B (zh) * 2021-03-30 2022-12-02 长鑫存储技术有限公司 光刻工艺条件添加方法及装置、设计系统、介质和设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1116771A (zh) * 1994-05-07 1996-02-14 现代电子产业株式会社 制造半导体器件的方法
CN1146072A (zh) * 1995-06-30 1997-03-26 现代电子产业株式会社 用于制造半导体器件的方法
US5958635A (en) * 1997-10-20 1999-09-28 Motorola, Inc. Lithographic proximity correction through subset feature modification
US20050076316A1 (en) * 2003-10-07 2005-04-07 Fortis Systems Inc. Design-manufacturing interface via a unified model

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3466852B2 (ja) * 1997-02-18 2003-11-17 株式会社東芝 半導体装置の製造方法
US6557162B1 (en) * 2000-09-29 2003-04-29 Numerical Technologies, Inc. Method for high yield reticle formation
US6553559B2 (en) 2001-01-05 2003-04-22 International Business Machines Corporation Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions
US6578190B2 (en) 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images
JP2003043666A (ja) * 2001-08-03 2003-02-13 Matsushita Electric Ind Co Ltd 回路設計パターンの評価方法
JP2003142584A (ja) 2001-11-05 2003-05-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法
JP2003322945A (ja) * 2002-05-01 2003-11-14 Mitsubishi Electric Corp レイアウトパターンデータの補正装置
US7302672B2 (en) * 2002-07-12 2007-11-27 Cadence Design Systems, Inc. Method and system for context-specific mask writing
CN100403518C (zh) * 2002-08-06 2008-07-16 松下电器产业株式会社 半导体装置及其制造方法、生成该装置图案的装置和方法
US7313508B2 (en) * 2002-12-27 2007-12-25 Lsi Corporation Process window compliant corrections of design layout
US6928634B2 (en) 2003-01-02 2005-08-09 Yuri Granik Matrix optical process correction
EP1513012B1 (en) 2003-09-05 2008-02-20 ASML MaskTools B.V. Method and apparatus for performing model based placement of phase-balanced scattering bars for sub-wavelength optical lithography
JP4068541B2 (ja) 2003-09-25 2008-03-26 株式会社東芝 集積回路パターン検証装置と検証方法
US7269817B2 (en) * 2004-02-10 2007-09-11 International Business Machines Corporation Lithographic process window optimization under complex constraints on edge placement
JP2007536581A (ja) * 2004-05-07 2007-12-13 メンター・グラフィクス・コーポレーション プロセス変動バンドを用いた集積回路レイアウト設計法
US7908572B2 (en) * 2004-10-15 2011-03-15 Takumi Technology Corporation Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity
US7260814B2 (en) * 2004-12-14 2007-08-21 Lsi Corporation OPC edge correction based on a smoothed mask design
US7284231B2 (en) * 2004-12-21 2007-10-16 Freescale Semiconductor, Inc. Layout modification using multilayer-based constraints
US7914949B2 (en) * 2005-02-24 2011-03-29 International Business Machines Corporation Method for testing a photomask
JP2007102207A (ja) * 2005-09-08 2007-04-19 Takumi Technology Corp 複雑度低減のためのルールベース光学近接効果補正における可変バイアス・ルールの作成および適用

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1116771A (zh) * 1994-05-07 1996-02-14 现代电子产业株式会社 制造半导体器件的方法
CN1146072A (zh) * 1995-06-30 1997-03-26 现代电子产业株式会社 用于制造半导体器件的方法
US5958635A (en) * 1997-10-20 1999-09-28 Motorola, Inc. Lithographic proximity correction through subset feature modification
US20050076316A1 (en) * 2003-10-07 2005-04-07 Fortis Systems Inc. Design-manufacturing interface via a unified model

Also Published As

Publication number Publication date
US7607114B2 (en) 2009-10-20
EP1952289A4 (en) 2009-07-29
EP1952289A1 (en) 2008-08-06
CN101288080A (zh) 2008-10-15
TW200725348A (en) 2007-07-01
US20070261013A1 (en) 2007-11-08
WO2007047298A1 (en) 2007-04-26
KR101006264B1 (ko) 2011-01-06
JP5243958B2 (ja) 2013-07-24
KR20080067624A (ko) 2008-07-21
US7266798B2 (en) 2007-09-04
JP2009511988A (ja) 2009-03-19
US20070083847A1 (en) 2007-04-12

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