JP5204504B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5204504B2
JP5204504B2 JP2008025212A JP2008025212A JP5204504B2 JP 5204504 B2 JP5204504 B2 JP 5204504B2 JP 2008025212 A JP2008025212 A JP 2008025212A JP 2008025212 A JP2008025212 A JP 2008025212A JP 5204504 B2 JP5204504 B2 JP 5204504B2
Authority
JP
Japan
Prior art keywords
circuit
clock signal
film
reference clock
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008025212A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008219877A5 (enExample
JP2008219877A (ja
Inventor
義元 黒川
隆之 池田
正己 遠藤
洋樹 傳保
大輔 河江
卓之 井上
宗広 上妻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008025212A priority Critical patent/JP5204504B2/ja
Publication of JP2008219877A publication Critical patent/JP2008219877A/ja
Publication of JP2008219877A5 publication Critical patent/JP2008219877A5/ja
Application granted granted Critical
Publication of JP5204504B2 publication Critical patent/JP5204504B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Thin Film Transistor (AREA)
JP2008025212A 2007-02-08 2008-02-05 半導体装置 Expired - Fee Related JP5204504B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008025212A JP5204504B2 (ja) 2007-02-08 2008-02-05 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007029287 2007-02-08
JP2007029287 2007-02-08
JP2008025212A JP5204504B2 (ja) 2007-02-08 2008-02-05 半導体装置

Publications (3)

Publication Number Publication Date
JP2008219877A JP2008219877A (ja) 2008-09-18
JP2008219877A5 JP2008219877A5 (enExample) 2011-02-03
JP5204504B2 true JP5204504B2 (ja) 2013-06-05

Family

ID=39401148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008025212A Expired - Fee Related JP5204504B2 (ja) 2007-02-08 2008-02-05 半導体装置

Country Status (4)

Country Link
US (1) US7639058B2 (enExample)
EP (1) EP1956480B1 (enExample)
JP (1) JP5204504B2 (enExample)
KR (1) KR101428787B1 (enExample)

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GB2463074B (en) * 2008-09-02 2010-12-22 Ip Access Ltd Communication unit and method for selective frequency synchronisation in a cellular communication network
US8386829B2 (en) * 2009-06-17 2013-02-26 Macronix International Co., Ltd. Automatic internal trimming calibration method to compensate process variation
US20110285421A1 (en) * 2010-05-24 2011-11-24 Alexander Roger Deas Synchronous logic system secured against side-channel attack
US8427194B2 (en) * 2010-05-24 2013-04-23 Alexander Roger Deas Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram
KR101162259B1 (ko) * 2010-12-03 2012-07-04 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 구동 방법
US10191466B2 (en) 2015-01-28 2019-01-29 Lam Research Corporation Systems and methods for synchronizing execution of recipe sets
US9509318B2 (en) * 2015-03-13 2016-11-29 Qualcomm Incorporated Apparatuses, methods, and systems for glitch-free clock switching
US10930205B2 (en) 2016-05-19 2021-02-23 Semiconductor Energy Laboratory Co., Ltd. Display system and moving object
CN110088823B (zh) 2016-12-23 2023-06-30 株式会社半导体能源研究所 数据转换电路及显示装置
JP6828482B2 (ja) * 2017-02-08 2021-02-10 オムロン株式会社 制御システム、およびパルス出力装置
US10200192B2 (en) 2017-04-19 2019-02-05 Seagate Technology Llc Secure execution environment clock frequency hopping
US10459477B2 (en) 2017-04-19 2019-10-29 Seagate Technology Llc Computing system with power variation attack countermeasures
US10270586B2 (en) 2017-04-25 2019-04-23 Seagate Technology Llc Random time generated interrupts in a cryptographic hardware pipeline circuit
US10771236B2 (en) 2017-05-03 2020-09-08 Seagate Technology Llc Defending against a side-channel information attack in a data storage device
US10511433B2 (en) 2017-05-03 2019-12-17 Seagate Technology Llc Timing attack protection in a cryptographic processing system
US11308239B2 (en) 2018-03-30 2022-04-19 Seagate Technology Llc Jitter attack protection circuit
US10785016B2 (en) * 2018-07-25 2020-09-22 Silicon Laboratories, Inc. Countermeasure for power injection security attack
WO2021094844A1 (ja) 2019-11-11 2021-05-20 株式会社半導体エネルギー研究所 情報処理装置、および情報処理装置の動作方法
US11057001B2 (en) 2020-06-14 2021-07-06 Intel Corporation Apparatus, system, and method of distributing a reset signal to a plurality of PHY chains
US11762993B2 (en) * 2021-04-12 2023-09-19 Nxp B.V. Securing cryptographic operations from side channel attacks using a chaotic oscillator

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
JPH01112819A (ja) * 1987-10-26 1989-05-01 Fujitsu Ltd クロック生成回路の動作補償方式
JPH04281617A (ja) * 1991-03-08 1992-10-07 Victor Co Of Japan Ltd 基準クロック発生回路
US5155748A (en) * 1991-04-04 1992-10-13 Zenith Electronics Corporation Programmable multi-source IR detector
JP3181396B2 (ja) 1992-09-29 2001-07-03 沖電気工業株式会社 クロック発生回路
JPH07154243A (ja) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp 電子式時計装置ならびに補正値決定装置および方法
US6343364B1 (en) * 2000-07-13 2002-01-29 Schlumberger Malco Inc. Method and device for local clock generation using universal serial bus downstream received signals DP and DM
JP2002305443A (ja) 2001-04-06 2002-10-18 Texas Instr Japan Ltd タイマー回路
JP2003198874A (ja) * 2001-12-26 2003-07-11 Nec Corp システムクロック生成回路
US6928127B2 (en) * 2003-03-11 2005-08-09 Atheros Communications, Inc. Frequency synthesizer with prescaler
US7282937B2 (en) 2003-12-31 2007-10-16 Intel Corporation On-chip frequency degradation compensation
WO2006118284A1 (en) * 2005-04-27 2006-11-09 Semiconductor Energy Laboratory Co., Ltd. Pll circuit and semiconductor device having the same
JP4823597B2 (ja) 2005-07-25 2011-11-24 オリンパスメディカルシステムズ株式会社 医療用制御装置
EP1748344A3 (en) * 2005-07-29 2015-12-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
EP1873959A3 (en) * 2006-06-30 2012-07-25 Semiconductor Energy Laboratory Co., Ltd. Clock synchronization circuit and semiconductor device provided therewith
KR101381359B1 (ko) 2006-08-31 2014-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 클록 생성 회로 및 이 클록 생성 회로를 구비한 반도체장치

Also Published As

Publication number Publication date
EP1956480A1 (en) 2008-08-13
EP1956480B1 (en) 2012-04-18
KR101428787B1 (ko) 2014-08-08
US7639058B2 (en) 2009-12-29
JP2008219877A (ja) 2008-09-18
KR20080074730A (ko) 2008-08-13
US20080211561A1 (en) 2008-09-04

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