KR101428787B1 - 클록 신호 생성 회로 및 반도체 장치 - Google Patents

클록 신호 생성 회로 및 반도체 장치 Download PDF

Info

Publication number
KR101428787B1
KR101428787B1 KR1020080006679A KR20080006679A KR101428787B1 KR 101428787 B1 KR101428787 B1 KR 101428787B1 KR 1020080006679 A KR1020080006679 A KR 1020080006679A KR 20080006679 A KR20080006679 A KR 20080006679A KR 101428787 B1 KR101428787 B1 KR 101428787B1
Authority
KR
South Korea
Prior art keywords
circuit
reset signal
clock signal
signal
reference clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020080006679A
Other languages
English (en)
Korean (ko)
Other versions
KR20080074730A (ko
Inventor
요시유키 쿠로카와
타카유키 이케다
마사미 엔도
히로키 뎀보
다이스케 카와에
타카유키 이노우에
무네히로 코즈마
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20080074730A publication Critical patent/KR20080074730A/ko
Application granted granted Critical
Publication of KR101428787B1 publication Critical patent/KR101428787B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Thin Film Transistor (AREA)
KR1020080006679A 2007-02-08 2008-01-22 클록 신호 생성 회로 및 반도체 장치 Expired - Fee Related KR101428787B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007029287 2007-02-08
JPJP-P-2007-00029287 2007-02-08

Publications (2)

Publication Number Publication Date
KR20080074730A KR20080074730A (ko) 2008-08-13
KR101428787B1 true KR101428787B1 (ko) 2014-08-08

Family

ID=39401148

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080006679A Expired - Fee Related KR101428787B1 (ko) 2007-02-08 2008-01-22 클록 신호 생성 회로 및 반도체 장치

Country Status (4)

Country Link
US (1) US7639058B2 (enExample)
EP (1) EP1956480B1 (enExample)
JP (1) JP5204504B2 (enExample)
KR (1) KR101428787B1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11057001B2 (en) 2020-06-14 2021-07-06 Intel Corporation Apparatus, system, and method of distributing a reset signal to a plurality of PHY chains

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2463074B (en) * 2008-09-02 2010-12-22 Ip Access Ltd Communication unit and method for selective frequency synchronisation in a cellular communication network
US8386829B2 (en) * 2009-06-17 2013-02-26 Macronix International Co., Ltd. Automatic internal trimming calibration method to compensate process variation
US20110285421A1 (en) * 2010-05-24 2011-11-24 Alexander Roger Deas Synchronous logic system secured against side-channel attack
US8427194B2 (en) * 2010-05-24 2013-04-23 Alexander Roger Deas Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram
KR101162259B1 (ko) * 2010-12-03 2012-07-04 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 구동 방법
US10191466B2 (en) 2015-01-28 2019-01-29 Lam Research Corporation Systems and methods for synchronizing execution of recipe sets
US9509318B2 (en) * 2015-03-13 2016-11-29 Qualcomm Incorporated Apparatuses, methods, and systems for glitch-free clock switching
US10930205B2 (en) 2016-05-19 2021-02-23 Semiconductor Energy Laboratory Co., Ltd. Display system and moving object
CN110088823B (zh) 2016-12-23 2023-06-30 株式会社半导体能源研究所 数据转换电路及显示装置
JP6828482B2 (ja) * 2017-02-08 2021-02-10 オムロン株式会社 制御システム、およびパルス出力装置
US10200192B2 (en) 2017-04-19 2019-02-05 Seagate Technology Llc Secure execution environment clock frequency hopping
US10459477B2 (en) 2017-04-19 2019-10-29 Seagate Technology Llc Computing system with power variation attack countermeasures
US10270586B2 (en) 2017-04-25 2019-04-23 Seagate Technology Llc Random time generated interrupts in a cryptographic hardware pipeline circuit
US10771236B2 (en) 2017-05-03 2020-09-08 Seagate Technology Llc Defending against a side-channel information attack in a data storage device
US10511433B2 (en) 2017-05-03 2019-12-17 Seagate Technology Llc Timing attack protection in a cryptographic processing system
US11308239B2 (en) 2018-03-30 2022-04-19 Seagate Technology Llc Jitter attack protection circuit
US10785016B2 (en) * 2018-07-25 2020-09-22 Silicon Laboratories, Inc. Countermeasure for power injection security attack
WO2021094844A1 (ja) 2019-11-11 2021-05-20 株式会社半導体エネルギー研究所 情報処理装置、および情報処理装置の動作方法
US11762993B2 (en) * 2021-04-12 2023-09-19 Nxp B.V. Securing cryptographic operations from side channel attacks using a chaotic oscillator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167361A1 (en) 2001-04-06 2002-11-14 Kouzou Ichimaru Timer circuit
US20050140418A1 (en) 2003-12-31 2005-06-30 Ravisangar Muniandy On-chip frequency degradation compensation

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01112819A (ja) * 1987-10-26 1989-05-01 Fujitsu Ltd クロック生成回路の動作補償方式
JPH04281617A (ja) * 1991-03-08 1992-10-07 Victor Co Of Japan Ltd 基準クロック発生回路
US5155748A (en) * 1991-04-04 1992-10-13 Zenith Electronics Corporation Programmable multi-source IR detector
JP3181396B2 (ja) 1992-09-29 2001-07-03 沖電気工業株式会社 クロック発生回路
JPH07154243A (ja) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp 電子式時計装置ならびに補正値決定装置および方法
US6343364B1 (en) * 2000-07-13 2002-01-29 Schlumberger Malco Inc. Method and device for local clock generation using universal serial bus downstream received signals DP and DM
JP2003198874A (ja) * 2001-12-26 2003-07-11 Nec Corp システムクロック生成回路
US6928127B2 (en) * 2003-03-11 2005-08-09 Atheros Communications, Inc. Frequency synthesizer with prescaler
WO2006118284A1 (en) * 2005-04-27 2006-11-09 Semiconductor Energy Laboratory Co., Ltd. Pll circuit and semiconductor device having the same
JP4823597B2 (ja) 2005-07-25 2011-11-24 オリンパスメディカルシステムズ株式会社 医療用制御装置
EP1748344A3 (en) * 2005-07-29 2015-12-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
EP1873959A3 (en) * 2006-06-30 2012-07-25 Semiconductor Energy Laboratory Co., Ltd. Clock synchronization circuit and semiconductor device provided therewith
KR101381359B1 (ko) 2006-08-31 2014-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 클록 생성 회로 및 이 클록 생성 회로를 구비한 반도체장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167361A1 (en) 2001-04-06 2002-11-14 Kouzou Ichimaru Timer circuit
US20050140418A1 (en) 2003-12-31 2005-06-30 Ravisangar Muniandy On-chip frequency degradation compensation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11057001B2 (en) 2020-06-14 2021-07-06 Intel Corporation Apparatus, system, and method of distributing a reset signal to a plurality of PHY chains

Also Published As

Publication number Publication date
EP1956480A1 (en) 2008-08-13
JP5204504B2 (ja) 2013-06-05
EP1956480B1 (en) 2012-04-18
US7639058B2 (en) 2009-12-29
JP2008219877A (ja) 2008-09-18
KR20080074730A (ko) 2008-08-13
US20080211561A1 (en) 2008-09-04

Similar Documents

Publication Publication Date Title
KR101428787B1 (ko) 클록 신호 생성 회로 및 반도체 장치
KR101381359B1 (ko) 클록 생성 회로 및 이 클록 생성 회로를 구비한 반도체장치
KR101373532B1 (ko) 반도체장치 및 상기 반도체장치를 구비하는 전자 장치
US7612598B2 (en) Clock signal generation circuit and semiconductor device
KR101394098B1 (ko) 반도체 장치 및 그 구동 방법
KR101358951B1 (ko) 클록 동기 회로 및 그것을 구비한 반도체장치
JP5063256B2 (ja) クロック生成回路、クロック生成回路が有するカウンター回路、及び半導体装置
JP5204998B2 (ja) 半導体装置
JP5348859B2 (ja) 受信回路及び半導体装置
HK1125504A (en) Clock signal generation circuit and semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20170704

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20180718

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20190718

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20210805

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20210805