JP5184497B2 - 電子部品内装型プリント基板及びその製造方法 - Google Patents
電子部品内装型プリント基板及びその製造方法 Download PDFInfo
- Publication number
- JP5184497B2 JP5184497B2 JP2009275331A JP2009275331A JP5184497B2 JP 5184497 B2 JP5184497 B2 JP 5184497B2 JP 2009275331 A JP2009275331 A JP 2009275331A JP 2009275331 A JP2009275331 A JP 2009275331A JP 5184497 B2 JP5184497 B2 JP 5184497B2
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- Prior art keywords
- electronic component
- flexible film
- layer
- insulating layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
200 絶縁層
300 電子部品
350 接続端子
370 接続部材
400 回路層
450 接続パターン
500 ビア
530 ビア
550 回路パターン
600 ビルドアップ層
700 ソルダレジスト層
1000、2000 電子部品内装型プリント基板
Claims (10)
- フレキシブルフィルム;
前記フレキシブルフィルムの一面に積層された絶縁層;
前記フレキシブルフィルムの一面に実装されて前記絶縁層に埋め込まれた電子部品;
前記フレキシブルフィルムの一面に形成され、接続部材によって前記電子部品の接続端子と接続する接続パターンを含む回路層;及び
前記回路層に連結され、前記回路層を基準として、前記回路層の上下に向かい合って、前記フレキシブルフィルム側に前記フレキシブルフィルムを貫通する1個のビア、前記絶縁層側に前記絶縁層を貫通する1個のビア、合計2個のビア;
を含み、
前記電子部品と前記フレキシブルフィルムの間の前記接続端子周りには前記絶縁層が充填されていることを特徴とする電子部品内装型プリント基板。 - 前記フレキシブルフィルムの露出面または前記絶縁層の露出面に形成されて前記ビアと連結された回路パターンをさらに含むことを特徴とする請求項1に記載の電子部品内装型プリント基板。
- 前記フレキシブルフィルムの露出面または前記絶縁層の露出面に積層されたビルドアップ層をさらに含むことを特徴とする請求項1に記載の電子部品内装型プリント基板。
- 前記接続部材が、ソルダペーストであることを特徴とする請求項1に記載の電子部品内装型プリント基板。
- 前記フレキシブルフィルムが、ポリイミドで形成されたことを特徴とする請求項1に記載の電子部品内装型プリント基板。
- (A)フレキシブルフィルムの一面に接続パターンを含む回路層を形成する段階;
(B)前記接続パターンに電子部品の接続端子が接続部材によって接続されるように、前記電子部品をフェースダウン方式でフレキシブルフィルムの一面に実装する段階;
(C)前記電子部品を埋め込むように、前記フレキシブルフィルムの一面に液状コーティングで絶縁層を積層し、前記電子部品と前記フレキシブルフィルムの間の前記接続端子周りには前記絶縁層を充填する段階;及び
(D)前記回路層を基準として、前記回路層の上下に向かい合って、前記フレキシブルフィルム側に前記回路層と連結される前記フレキシブルフィルムを貫通する1個のビア、前記絶縁層側に前記回路層と連結される前記絶縁層を貫通する1個のビア、合計2個のビアを形成する段階;
を含むことを特徴とする電子部品内装型プリント基板の製造方法。 - 前記フレキシブルフィルムの露出面または前記絶縁層の露出面に前記ビアと連結される回路パターンを形成する段階をさらに含むことを特徴とする請求項6に記載の電子部品内装型プリント基板の製造方法。
- 前記(C)段階の後に、
前記フレキシブルフィルムの露出面または前記絶縁層の露出面にビルドアップ層を積層する段階をさらに含むことを特徴とする請求項6に記載の電子部品内装型プリント基板の製造方法。 - 前記(B)段階で、
前記接続部材が、ソルダペーストであることを特徴とする請求項6に記載の電子部品内装型プリント基板の製造方法。 - 前記(A)段階で、
前記フレキシブルフィルムが、ポリイミドで形成されたことを特徴とする請求項6に記載の電子部品内装型プリント基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2009-0096913 | 2009-10-12 | ||
KR1020090096913A KR20110039879A (ko) | 2009-10-12 | 2009-10-12 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011082471A JP2011082471A (ja) | 2011-04-21 |
JP5184497B2 true JP5184497B2 (ja) | 2013-04-17 |
Family
ID=43853935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009275331A Expired - Fee Related JP5184497B2 (ja) | 2009-10-12 | 2009-12-03 | 電子部品内装型プリント基板及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110083891A1 (ja) |
JP (1) | JP5184497B2 (ja) |
KR (1) | KR20110039879A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9613933B2 (en) | 2014-03-05 | 2017-04-04 | Intel Corporation | Package structure to enhance yield of TMI interconnections |
TWI611523B (zh) * | 2014-09-05 | 2018-01-11 | 矽品精密工業股份有限公司 | 半導體封裝件之製法 |
TWI582861B (zh) * | 2014-09-12 | 2017-05-11 | 矽品精密工業股份有限公司 | 嵌埋元件之封裝結構及其製法 |
US10231338B2 (en) | 2015-06-24 | 2019-03-12 | Intel Corporation | Methods of forming trenches in packages structures and structures formed thereby |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61196219U (ja) * | 1985-05-22 | 1986-12-06 | ||
JP3208176B2 (ja) * | 1992-05-18 | 2001-09-10 | イビデン株式会社 | 電子回路部品を埋め込んだ多層プリント配線板 |
JP2001185653A (ja) * | 1999-10-12 | 2001-07-06 | Fujitsu Ltd | 半導体装置及び基板の製造方法 |
US7141884B2 (en) * | 2003-07-03 | 2006-11-28 | Matsushita Electric Industrial Co., Ltd. | Module with a built-in semiconductor and method for producing the same |
CN1577819A (zh) * | 2003-07-09 | 2005-02-09 | 松下电器产业株式会社 | 带内置电子部件的电路板及其制造方法 |
US7358444B2 (en) * | 2004-10-13 | 2008-04-15 | Intel Corporation | Folded substrate with interposer package for integrated circuit devices |
JP4718889B2 (ja) * | 2005-04-28 | 2011-07-06 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法、多層配線基板構造体及びその製造方法 |
JP2007059821A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2008205290A (ja) * | 2007-02-21 | 2008-09-04 | Fujitsu Ltd | 部品内蔵基板及びその製造方法 |
WO2008120755A1 (ja) * | 2007-03-30 | 2008-10-09 | Nec Corporation | 機能素子内蔵回路基板及びその製造方法、並びに電子機器 |
JP5262188B2 (ja) * | 2008-02-29 | 2013-08-14 | 富士通株式会社 | 基板 |
-
2009
- 2009-10-12 KR KR1020090096913A patent/KR20110039879A/ko not_active Application Discontinuation
- 2009-12-03 JP JP2009275331A patent/JP5184497B2/ja not_active Expired - Fee Related
- 2009-12-04 US US12/631,555 patent/US20110083891A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20110083891A1 (en) | 2011-04-14 |
KR20110039879A (ko) | 2011-04-20 |
JP2011082471A (ja) | 2011-04-21 |
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