JP5153706B2 - Ecu用混成集積回路装置 - Google Patents
Ecu用混成集積回路装置 Download PDFInfo
- Publication number
- JP5153706B2 JP5153706B2 JP2009075741A JP2009075741A JP5153706B2 JP 5153706 B2 JP5153706 B2 JP 5153706B2 JP 2009075741 A JP2009075741 A JP 2009075741A JP 2009075741 A JP2009075741 A JP 2009075741A JP 5153706 B2 JP5153706 B2 JP 5153706B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- circuit unit
- wiring
- control circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Structure Of Printed Boards (AREA)
Description
11:第1の絶縁基板
12:第2の絶縁基板
2:配線
3:パワー回路部
31:スイッチング素子
32:ダイオード
4:制御回路部
41:マイクロプロセッサ
42:トランジスタ
43:演算増幅器
Claims (1)
- 絶縁基板の一方主面上に薄板状金属体を固着してなる配線を備えるとともに少なくともスイッチング素子および該スイッチング素子の動作を制御する制御素子が搭載されてなり、前記スイッチング素子を備えたパワー回路部と前記制御素子を備えた制御回路部とを有するECU用混成集積回路装置であって、
前記絶縁基板は、前記配線の固着後に、前記パワー回路部を構成する第1の絶縁基板と前記制御回路部を構成する第2の絶縁基板とに、前記配線を残してレーザ加工によって分離されており、
前記第1の絶縁基板から前記第2の絶縁基板にわたって一体に形成された前記配線によって、前記パワー回路部と前記制御回路部とが接続されていることを特徴とするECU用混成集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009075741A JP5153706B2 (ja) | 2009-03-26 | 2009-03-26 | Ecu用混成集積回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009075741A JP5153706B2 (ja) | 2009-03-26 | 2009-03-26 | Ecu用混成集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010232254A JP2010232254A (ja) | 2010-10-14 |
JP5153706B2 true JP5153706B2 (ja) | 2013-02-27 |
Family
ID=43047845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009075741A Expired - Fee Related JP5153706B2 (ja) | 2009-03-26 | 2009-03-26 | Ecu用混成集積回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5153706B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5660076B2 (ja) | 2012-04-26 | 2015-01-28 | 三菱電機株式会社 | 半導体装置とその製造方法 |
JP2015046439A (ja) * | 2013-08-27 | 2015-03-12 | アンデン株式会社 | 電気装置およびその製造方法 |
JP6154254B2 (ja) * | 2013-09-03 | 2017-06-28 | 矢崎総業株式会社 | 高圧/低圧混載型ハイブリッド集積回路 |
JPWO2018164206A1 (ja) * | 2017-03-07 | 2020-01-09 | Ngkエレクトロデバイス株式会社 | 絶縁回路基板用端子および絶縁回路基板複合体および半導体装置複合体 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62134956A (ja) * | 1985-12-09 | 1987-06-18 | Tdk Corp | パワ−用混成集積回路 |
JPS63229797A (ja) * | 1987-03-19 | 1988-09-26 | 富士通株式会社 | 厚膜集積回路の製造方法 |
JPH03141694A (ja) * | 1989-10-26 | 1991-06-17 | Aica Kogyo Co Ltd | リジッド―フレキシブル複合多層プリント配線板の製法 |
-
2009
- 2009-03-26 JP JP2009075741A patent/JP5153706B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010232254A (ja) | 2010-10-14 |
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