CN110168709B - 具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法 - Google Patents

具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法 Download PDF

Info

Publication number
CN110168709B
CN110168709B CN201780081245.3A CN201780081245A CN110168709B CN 110168709 B CN110168709 B CN 110168709B CN 201780081245 A CN201780081245 A CN 201780081245A CN 110168709 B CN110168709 B CN 110168709B
Authority
CN
China
Prior art keywords
semiconductor chip
connecting element
semiconductor
semiconductor module
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201780081245.3A
Other languages
English (en)
Other versions
CN110168709A (zh
Inventor
格奥尔格·扎伊泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of CN110168709A publication Critical patent/CN110168709A/zh
Application granted granted Critical
Publication of CN110168709B publication Critical patent/CN110168709B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92132—Sequential connecting processes the first connecting process involving a build-up interconnect
    • H01L2224/92137—Sequential connecting processes the first connecting process involving a build-up interconnect the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种半导体模块(1)，其具有：衬底(2)；半导体芯片(6)，其设置在衬底(2)上；和用于将半导体芯片(6)与印制导线(7)和/或半导体模块(1)的另外的器件电连接的第一连接元件(12)，其中，第一连接元件(12)至少在部分区域以表面贴靠半导体芯片(6)和衬底(2)以及印制导线(7)和/或另外的器件，其中，半导体模块(1)具有用于将半导体芯片(6)与印制导线(7)和/或另外的器件电连接的第二连接元件(13)，其中，第二连接元件(13)设计为线或条带。

Description

具有用于连接半导体芯片的第一和第二连接元件的半导体模 块及制造方法
技术领域
本发明涉及一种半导体模块，其具有：衬底；半导体芯片，半导体芯片布置在衬底上；和用于将半导体芯片与半导体模块的另外的半导体芯片电连接的第一连接元件，其中，第一连接元件至少在部分区域以表面贴靠半导体芯片和衬底以及另外的半导体芯片。此外，本发明涉及一种用于制造半导体模块的方法。
背景技术
当前，所关注的是如下半导体模块，其例如能够是电子装置或电力电子装置的一部分。这种半导体模块包括布置在衬底上的至少一个半导体芯片。半导体芯片与半导体模块的另外的部件电连接。例如，半导体芯片能够与一个或多个布置在衬底上的印制导线连接。此外，半导体芯片能够与另外的半导体模块的另外的组件或半导体芯片电连接。现有技术中披露了用于电接触半导体芯片的多种方法。
用于接触半导体芯片的一种通常使用的形式是键合线。但是在此，键合线在半导体芯片处的接触部位被已知为薄弱部位。这是由于，接触面比较小。此外，键合线带来如下缺点：在半导体模块之内可能出现电磁干扰，进而无法充分地确保电磁兼容性(EMV)。此外，通过键合线汇总的加载会提高温度。这能够引起膨胀进而产生热应力。这能够导致损坏。
此外，从现有技术中已知一种半导体芯片与条带(也能够称作为英语ribbon)接触。因为单个条带具有比键合线更大的横截面，所以为了实现相同的导体横截面，与键合线相比需要更少数量的条带。然而，需要更大的面才能将条带接触到半导体芯片表面上。因此不再能实现更好的载流能力。此外，没有排除射入电磁干扰，并且已经证明：半导体模块在特定的运行状态下易于振荡。
在US2007/040252 A1中公开了一种具有半导体电力芯片的半导体电力部件，其中，半导体电力芯片具有至少一个大面积的电极在其上侧和大面积的电子在其底侧。在此，上侧电极经由连接元件与扁平电阻框的内表面电阻电连接。连接元件具有键合条带，其从上侧电极延伸到内表面导体。在键合条带的上侧，还布置有从上侧电极到内表面导体的键合线。
此外，从现有技术中已知使用柔性板以接触半导体芯片。在此，半导体芯片通过预制的连接元件大面积地被接触，连接元件例如能够设计为柔性板。因此显著增大了接触面。但是，连接元件的有效横截面比键合线更小。在此，只能通过提高柔性板或连接元件的层厚度才能改进有效横截面。
DE 91 09 259 U1描述了一种具有芯片器件的电子电路设备，其在上侧具有接触面。接触面借助于导电连接元件与另外的芯片器件的所属的连接面导电地连接。连接元件能够由附着在绝缘层上的结构化的金属层构成。
另外，DE 10 2008 045 338 A1描述了一种半导体器件，其具有载体和安装在载体上的半导体芯片。另外，半导体器件包括具有第一厚度的第一导体，其被半导体芯片和载体分隔开，还包括具有第二厚度的第二导体，其被半导体芯片和载体分隔开，其中，第一厚度小于第二厚度。
但是，如果连接元件构造成薄且柔性的，则连接元件的弹性和膨胀良好，并且连接元件能够连同半导体芯片一起发生弹性形变，从而不引起连接元件的剩余形变。但是，连接元件的载流能力会由于层厚度小而不足。也能够是如下情况：即连接元件之内的温度上升被提高，从而无法充分利用半导体芯片的有效功率。但是如果提高连接元件的层厚度，则这可能导致连接元件不再具有用于在温度变换时与半导体芯片一起膨胀的足够柔性。因此无法保证足够的鲁棒性。
发明内容
本发明的目的在于，提出一种如何能够可靠地构成前文提出类型的半导体模块之内的电连接的解决方案。
根据本发明，所述目的通过根据本发明的半导体模块、以及方法来实现。
根据本发明的半导体模块包括衬底。此外，半导体模块包括半导体芯片，半导体芯片布置在衬底上。此外，半导体模块包括用于将半导体芯片与半导体模块的另外的半导体芯片电连接的第一连接元件，其中，第一连接元件至少在部分区域以表面贴靠半导体芯片和衬底以及另外的半导体芯片。最后，半导体模块包括用于将半导体芯片与另外的半导体芯片电连接的第二连接元件，其中，第二连接元件设计为线。
半导体模块例如能够用于电力电子装置。半导体模块包括能够由电绝缘材料形成的衬底。优选地，衬底由陶瓷制成。在衬底上布置有半导体芯片。也可称作为裸片(die)的半导体芯片尤其是未封装的半导体器件。半导体芯片例如能够设计为二极管、晶体管等。此外，半导体模块能够具有印制导线，印制导线布置在衬底上或印制导线施加到衬底上。此外，半导体模块能够具有另外的器件或电子器件。另外的器件是另外的半导体芯片。此外，半导体模块包括第一电连接元件。该第一电连接元件用于将半导体芯片与另外的半导体芯片电连接。在此，第一连接元件设计为，使得其以表面贴靠半导体芯片的一个区域并也贴靠衬底的一个区域。此外，第一连接元件能够以表面贴靠另一组件或印制导线的一个区域。连接元件尤其能够设计为叠层结构或设计为柔性板。
根据本发明的一个主要方面提出：半导体模块除了第一连接元件之外还具有第二连接元件。该第二连接元件也用于将半导体芯片与另外的半导体芯片连接。在此，第二连接元件设计为线。还可以提出，第二连接元件包括多个线。例如，第二连接元件能够设计为键合线。通过第二连接元件，显著改进了第一连接元件的载流能力。在此，第二连接元件尤其用于提供低电感的换向路径，由此使半导体芯片中的开关损失最小化。此外，第一连接元件带来在开关过程期间电磁干扰小的优点。通过第二连接元件，提高了半导体芯片和另外的半导体芯片之间的电连接的载流能力。因此整体上能够提供用于半导体芯片的更可靠的电连接。
另外，第一连接元件包括电绝缘的薄膜和施加在薄膜上的金属层。例如，能够借助于所谓的方法(SiPLIT-西门子平面互联技术)来提供第一连接元件。在此，可以首先将电绝缘的薄膜施加到半导体芯片、衬底以及印制导线和/或另外的半导体芯片上，使得这些薄膜贴靠这些部件。随后，薄膜能够被相应地结构化。随后能够将金属层施加到薄膜上。也能够提出：第一连接元件借助于所谓的/>技术提供。在此，金属层能够以烧结方法施加到薄膜上。借此，能够使用已知的方法来制造第一连接元件。
优选地，第二连接元件布置在第一连接元件背离半导体芯片的一侧上。因此，线或条带作为平行的电流路径安装在第一连接元件之上。这使得键合线或条带的温度上升更小。此外，线或条带与第一连接元件电连接。因此，能够改进线或条带的接触。当仅使用线或条带而没有第一连接元件时，这些线或条带通常直接与半导体芯片连接。由于在此形成的接触面比较小，可能出现损坏。因此能够提供具有鲁棒性的电连接。
根据另一实施方式，第一连接元件可以设计为柔性的。原则上，第一连接元件能够通过如下方式提供：将柔性的能导电的板施加到半导体模块的待连接的部件上。因此例如能够在电连接时显著地增大接触面。此外，能够可靠地补偿与温度波动相关的膨胀。
还有利的是：第二连接元件至少在部分区域具有预设的曲率。换言之，线能够在部分区域设计为弓形的。通过第二连接元件的该设计方案能够实现：第二连接元件具有一定弹性。因此，能够补偿由于温差引起的半导体模块的单个部件的膨胀。
根据另一实施方式，半导体模块具有至少一个绝缘元件，该绝缘元件布置在半导体芯片和第一连接元件之间。该绝缘元件优选由电绝缘材料制成。特别地，该绝缘元件能够布置在半导体芯片的边缘区域处。在半导体芯片的边缘区域处存在半导体芯片的结构负责止挡功能的相应的结构。通过绝缘元件能够防止，结构被电连接。因此能够借助于绝缘元件提供可靠的边缘绝缘。
还有利的是，半导体模块具有底板，底板在衬底背离半导体芯片的一侧上与衬底连接。例如，底板能够由金属构成。底板也能够由包括碳化硅和/或铝的材料形成。借助于底板能够可靠地排出在半导体模块或半导体芯片运行时产生的热量。
此外能够提出，半导体模块具有控制回路。在控制回路中于是能够仅使用第一连接元件用于电连接。在控制回路中通常存在更低的电流负载。因此，排除或最小化电磁干扰或影像。
半导体模块能够被用于电力电子装置或另外的电子部件中。也能够提出，电力电子装置或电子部件包括多个半导体模块。半导体芯片尤其能够设计为晶体管、例如设计为MOSFET或设计为IGBT。半导体芯片也能够设计为功率半导体器件。
根据本发明的方法用于制造半导体模块。在此，提供衬底。此外，在衬底上布置半导体芯片。此外，提供用于将半导体芯片与半导体模块的另外的半导体芯片电连接的第一连接元件，使得第一连接元件至少在部分区域以表面贴靠半导体芯片和衬底以及另外的半导体芯片。此外，提供用于半导体芯片与另外的半导体芯片电连接的第二连接元件，其中，第二连接元件设计为线。借助于根据本发明的方法能够制造根据本发明的半导体模块。另外，为了提供第一连接元件将金属层施加到电绝缘薄膜上。
在此尤其提出，首先将第一连接元件至少在部分区域施加到半导体芯片和衬底上以及施加到另外的半导体芯片上，并且随后第二连接元件至少在部分区域施加到第一连接元件上。因此，与已知的第一连接元件或柔性板相比，第一连接元件能够设计具有更小的层厚度。由此简化了制造的工艺。此外，与已知的连接元件相比，第一连接元件具有更高的弹性并且还能够更好地施加到半导体芯片的表面上。此外，也在热膨胀系数不同的情况下，能够保证第一连接元件与半导体芯片之间的可靠连接。因此整体上能够提供具有鲁棒性且可靠的连接。
根据另一实施方式，为了提供第一连接元件借助烧结、焊接和/或电镀技术将金属层施加到薄膜上。如已经阐述的那样，第一连接元件能够设计为层压的结构或设计为柔性板。第一连接元件能够包括电绝缘薄膜，在该电绝缘薄膜上施加有金属层。金属层例如能够由铜、铝、金等制成。因此能够以简单且可靠的方式制造第一连接元件。
参考根据本发明的半导体模块提出的优选的实施方式和其优选相应地适用于根据本发明的方法。
附图说明
现在，根据优选的实施例以及参考所附的附图详细阐述本发明。在此示出：
图1示出根据现有技术的半导体模块的第一实施方式；
图2示出根据现有技术的半导体模块的另一实施方式；和
图3示出具有第一连接元件和第二连接元件的半导体模块。
在附图中相同的和功能相同的元件设有相同的附图标记。
具体实施方式
图1示出根据现有技术的半导体模块的第一实施方式。在此，示出半导体模块1的剖切侧视图。半导体模块1包括衬底2，该衬底由电绝缘材料形成。例如，衬底2能够由陶瓷形成。此外，半导体模块1包括底板3，其与衬底2的下侧4连接。底板3能够由金属形成。在衬底2的上侧5上存在半导体芯片6。半导体芯片6也能够称作为裸片。此外，在衬底2的上侧5上存在印制导线7。在此，半导体芯片6与印制导线借助于键合线8电连接。在此，键合线8布置在半导体芯片6的上侧9上。半导体芯片6还能够在其上侧上与导电层电连接。经由该导电层能够将半导体芯片6与另外的器件连接或激励另外的器件。
图2示出根据现有技术的半导体模块1的另一实施方式。与根据图1的半导体模块1相比，半导体芯片6和印制导线7与柔性的连接元件10彼此连接。该柔性的连接元件10以表面贴靠在半导体芯片6、衬底2的以及印制导线7的区域上。连接元件10例如能够通过如下方式提供：即将薄膜施加到印制导线7、衬底2和半导体芯片6上。随后，薄膜能够被相应地结构化。随后能够将金属层施加到结构化的薄膜上。也能够提出，连接元件10设计为柔性的导电板，板施加到印制导线7、衬底2以及半导体芯片6上。此外，设有绝缘元件11，绝缘元件布置在半导体芯片6和连接元件10之间。该绝缘元件11用于边缘绝缘。
图3示出另一个半导体模块1。在此，半导体模块包括第一连接元件12，该第一连接元件根据图2中示出的连接元件的类型来设计。在此，与连接元件相比，第一连接元件12具有更小的层厚度。此外，半导体模块1具有第二连接元件13，该第二连接元件当前设计为键合线8。在此，第二连接元件施加到第一连接元件12的上侧14上。
因此，第二连接元件13或键合线8是在柔性板或第一连接元件12之上的平行的电流路径。在此，第一连接元件12形成低电感的换向路径，其用于半导体芯片6中无摩擦地换向。通过第二连接元件13或键合线能够提高载流能力。因此，能够在半导体芯片6和印制导线7之间提供可靠且具有鲁棒性的连接。该连接也用于将半导体芯片6与半导体模块1的另外的半导体芯片连接。

Claims (12)

1.一种半导体模块(1)，具有：衬底(2)；半导体芯片(6)，所述半导体芯片设置在所述衬底(2)上；和第一连接元件(12)，用于将所述半导体芯片(6)与所述半导体模块(1)的另外的半导体芯片电连接；其中，所述第一连接元件(12)至少在部分区域以表面贴靠所述半导体芯片(6)和所述衬底(2)以及所述另外的半导体芯片，并且其中，所述第一连接元件(12)包括电绝缘薄膜和施加在所述薄膜上的金属层，其特征在于，所述半导体模块(1)具有第二连接元件(13)，所述第二连接元件用于将所述半导体芯片(6)与所述另外的半导体芯片电连接，其中，所述第二连接元件(13)设计为线，所述半导体模块(1)还具有控制回路，在所述控制回路中能够仅将所述第一连接元件(12)用于所述电连接。
2.根据权利要求1所述的半导体模块(1)，其特征在于，所述第二连接元件(13)布置在所述第一连接元件(12)背离所述半导体芯片(6)的一侧(14)上。
3.根据权利要求1或2所述的半导体模块(1)，其特征在于，所述第一连接元件(12)设计为柔性的。
4.根据权利要求1或2所述的半导体模块(1)，其特征在于，所述第二连接元件(13)至少在部分区域具有预设的曲率。
5.根据权利要求3所述的半导体模块(1)，其特征在于，所述第二连接元件(13)至少在部分区域具有预设的曲率。
6.根据权利要求1或2所述的半导体模块(1)，其特征在于，所述半导体模块(1)具有至少一个绝缘元件(11)，所述绝缘元件布置在所述半导体芯片(6)与所述第一连接元件(12)之间。
7.根据权利要求5所述的半导体模块(1)，其特征在于，所述半导体模块(1)具有至少一个绝缘元件(11)，所述绝缘元件布置在所述半导体芯片(6)与所述第一连接元件(12)之间。
8.根据权利要求1或2所述的半导体模块(1)，其特征在于，所述半导体模块(1)具有底板(3)，所述底板在所述衬底(2)背离所述半导体芯片(6)的一侧(4)上与所述衬底(2)连接。
9.根据权利要求7所述的半导体模块(1)，其特征在于，所述半导体模块(1)具有底板(3)，所述底板在所述衬底(2)背离所述半导体芯片(6)的一侧(4)上与所述衬底(2)连接。
10.一种用于制造半导体模块(1)的方法，其中，提供衬底(2)，在所述衬底(2)上布置半导体芯片(6)，并提供用于将所述半导体芯片(6)与所述半导体模块(1)的另外的半导体芯片电连接的第一连接元件(12)，使得所述第一连接元件(12)至少在部分区域以表面贴靠所述半导体芯片(6)和所述衬底(2)以及所述另外的半导体芯片，并且其中，为了提供所述第一连接元件(12)将金属层施加到电绝缘的薄膜上，其特征在于，提供用于将所述半导体芯片(6)与所述另外的半导体芯片电连接的第二连接元件(13)，其中，所述第二连接元件(13)设计为线，所述半导体模块(1)具有控制回路，在所述控制回路中能够仅将所述第一连接元件(12)用于所述电连接。
11.根据权利要求10所述的方法，其特征在于，首先将所述第一连接元件(12)至少在部分区域施加到所述半导体芯片(6)和所述衬底(2)以及所述另外的半导体芯片上，并且随后将所述第二连接元件(13)至少在部分区域施加到所述第一连接元件(12)上。
12.根据权利要求10或11所述的方法，其特征在于，为了提供所述第一连接元件(12)，借助烧结、焊接和/或电镀技术将所述金属层施加到所述薄膜上。
CN201780081245.3A 2016-12-28 2017-11-28 具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法 Active CN110168709B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP16207050.2 2016-12-28
EP16207050.2A EP3343600A1 (de) 2016-12-28 2016-12-28 Halbleitermodul mit einem ersten und einem zweiten verbindungselement zum verbinden eines halbleiterchips sowie herstellungsverfahren
PCT/EP2017/080640 WO2018121949A1 (de) 2016-12-28 2017-11-28 Halbleitermodul mit einem ersten und einem zweiten verbindungselement zum verbinden eines halbleiterchips sowie herstellungsverfahren

Publications (2)

Publication Number Publication Date
CN110168709A CN110168709A (zh) 2019-08-23
CN110168709B true CN110168709B (zh) 2023-10-20

Family

ID=57749749

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780081245.3A Active CN110168709B (zh) 2016-12-28 2017-11-28 具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法

Country Status (5)

Country Link
US (1) US11837571B2 (zh)
EP (2) EP3343600A1 (zh)
JP (1) JP7026688B2 (zh)
CN (1) CN110168709B (zh)
WO (1) WO2018121949A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
WO2009034008A2 (de) * 2007-09-10 2009-03-19 Siemens Aktiengesellschaft Bandverfahren für elektronische bauelemente, module und led-anwendungen
JP2012049528A (ja) * 2010-08-26 2012-03-08 Semikron Elektronik Gmbh & Co Kg 可撓な接続デバイスを備えたパワーアセンブリ

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE9109295U1 (de) * 1991-04-11 1991-10-10 Export-Contor Außenhandelsgesellschaft mbH, 8500 Nürnberg Elektronische Schaltungsanordnung
JP3360778B2 (ja) 1995-08-10 2002-12-24 サンケン電気株式会社 半導体装置の半田付け方法
JP3674333B2 (ja) 1998-09-11 2005-07-20 株式会社日立製作所 パワー半導体モジュール並びにそれを用いた電動機駆動システム
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US20040217488A1 (en) 2003-05-02 2004-11-04 Luechinger Christoph B. Ribbon bonding
JP2006066704A (ja) 2004-08-27 2006-03-09 Toyota Motor Corp 半導体装置
US7479691B2 (en) * 2005-03-16 2009-01-20 Infineon Technologies Ag Power semiconductor module having surface-mountable flat external contacts and method for producing the same
US20070035019A1 (en) * 2005-08-15 2007-02-15 Semiconductor Components Industries, Llc. Semiconductor component and method of manufacture
DE102005039165B4 (de) * 2005-08-17 2010-12-02 Infineon Technologies Ag Draht- und streifengebondetes Halbleiterleistungsbauteil und Verfahren zu dessen Herstellung
DE102005041174A1 (de) * 2005-08-30 2007-03-15 Infineon Technologies Ag Leistungshalbleiterbauteil mit Leitungen innerhalb eines Gehäuses
DE102007033288A1 (de) * 2007-07-17 2009-01-22 Siemens Ag Elektronisches Bauelement und Vorrichtung mit hoher Isolationsfestigkeit sowie Verfahren zu deren Herstellung
US9059083B2 (en) 2007-09-14 2015-06-16 Infineon Technologies Ag Semiconductor device
US7838978B2 (en) * 2007-09-19 2010-11-23 Infineon Technologies Ag Semiconductor device
US7626249B2 (en) * 2008-01-10 2009-12-01 Fairchild Semiconductor Corporation Flex clip connector for semiconductor device
US8120915B2 (en) 2008-08-18 2012-02-21 General Electric Company Integral heat sink with spiral manifolds
JP2010141293A (ja) * 2008-11-14 2010-06-24 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
TWI447878B (zh) * 2009-08-28 2014-08-01 Great Team Backend Foundry Inc 增加通路及降低電阻之電晶體連接結構
US8008785B2 (en) 2009-12-22 2011-08-30 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
KR101118711B1 (ko) 2010-12-17 2012-03-12 테세라, 인코포레이티드 중앙 콘택을 구비한 적층형 마이크로전자 조립체

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
WO2009034008A2 (de) * 2007-09-10 2009-03-19 Siemens Aktiengesellschaft Bandverfahren für elektronische bauelemente, module und led-anwendungen
JP2012049528A (ja) * 2010-08-26 2012-03-08 Semikron Elektronik Gmbh & Co Kg 可撓な接続デバイスを備えたパワーアセンブリ

Also Published As

Publication number Publication date
US11837571B2 (en) 2023-12-05
EP3535779A1 (de) 2019-09-11
US20190348390A1 (en) 2019-11-14
WO2018121949A1 (de) 2018-07-05
JP2020503688A (ja) 2020-01-30
CN110168709A (zh) 2019-08-23
EP3343600A1 (de) 2018-07-04
JP7026688B2 (ja) 2022-02-28

Similar Documents

Publication Publication Date Title
EP3226292B1 (en) Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device
US20140167237A1 (en) Power module package
US20170221853A1 (en) Electrode terminal, semiconductor device, and power conversion apparatus
KR950024311A (ko) 얇은 회로기판과 반도체 장치가 접합되어 있는 열전도성 지지부재를 갖춘 전자 패키지
US6882538B1 (en) Intelligent power module
US20140110833A1 (en) Power module package
US20150380331A1 (en) Semiconductor device
EP3232468B1 (en) Heat dissipation structure of a semiconductor device
US20170194296A1 (en) Semiconductor module
KR101343199B1 (ko) 반도체 패키지
US10937767B2 (en) Chip packaging method and device with packaged chips
US11942449B2 (en) Semiconductor arrangement and method for producing the same
US20200357731A1 (en) Power semiconductor module arrangement
EP2178117A1 (en) Power semiconductor module with double side cooling
US7310224B2 (en) Electronic apparatus with thermal module
CN108987368B (zh) 具有由钢制成的绝缘金属基板的印刷电路板
CN110168709B (zh) 具有用于连接半导体芯片的第一和第二连接元件的半导体模块及制造方法
US20120199989A1 (en) Circuit arrangement and manufacturing method thereof
US11004695B2 (en) Power semiconductor module arrangement having a base plate and a contact element
JPH08274228A (ja) 半導体搭載基板、電力用半導体装置及び電子回路装置
JP6060053B2 (ja) パワー半導体装置
EP4421868A1 (en) Semiconductor module arrangement
CN113206049B (zh) 半导体装置
CN114556554A (zh) 基板、封装结构及电子设备
CN117293118A (zh) 功率模块及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant