JP5138611B2 - 接合用の隣接収納部を有する半導体相互接続、及び形成方法 - Google Patents

接合用の隣接収納部を有する半導体相互接続、及び形成方法 Download PDF

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Publication number
JP5138611B2
JP5138611B2 JP2008552305A JP2008552305A JP5138611B2 JP 5138611 B2 JP5138611 B2 JP 5138611B2 JP 2008552305 A JP2008552305 A JP 2008552305A JP 2008552305 A JP2008552305 A JP 2008552305A JP 5138611 B2 JP5138611 B2 JP 5138611B2
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Japan
Prior art keywords
layer
dielectric layer
opening
dielectric
forming
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JP2008552305A
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Japanese (ja)
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JP2009524932A5 (https=
JP2009524932A (ja
Inventor
チャッタージー、リットウィック
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NXP USA Inc
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NXP USA Inc
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Publication of JP2009524932A5 publication Critical patent/JP2009524932A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2008552305A 2006-01-25 2006-12-07 接合用の隣接収納部を有する半導体相互接続、及び形成方法 Active JP5138611B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/339,132 US7579258B2 (en) 2006-01-25 2006-01-25 Semiconductor interconnect having adjacent reservoir for bonding and method for formation
US11/339,132 2006-01-25
PCT/US2006/061737 WO2007100404A2 (en) 2006-01-25 2006-12-07 Semiconductor interconnect having adjacent reservoir for bonding and method for formation

Publications (3)

Publication Number Publication Date
JP2009524932A JP2009524932A (ja) 2009-07-02
JP2009524932A5 JP2009524932A5 (https=) 2010-02-04
JP5138611B2 true JP5138611B2 (ja) 2013-02-06

Family

ID=38284743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008552305A Active JP5138611B2 (ja) 2006-01-25 2006-12-07 接合用の隣接収納部を有する半導体相互接続、及び形成方法

Country Status (5)

Country Link
US (2) US7579258B2 (https=)
JP (1) JP5138611B2 (https=)
CN (1) CN101496166B (https=)
TW (1) TWI415216B (https=)
WO (1) WO2007100404A2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134235B2 (en) * 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device
US8053900B2 (en) * 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
US8796822B2 (en) * 2011-10-07 2014-08-05 Freescale Semiconductor, Inc. Stacked semiconductor devices
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
KR102724620B1 (ko) * 2019-11-19 2024-11-01 에스케이하이닉스 주식회사 반도체 메모리 장치
GB2589329B (en) * 2019-11-26 2022-02-09 Plessey Semiconductors Ltd Substrate bonding

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JPH04258125A (ja) * 1991-02-13 1992-09-14 Nec Corp 半導体装置
US5739579A (en) 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
US6232219B1 (en) 1998-05-20 2001-05-15 Micron Technology, Inc. Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures
JP2002026056A (ja) * 2000-07-12 2002-01-25 Sony Corp 半田バンプの形成方法及び半導体装置の製造方法
DE10118422B4 (de) 2001-04-12 2007-07-12 Infineon Technologies Ag Verfahren zur Herstellung einer strukturierten metallhaltigen Schicht auf einem Halbleiterwafer
JP3735547B2 (ja) * 2001-08-29 2006-01-18 株式会社東芝 半導体装置及びその製造方法
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
EP1732116B1 (en) 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods

Also Published As

Publication number Publication date
TW200746358A (en) 2007-12-16
US7514340B2 (en) 2009-04-07
JP2009524932A (ja) 2009-07-02
CN101496166A (zh) 2009-07-29
CN101496166B (zh) 2010-11-03
WO2007100404A3 (en) 2008-10-09
US20070170585A1 (en) 2007-07-26
TWI415216B (zh) 2013-11-11
US20070170584A1 (en) 2007-07-26
US7579258B2 (en) 2009-08-25
WO2007100404A2 (en) 2007-09-07

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