JP5105835B2 - 突起型トランジスタ製造方法 - Google Patents
突起型トランジスタ製造方法 Download PDFInfo
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- JP5105835B2 JP5105835B2 JP2006314879A JP2006314879A JP5105835B2 JP 5105835 B2 JP5105835 B2 JP 5105835B2 JP 2006314879 A JP2006314879 A JP 2006314879A JP 2006314879 A JP2006314879 A JP 2006314879A JP 5105835 B2 JP5105835 B2 JP 5105835B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図1は本発明に係る突起型トランジスタ製造方法を説明するための平面図である。
12 活性領域
14 フィールド領域
20 ハードマスク膜
30 トレンチ
40 側壁酸化膜
50 ライナー窒化膜
60 SOG膜
70 エピシリコン膜
80 HDP酸化膜
90 フィールド酸化膜
100 ゲート
100a ゲート絶縁膜
100b ゲート導電膜
100c ゲートハードマスク膜
Claims (13)
- 活性領域及びフィールド領域を有するシリコン基板上に前記フィールド領域を露出させるハードマスク膜を形成するステップと、
前記露出した基板フィールド領域をエッチングしてトレンチを形成するステップと、
前記トレンチ内にSOG(Spin On Glass)膜を埋込むステップと、
前記ハードマスク膜を除去して基板活性領域を露出させるステップと、
前記露出した基板活性領域上にエピシリコン膜を形成するステップと、
前記トレンチ内の下層部のみ埋込むようにSOG膜をエッチングするステップと、
前記トレンチを埋込むようにエッチングされたSOG膜上にHDP(High Density Plasma)酸化膜を形成して、前記SOG膜とHDP酸化膜からなるフィールド酸化膜を形成するステップと、
前記エピシリコン膜の両側面が露出するようにフィールド酸化膜のHDP酸化膜をエッチングするステップと、
前記両側面が露出したエピシリコン膜及びフィールド酸化膜上にゲートを形成するステップと、
を含むことを特徴とする突起型トランジスタ製造方法。 - 前記ハードマスク膜は、パッド酸化膜とパッド窒化膜の積層膜であることを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記ハードマスク膜は、300〜1000Åの厚さで形成することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記エピシリコン膜を形成するステップは、ファーネスで600〜1000℃の温度で遂行することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記エピシリコン膜は、SiH4、Si2H6及びSiCl2H2から構成されたグループから選択されるいずれか1つをソースガスとして使用して形成することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記エピシリコン膜は、GeまたはPの不純物をドーピングさせて形成することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記エピシリコン膜は、SiとSiGeとを順次に積層して形成する、または、SiとSiGeとを所望する厚さが得られるまで少なくとも2回以上交互に積層して形成することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記エピシリコン膜は、ハードマスク膜よりも90〜110Å薄く形成することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記SOG膜のエッチングは、トレンチ上段から150〜200Å下の深さから残留するように遂行することを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記SOG膜のエッチング後、そして、前記HDP酸化膜の形成前、前記SOG膜の緻密化のために熱処理を遂行するステップを更に含むことを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記熱処理は、ファーネスでN2雰囲気及び600〜1000℃の温度で遂行することを特徴とする請求項10に記載の突起型トランジスタ製造方法。
- 前記HDP膜の形成後、前記HDP膜を緻密化させるために熱処理を遂行するステップを更に含むことを特徴とする請求項1に記載の突起型トランジスタ製造方法。
- 前記熱処理は、ファーネスでN2またはO2雰囲気で700〜1000℃の温度で遂行することを特徴とする請求項12に記載の突起型トランジスタ製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2005-0128607 | 2005-12-23 | ||
KR1020050128607A KR100713924B1 (ko) | 2005-12-23 | 2005-12-23 | 돌기형 트랜지스터 및 그의 형성방법 |
Publications (2)
Publication Number | Publication Date |
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JP2007173789A JP2007173789A (ja) | 2007-07-05 |
JP5105835B2 true JP5105835B2 (ja) | 2012-12-26 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006314879A Expired - Fee Related JP5105835B2 (ja) | 2005-12-23 | 2006-11-21 | 突起型トランジスタ製造方法 |
Country Status (3)
Country | Link |
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US (1) | US7655534B2 (ja) |
JP (1) | JP5105835B2 (ja) |
KR (1) | KR100713924B1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100843016B1 (ko) * | 2007-03-14 | 2008-07-01 | 주식회사 하이닉스반도체 | 반도체 소자의 액티브 구조 |
US7687355B2 (en) | 2007-03-30 | 2010-03-30 | Hynix Semiconductor Inc. | Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer |
KR100929636B1 (ko) | 2007-03-30 | 2009-12-03 | 주식회사 하이닉스반도체 | 핀 트랜지스터 제조방법 |
KR100870297B1 (ko) * | 2007-04-27 | 2008-11-25 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100984859B1 (ko) * | 2008-04-29 | 2010-10-04 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 및 그 형성방법 |
KR20110100464A (ko) * | 2010-03-04 | 2011-09-14 | 삼성전자주식회사 | 반도체 메모리 장치 |
US9761666B2 (en) * | 2011-06-16 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel field effect transistor |
US9012286B2 (en) | 2012-04-12 | 2015-04-21 | Globalfoundries Inc. | Methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices |
US8580642B1 (en) | 2012-05-21 | 2013-11-12 | Globalfoundries Inc. | Methods of forming FinFET devices with alternative channel materials |
US8673718B2 (en) | 2012-07-09 | 2014-03-18 | Globalfoundries Inc. | Methods of forming FinFET devices with alternative channel materials |
US8815659B2 (en) | 2012-12-17 | 2014-08-26 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device by performing an epitaxial growth process |
US9379106B2 (en) | 2013-08-22 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels |
KR102025309B1 (ko) * | 2013-08-22 | 2019-09-25 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9269628B1 (en) | 2014-12-04 | 2016-02-23 | Globalfoundries Inc. | Methods of removing portions of at least one fin structure so as to form isolation regions when forming FinFET semiconductor devices |
US10141305B2 (en) * | 2016-09-15 | 2018-11-27 | Qualcomm Incorporated | Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts |
CN113314467B (zh) * | 2020-02-26 | 2024-08-27 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
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KR100332108B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
KR100500923B1 (ko) * | 2000-05-23 | 2005-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US6429061B1 (en) * | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
JP4832629B2 (ja) * | 2000-10-04 | 2011-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100354439B1 (ko) * | 2000-12-08 | 2002-09-28 | 삼성전자 주식회사 | 트렌치 소자 분리막 형성 방법 |
KR100512167B1 (ko) * | 2001-03-12 | 2005-09-02 | 삼성전자주식회사 | 트렌치 소자 분리형 반도체 장치 및 트렌치형 소자 분리막형성방법 |
US20020171107A1 (en) * | 2001-05-21 | 2002-11-21 | Baohong Cheng | Method for forming a semiconductor device having elevated source and drain regions |
KR100728173B1 (ko) * | 2003-03-07 | 2007-06-13 | 앰버웨이브 시스템즈 코포레이션 | 쉘로우 트렌치 분리법 |
JP2004311487A (ja) * | 2003-04-02 | 2004-11-04 | Hitachi Ltd | 半導体装置の製造方法 |
KR100487567B1 (ko) * | 2003-07-24 | 2005-05-03 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 형성 방법 |
KR100506460B1 (ko) * | 2003-10-31 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체소자의 트랜지스터 및 그 형성방법 |
US7118987B2 (en) * | 2004-01-29 | 2006-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of achieving improved STI gap fill with reduced stress |
US7045432B2 (en) * | 2004-02-04 | 2006-05-16 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) |
US7154159B2 (en) * | 2004-02-24 | 2006-12-26 | Nanya Technology Corporation | Trench isolation structure and method of forming the same |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
TWI299519B (en) * | 2005-09-28 | 2008-08-01 | Promos Technologies Inc | Method of fabricating shallow trench isolation structure |
-
2005
- 2005-12-23 KR KR1020050128607A patent/KR100713924B1/ko not_active IP Right Cessation
-
2006
- 2006-11-08 US US11/594,579 patent/US7655534B2/en not_active Expired - Fee Related
- 2006-11-21 JP JP2006314879A patent/JP5105835B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US20070148840A1 (en) | 2007-06-28 |
US7655534B2 (en) | 2010-02-02 |
JP2007173789A (ja) | 2007-07-05 |
KR100713924B1 (ko) | 2007-05-07 |
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