JP5084724B2 - 放電速度制御を備える不揮発性メモリを有する集積回路及び放電速度制御方法 - Google Patents

放電速度制御を備える不揮発性メモリを有する集積回路及び放電速度制御方法 Download PDF

Info

Publication number
JP5084724B2
JP5084724B2 JP2008509987A JP2008509987A JP5084724B2 JP 5084724 B2 JP5084724 B2 JP 5084724B2 JP 2008509987 A JP2008509987 A JP 2008509987A JP 2008509987 A JP2008509987 A JP 2008509987A JP 5084724 B2 JP5084724 B2 JP 5084724B2
Authority
JP
Japan
Prior art keywords
current
array
memory cell
discharge rate
discharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2008509987A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008541325A (ja
JP2008541325A5 (enExample
Inventor
プラサンナ ゴゴイ、ビシュヌ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2008541325A publication Critical patent/JP2008541325A/ja
Publication of JP2008541325A5 publication Critical patent/JP2008541325A5/ja
Application granted granted Critical
Publication of JP5084724B2 publication Critical patent/JP5084724B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
JP2008509987A 2005-05-02 2005-10-14 放電速度制御を備える不揮発性メモリを有する集積回路及び放電速度制御方法 Expired - Lifetime JP5084724B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/120,270 US7272053B2 (en) 2004-11-18 2005-05-02 Integrated circuit having a non-volatile memory with discharge rate control and method therefor
US11/120,270 2005-05-02
PCT/US2005/037070 WO2006118601A1 (en) 2005-05-02 2005-10-14 Integrated circuit having a non-volatile memory with discharge rate control and method therefor

Publications (3)

Publication Number Publication Date
JP2008541325A JP2008541325A (ja) 2008-11-20
JP2008541325A5 JP2008541325A5 (enExample) 2009-01-08
JP5084724B2 true JP5084724B2 (ja) 2012-11-28

Family

ID=37308269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008509987A Expired - Lifetime JP5084724B2 (ja) 2005-05-02 2005-10-14 放電速度制御を備える不揮発性メモリを有する集積回路及び放電速度制御方法

Country Status (3)

Country Link
US (1) US7272053B2 (enExample)
JP (1) JP5084724B2 (enExample)
WO (1) WO2006118601A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7532496B1 (en) * 2007-02-21 2009-05-12 National Semiconductor Corporation System and method for providing a low voltage low power EPROM based on gate oxide breakdown
US7859340B2 (en) * 2007-03-30 2010-12-28 Qualcomm Incorporated Metal-oxide-semiconductor circuit designs and methods for operating same
US7808827B2 (en) * 2007-11-06 2010-10-05 Spansion Llc Controlled bit line discharge for channel erases in nonvolatile memory
TWI358067B (en) * 2007-12-19 2012-02-11 Powerchip Technology Corp Integrated circuits and discharge circuits
JP5235400B2 (ja) * 2007-12-20 2013-07-10 三星電子株式会社 放電回路
JP2010079977A (ja) * 2008-09-25 2010-04-08 Toppan Printing Co Ltd 定電流型電源回路を有する不揮発性半導体メモリ装置
US7944281B2 (en) * 2008-12-12 2011-05-17 Mosys, Inc. Constant reference cell current generator for non-volatile memories
JP2010262696A (ja) * 2009-04-30 2010-11-18 Toshiba Corp Nand型フラッシュメモリ
IT1400967B1 (it) 2010-06-15 2013-07-05 St Microelectronics Srl Dispositivo di memoria non volatile con circuito di riconnessione
IT1400968B1 (it) 2010-06-15 2013-07-05 St Microelectronics Srl Dispositivo di memoria non-volatile con scarica controllata
US8553463B1 (en) 2011-03-21 2013-10-08 Lattice Semiconductor Corporation Voltage discharge circuit having divided discharge current
US8830776B1 (en) 2013-03-15 2014-09-09 Freescale Semiconductor, Inc. Negative charge pump regulation
KR102173431B1 (ko) 2014-05-02 2020-11-03 삼성전자주식회사 동작 전류가 감소된 메모리 장치
US9590504B2 (en) 2014-09-30 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Flipped gate current reference and method of using
US11563373B2 (en) 2020-11-19 2023-01-24 Stmicroelectronics International N.V. Circuit and method for controlled discharge of a high (positive or negative) voltage charge pump

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750078A (en) 1987-06-15 1988-06-07 Motorola, Inc. Semiconductor protection circuit having both positive and negative high voltage protection
JP3204666B2 (ja) * 1990-11-21 2001-09-04 株式会社東芝 不揮発性半導体記憶装置
JP3409404B2 (ja) * 1993-12-27 2003-05-26 富士通株式会社 フラッシュ・メモリ
EP0668593B1 (en) * 1994-02-21 2001-09-26 STMicroelectronics S.r.l. Regulation circuit and method for the erasing phase of non-volatile memory cells
US5701090A (en) 1994-11-15 1997-12-23 Mitsubishi Denki Kabushiki Kaisha Data output circuit with reduced output noise
EP0757356B1 (en) 1995-07-31 2001-06-06 STMicroelectronics S.r.l. Flash EEPROM with controlled discharge time of the word lines and source potentials after erase
US5732020A (en) 1996-06-12 1998-03-24 Altera Corporation Circuitry and methods for erasing EEPROM transistors
JP3191861B2 (ja) 1997-01-30 2001-07-23 日本電気株式会社 不揮発性半導体メモリ装置及びその消去方法
JPH1145588A (ja) * 1997-07-25 1999-02-16 Nec Corp 不揮発性半導体記憶装置
JP3892612B2 (ja) 1999-04-09 2007-03-14 株式会社東芝 半導体装置
JP3633853B2 (ja) * 2000-06-09 2005-03-30 Necエレクトロニクス株式会社 フラッシュメモリの消去動作制御方法およびフラッシュメモリの消去動作制御装置
US6445518B1 (en) * 2000-11-28 2002-09-03 Semiconductor Technologies & Instruments, Inc. Three dimensional lead inspection system
KR100385230B1 (ko) * 2000-12-28 2003-05-27 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 방법
US6438032B1 (en) 2001-03-27 2002-08-20 Micron Telecommunications, Inc. Non-volatile memory with peak current noise reduction
US6714458B2 (en) 2002-02-11 2004-03-30 Micron Technology, Inc. High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices
US6667910B2 (en) 2002-05-10 2003-12-23 Micron Technology, Inc. Method and apparatus for discharging an array well in a flash memory device

Also Published As

Publication number Publication date
US20060104122A1 (en) 2006-05-18
JP2008541325A (ja) 2008-11-20
US7272053B2 (en) 2007-09-18
WO2006118601A1 (en) 2006-11-09

Similar Documents

Publication Publication Date Title
US6671206B2 (en) High voltage low power sensing device for flash memory
CN105185409B (zh) 具有两个独立控制电压泵的存储器架构
US6717861B2 (en) Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof
JP4746326B2 (ja) 不揮発性半導体記憶装置
US7821829B2 (en) Nonvolatile memory device including circuit formed of thin film transistors
US7573752B2 (en) NAND flash memory cell programming
US7616487B2 (en) Decoders and decoding methods for nonvolatile semiconductor memory devices
JP5084724B2 (ja) 放電速度制御を備える不揮発性メモリを有する集積回路及び放電速度制御方法
US6680865B2 (en) Nonvolatile memory for which program operation is optimized by controlling source potential
JP2001195890A (ja) 不揮発性半導体メモリ装置の書込み方式および書込み回路
JP3204666B2 (ja) 不揮発性半導体記憶装置
KR100893474B1 (ko) 반도체 기억 장치
JP3615009B2 (ja) 半導体記憶装置
KR100781980B1 (ko) 불휘발성 메모리 장치에서의 디코더 및 그에 의한 디코딩방법
US7151695B2 (en) Integrated circuit having a non-volatile memory with discharge rate control and method therefor
JP3600461B2 (ja) 半導体回路
KR100634456B1 (ko) 플래시 메모리 장치 및 그것의 독출 방법
KR100222575B1 (ko) 불휘발성 반도체 메모리 장치의 더미 셀 구동회로
JP3181478B2 (ja) 不揮発性半導体記憶装置
JPH04252497A (ja) 不揮発性半導体記憶装置
EP0903752A2 (en) Nonvolatile semiconductor memory
JP2002203394A (ja) 半導体メモリ
JPH08235879A (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080917

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080917

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110428

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120131

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120530

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120606

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120807

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120904

R150 Certificate of patent or registration of utility model

Ref document number: 5084724

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150914

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250