JP5074577B2 - セラミック多層回路アッセンブリを製造するための方法および相応の多層回路アッセンブリ - Google Patents
セラミック多層回路アッセンブリを製造するための方法および相応の多層回路アッセンブリ Download PDFInfo
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- JP5074577B2 JP5074577B2 JP2010501453A JP2010501453A JP5074577B2 JP 5074577 B2 JP5074577 B2 JP 5074577B2 JP 2010501453 A JP2010501453 A JP 2010501453A JP 2010501453 A JP2010501453 A JP 2010501453A JP 5074577 B2 JP5074577 B2 JP 5074577B2
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- 238000000034 method Methods 0.000 title claims description 42
- 239000000919 ceramic Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000843 powder Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 11
- 239000007921 spray Substances 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000005245 sintering Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229940098458 powder spray Drugs 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 238000010304 firing Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B33—ADDITIVE MANUFACTURING TECHNOLOGY
- B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- B33Y80/00—Products made by additive manufacturing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
- H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09881—Coating only between conductors, i.e. flush with the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0169—Using a temporary frame during processing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1333—Deposition techniques, e.g. coating
- H05K2203/1344—Spraying small metal particles or droplets of molten metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1333—Deposition techniques, e.g. coating
- H05K2203/1366—Spraying coating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
- Y10T29/4916—Simultaneous circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49163—Manufacturing circuit on or in base with sintering of base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
請求項1記載のセラミック多層回路アッセンブリもしくは請求項11記載の相応の多層回路アッセンブリを製造するための本発明による方法は、公知のLTCC法と比べて材料処理時の手間のかかる中間段階なしで十分であるという利点を有している。なぜならば、粉末(金属、半金属、金属酸化物、誘電体)が、適切なプロセスによって直接的に処理可能となるからである。
本発明の実施例を図面に示し、以下に詳しく説明する。
Claims (11)
- セラミック多層回路アッセンブリを製造するための方法において、該方法が以下のステップ:すなわち
多層回路アッセンブリの複数の回路層(L1〜L4)を基板(10b)に粉末スプレー法で順次析出し、この場合、個々の回路層(L1〜L4)が、少なくとも1つの伝導性の粉末材料(MP)から成る導電性の領域(V1〜V7;LB1〜LB5)と、少なくとも1つのセラミック粉末材料(DP)から成る電気的に絶縁性の領域(D1〜D4)とを有しており;
析出された複数の回路層(L1〜L4)を加圧成形し;
加圧成形された複数の回路層(L1〜L4)を熱的に焼結する:
を備えていることを特徴とする、セラミック多層回路アッセンブリを製造するための方法。 - 加圧成形のために積層用フレーム(10;10a〜10c)を使用し、析出のための基板(10b)が、積層用フレーム(10;10a〜10c)の底部である、請求項1記載の方法。
- 粉末スプレー法において、伝導性の粉末材料(MP)から成る導電性の領域(V1〜V7、LB1〜LB5)と、セラミック粉末材料(DP)から成る電気的に絶縁性の領域(D1〜D4)とをスプレー被着するために、可動な2つのスプレーヘッド(S1、S2)を使用する、請求項1または2記載の方法。
- 伝導性の材料(MP)が、流動性を保証するためのコーティングを備えた金属粉末であり、コーティングを、焼結時に200℃〜500℃の間の温度範囲内で完全焼成する、請求項1から3までのいずれか1項記載の方法。
- セラミック材料(DP)が、流動性を保証するためのコーティングを備えたセラミック粉末であり、コーティングを、熱的な焼結時に200℃〜500℃の間の温度範囲内で完全焼成する、請求項1から4までのいずれか1項記載の方法。
- 回路層(L1〜L4)が、複数の基礎回路層(L1a〜L1d)の析出によって形成される少なくとも1つの回路層(L1〜L4)を有している、請求項1から5までのいずれか1項記載の方法。
- 伝導性の粉末材料(MP)とセラミック粉末材料(DP)とが、0.1〜5μmの範囲内の粒子サイズを有している、請求項1から6までのいずれか1項記載の方法。
- 加圧成形を100〜数百N/mm2の圧力(P)で実施する、請求項1から7までのいずれか1項記載の方法。
- 熱的な焼結を800℃〜1000℃、有利には900℃の温度で実施する、請求項1から8までのいずれか1項記載の方法。
- 個々の回路層(L1〜L4)を10〜200μmの間の厚さに形成する、請求項1から9までのいずれか1項記載の方法。
- 複数の回路層(L1〜L4)を備えたセラミック多層回路アッセンブリにおいて、
少なくとも1つの回路層(L1〜L4)が、粉末スプレー法による複数の基礎回路層(L1a〜L1d)の析出によって形成されており、
個々の回路層(L1〜L4)が、
加圧成形されかつ焼結された、粉末スプレー法によりスプレー被着された伝導性の粉末材料(MP)から成る導電性の領域(V1〜V7;LB1〜LB5)と、
加圧成形されかつ焼結された、粉末スプレー法によりスプレー被着されたセラミック粉末材料(DP)から成る電気的に絶縁性の領域と、
を有していることを特徴とする、セラミック多層回路アッセンブリ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200710015399 DE102007015399A1 (de) | 2007-03-30 | 2007-03-30 | Verfahren zur Herstellung einer keramischen Mehrlagen-Schaltungsanordnung und entsprechende Mehrlagen-Schaltungsanordnung |
DE102007015399.8 | 2007-03-30 | ||
PCT/EP2008/051485 WO2008119582A1 (de) | 2007-03-30 | 2008-02-07 | Verfahren zur herstellung einer keramischen mehrlagen-schaltungsanordnung und entsprechende mehrlagen-schaltungsanordnung |
Publications (2)
Publication Number | Publication Date |
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JP2010524212A JP2010524212A (ja) | 2010-07-15 |
JP5074577B2 true JP5074577B2 (ja) | 2012-11-14 |
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JP2010501453A Active JP5074577B2 (ja) | 2007-03-30 | 2008-02-07 | セラミック多層回路アッセンブリを製造するための方法および相応の多層回路アッセンブリ |
Country Status (5)
Country | Link |
---|---|
US (1) | US9003653B2 (ja) |
EP (1) | EP2132771B1 (ja) |
JP (1) | JP5074577B2 (ja) |
DE (1) | DE102007015399A1 (ja) |
WO (1) | WO2008119582A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015215759B4 (de) | 2015-08-19 | 2018-10-25 | Robert Bosch Gmbh | Verfahren zur Herstellung einer Kontaktierungsvorrichtung auf einem keramischen Substrat sowie eine nach dem Verfahren erzeugte Kontaktierungsvorrichtung |
DE102017123307A1 (de) * | 2017-10-06 | 2019-04-11 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Komponententräger mit zumindest einem Teil ausgebildet als dreidimensional gedruckte Struktur |
EP3468312B1 (en) | 2017-10-06 | 2023-11-29 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method of manufacturing a component carrier having a three dimensionally printed wiring structure |
EP3468311B1 (en) | 2017-10-06 | 2023-08-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Metal body formed on a component carrier by additive manufacturing |
DE102019208093A1 (de) * | 2019-06-04 | 2020-12-10 | Robert Bosch Gmbh | Verfahren zum Herstellen einer dreidimensionalen Schaltung sowie dreidimensionale Schaltung |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US4920640A (en) | 1988-01-27 | 1990-05-01 | W. R. Grace & Co.-Conn. | Hot pressing dense ceramic sheets for electronic substrates and for multilayer electronic substrates |
JP3084286B2 (ja) * | 1990-11-22 | 2000-09-04 | 真空冶金株式会社 | セラミツクス誘電体厚膜コンデンサ、その製造方法および製造装置 |
JPH09232174A (ja) * | 1996-02-23 | 1997-09-05 | Murata Mfg Co Ltd | 積層型セラミック電子部品およびその製造方法 |
DE19615787A1 (de) | 1996-04-20 | 1997-10-23 | Bosch Gmbh Robert | Verfahren zur Herstellung eines keramischen Multilayer-Substrats |
DE19638195A1 (de) | 1996-09-19 | 1998-04-02 | Bosch Gmbh Robert | Dielektrische Paste |
DE19646369B4 (de) | 1996-11-09 | 2008-07-31 | Robert Bosch Gmbh | Keramische Mehrlagenschaltung und Verfahren zu ihrer Herstellung |
US6085413A (en) | 1998-02-02 | 2000-07-11 | Ford Motor Company | Multilayer electrical interconnection device and method of making same |
JP2001079819A (ja) | 1999-09-20 | 2001-03-27 | Fujitsu General Ltd | キャビティ付き多層基板 |
SE520565C2 (sv) * | 2000-06-16 | 2003-07-29 | Ivf Industriforskning Och Utve | Sätt och apparat vid framställning av föremål genom FFF |
JP3805266B2 (ja) * | 2002-02-27 | 2006-08-02 | Uht株式会社 | セラミック積層体の製造装置 |
JP4478401B2 (ja) | 2003-05-15 | 2010-06-09 | 富士通株式会社 | 回路基板、電子装置、及び回路基板の製造方法 |
JP4190358B2 (ja) | 2003-06-16 | 2008-12-03 | 富士通株式会社 | 回路基板、受動部品、電子装置、及び回路基板の製造方法 |
-
2007
- 2007-03-30 DE DE200710015399 patent/DE102007015399A1/de not_active Withdrawn
-
2008
- 2008-02-07 JP JP2010501453A patent/JP5074577B2/ja active Active
- 2008-02-07 US US12/594,183 patent/US9003653B2/en active Active
- 2008-02-07 WO PCT/EP2008/051485 patent/WO2008119582A1/de active Application Filing
- 2008-02-07 EP EP08716766.4A patent/EP2132771B1/de active Active
Also Published As
Publication number | Publication date |
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EP2132771B1 (de) | 2017-04-12 |
US9003653B2 (en) | 2015-04-14 |
JP2010524212A (ja) | 2010-07-15 |
US20100187000A1 (en) | 2010-07-29 |
WO2008119582A1 (de) | 2008-10-09 |
DE102007015399A1 (de) | 2008-10-02 |
EP2132771A1 (de) | 2009-12-16 |
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