JP5054115B2 - 非対称型マルチプロセッサ装置上の診断動作の実行 - Google Patents
非対称型マルチプロセッサ装置上の診断動作の実行 Download PDFInfo
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- JP5054115B2 JP5054115B2 JP2009533925A JP2009533925A JP5054115B2 JP 5054115 B2 JP5054115 B2 JP 5054115B2 JP 2009533925 A JP2009533925 A JP 2009533925A JP 2009533925 A JP2009533925 A JP 2009533925A JP 5054115 B2 JP5054115 B2 JP 5054115B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
Description
16:共有メモリ
18:プライベートメモリ
26:マスター診断ユニット
Claims (29)
- 非対称型マルチプロセッサ装置であって、
データ処理動作を実行するために各プログラム命令に応答する複数の実行メカニズムと、プログラム命令実行のスレッドは、前記複数の実行メカニズム間で時分割され、前記複数の実行メカニズムの少なくとも1つは、一つ以上の他の前記複数の実行メカニズムとは異なる処理アーキテクチャを有し、
診断動作を実行するために各実行メカニズムに各々関連付けられる複数のスレーブ診断ユニットと、
前記複数のスレーブ診断ユニットに接続され、実行メカニズム間における所定のスレッドの実行の移行に応答し、前記所定のスレッドの処理に関してアクティブとなった前記実行メカニズムがどれであるかを判別することで、マスター診断ユニットは、どの実行メカニズムが前記所定のスレッドを実行しているかの変化を追跡する、マスター診断ユニットと
を具備し、
実行の前記移行は、1つの実行メカニズムからもう1つの実行メカニズムへの同期リモートプロシージャコールによることを特徴とする装置。 - 前記複数の実行メカニズムが同一のメモリマップを共有しないよう非対称型メモリ階層を具備することを特徴とする請求項1に記載の非対称型マルチプロセッサ装置。
- 前記マスター診断ユニットは、実行メカニズムから診断出力を提供し、前記診断出力における対応する変化を行うために前記所定のスレッドの実行メカニズムにおける変化に応答することを特徴とする請求項1〜2の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記マスター診断ユニットは、現在前記所定のスレッドを実行する、実行メカニズムに関連付けられるスレーブ診断ユニットに前記所定のスレッドに関する診断コマンドを向けることを特徴とする請求項1〜3の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記マスター診断ユニットは、一部が実行されることができるそれら実行メカニズムの各々の上で前記所定のスレッドの前記一部に関するブレイクポイントを設定することを特徴とする請求項1〜4の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記ブレイクポイントは、各実行メカニズムによって前記一部に使用されるメモリアドレスに一致するメモリアドレスで設定されることを特徴とする請求項5に記載の非対称型マルチプロセッサ装置。
- 前記ブレイクポイントがトリガされる時、前記マスター診断ユニットは、どのスレッドが前記ブレイクポイントをトリガしたかを判断することを特徴とする請求項5に記載の非対称型マルチプロセッサ装置。
- 複数のメモリを具備し、前記マスター診断ユニットは、データ項目を格納することができる前記複数のメモリの各々に関するデータ項目のウォッチポイントを設定することを特徴とする請求項1〜7の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記ウォッチポイントは、各メモリ内の前記データ項目に使用されるメモリアドレスに一致するメモリアドレスで設定されることを特徴とする請求項8に記載の非対称型マルチプロセッサ装置。
- 前記ウォッチポイントがトリガされる時、前記マスター診断ユニットは、どのスレッドが前記ウォッチポイントをトリガしたかを判断することを特徴とする請求項8に記載の非対称型マルチプロセッサ装置。
- 前記スレーブ診断ユニットは、スレーブ追跡ユニットであり、前記マスター診断ユニットは、マスター追跡ユニットであり、前記マスター追跡ユニットは、前記所定のスレッドのための追跡出力を形成する時、異なる実行メカニズム間における前記所定のスレッドの実行の移行を追跡することを特徴とする請求項1〜10の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記スレーブ診断ユニットは、スレーブプロファイリングユニットであり、前記マスター診断ユニットは、マスタープロファイリングユニットであり、前記マスタープロファイリングユニットは、前記所定のスレッドのためのプロファイリング出力を形成する時、異なる実行メカニズム間における前記所定のスレッドの実行の移行を追跡することを特徴とする請求項1〜11の何れか1項に記載の非対称型マルチプロセッサ装置。
- 前記複数の実行メカニズムは、
汎用プロセッサと、
ダイレクトメモリアクセスユニットと、
コプロセッサと、
VLIWプロセッサと、
デジタル信号プロセッサと、
ハードウェアアクセラレータユニットと
の一つ以上を具備することを特徴とする請求項1〜12の何れか1項に記載の非対称型マルチプロセッサ装置。 - 前記非対称型メモリ階層は、
前記実行メカニズムの全てにアクセス可能なグローバル共有メモリと、
前記実行メカニズムの少なくとも2つにアクセス可能な共有メモリと、
前記実行メカニズムの1つにアクセス可能なプライベートメモリと
の2つ以上を具備することを特徴とする請求項2に記載の非対称型マルチプロセッサ装置。 - 非対称型マルチプロセッサ装置上で診断動作を実行する方法であって、
複数の実行メカニズムでデータ処理動作を実行する各プログラム命令に応答する段階であって、プログラム命令実行のスレッドは、前記複数の実行メカニズム間で時分割され、前記複数の実行メカニズムの少なくとも1つは、一つ以上の他の前記複数の実行メカニズムとは異なる処理アーキテクチャを有する、段階と、
関連付けられる各スレーブ診断ユニットで前記複数の実行メカニズム上で診断動作を実行する段階と、
前記複数のスレーブ診断ユニットに接続され、実行メカニズム間で所定のスレッドの実行の移行に応答し、前記所定のスレッドの処理に関してアクティブとなった前記実行メカニズムがどれであるかを判別することで、マスター診断ユニットは、どの実行メカニズムが前記所定のスレッドを実行しているかの変化を追跡するマスター診断ユニットを使用する段階と
を具備し、
実行の前記移行は、1つの実行メカニズムからもう1つの実行メカニズムへの同期リモートプロシージャコールによることを特徴とする方法。 - 前記非対称型マルチプロセシング装置は、前記複数の実行メカニズムが同一のメモリマップを共有しないよう非対称型メモリ階層を具備することを特徴とする請求項15に記載の方法。
- 前記マスター診断ユニットは、実行メカニズムから診断出力を提供し、前記診断出力における対応する変化を行うために前記所定のスレッドのための実行メカニズムにおける変化に応答することを特徴とする請求項15〜16の何れか1項に記載の方法。
- 前記マスター診断ユニットは、現在前記所定のスレッドを実行する、実行メカニズムに関連付けられるスレーブ診断ユニットに前記所定のスレッドに関する診断コマンドを向けることを特徴とする請求項15〜17の何れか1項に記載の方法。
- 前記マスター診断ユニットは、一部が実行されることができるそれら実行メカニズムの各々の上で前記所定のスレッドの前記一部に関するブレイクポイントを設定することを特徴とする請求項15〜18の何れか1項に記載の方法。
- 前記ブレイクポイントは、各実行メカニズムによって前記一部に使用されるメモリアドレスに一致するメモリアドレスで設定されることを特徴とする請求項19に記載の方法。
- 前記ブレイクポイントがトリガされる時、前記マスター診断ユニットは、どのスレッドが前記ブレイクポイントをトリガしたかを判断することを特徴とする請求項19に記載の方法。
- 前記非対称型マルチプロセシング装置は、複数のメモリを具備し、前記マスター診断ユニットは、データ項目を格納することができる前記複数のメモリの各々に関するデータ項目のためのウォッチポイントを設定することを特徴とする請求項15〜21の何れか1項に記載の方法。
- 前記ウォッチポイントは、各メモリ内の前記データ項目に使用されるメモリアドレスに一致するメモリアドレスで設定されることを特徴とする請求項22に記載の方法。
- 前記ウォッチポイントがトリガされる時、前記マスター診断ユニットは、どのスレッドが前記ウォッチポイントをトリガしたかを判断することを特徴とする請求項22に記載の方法。
- 前記スレーブ診断ユニットは、スレーブ追跡ユニットであり、前記マスター診断ユニットは、マスター追跡ユニットであり、前記マスター追跡ユニットは、前記所定のスレッドのための追跡出力を形成する時、異なる実行メカニズム間における前記所定のスレッドの実行の移行を追跡することを特徴とする請求項15〜24の何れか1項に記載の方法。
- 前記スレーブ診断ユニットは、スレーブプロファイリングユニットであり、前記マスター診断ユニットは、マスタープロファイリングユニットであり、前記マスタープロファイリングユニットは、前記所定のスレッドのためのプロファイリング出力を形成する時、異なる実行メカニズム間における前記所定のスレッドの実行の移行を追跡することを特徴とする請求項15〜25の何れか1項に記載の方法。
- 前記複数の実行メカニズムは、
汎用プロセッサと、
ダイレクトメモリアクセスユニットと、
コプロセッサと、
VLIWプロセッサと、
デジタル信号プロセッサと、
ハードウェアアクセラレータユニットと
の一つ以上を具備することを特徴とする請求項15〜26の何れか1項に記載の方法。 - 前記非対称型メモリ階層は、
前記実行メカニズムの全てにアクセス可能なグローバル共有メモリと、
前記実行メカニズムの少なくとも2つにアクセス可能な共有メモリと、
前記実行メカニズムの1つにアクセス可能なプライベートメモリと
の2つ以上を具備することを特徴とする請求項16に記載の方法。 - 請求項15〜28の何れか1項に記載の方法に従って、マスター診断ユニット及び複数のスレーブ診断ユニットを制御するためにコンピュータを制御するためのコンピュータプログラム。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US85375606P | 2006-10-24 | 2006-10-24 | |
US60/853,756 | 2006-10-24 | ||
GB0709182A GB2443277B (en) | 2006-10-24 | 2007-05-11 | Performing diagnostics operations upon an asymmetric multiprocessor apparatus |
GB0709182.0 | 2007-05-11 | ||
PCT/GB2007/003223 WO2008050076A1 (en) | 2006-10-24 | 2007-08-24 | Performing diagnostic operations upon an asymmetric multiprocessor apparatus |
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JP2010507855A JP2010507855A (ja) | 2010-03-11 |
JP5054115B2 true JP5054115B2 (ja) | 2012-10-24 |
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US (5) | US20080098208A1 (ja) |
EP (1) | EP2076837B1 (ja) |
JP (1) | JP5054115B2 (ja) |
KR (1) | KR101325229B1 (ja) |
CN (1) | CN101529391B (ja) |
DE (1) | DE602007009857D1 (ja) |
GB (1) | GB2443277B (ja) |
IL (1) | IL197314A (ja) |
MY (1) | MY144449A (ja) |
TW (1) | TWI407374B (ja) |
WO (1) | WO2008050076A1 (ja) |
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EP2076837B1 (en) | 2010-10-13 |
MY144449A (en) | 2011-09-30 |
CN101529391B (zh) | 2011-06-15 |
KR20090082254A (ko) | 2009-07-29 |
US20080114937A1 (en) | 2008-05-15 |
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