US20080098208A1 - Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems - Google Patents

Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems Download PDF

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US20080098208A1
US20080098208A1 US11/898,360 US89836007A US2008098208A1 US 20080098208 A1 US20080098208 A1 US 20080098208A1 US 89836007 A US89836007 A US 89836007A US 2008098208 A1 US2008098208 A1 US 2008098208A1
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program
data
sections
computer program
code
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Alastair David Reid
Simon Andrew Ford
Yuan Lin
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ARM Ltd
University of Michigan
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University of Michigan
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring

Definitions

  • the field of the invention relates to data processing and in particular to improving the performance of program execution.
  • Such complex systems may comprise a number of different processing or execution units and they may be heterogeneous or asymmetric, with specialised processing units being used to increase energy efficiency and lower gate count.
  • specialised processing units being used to increase energy efficiency and lower gate count.
  • the programming of embedded systems with their hardware restriction, demand for efficiency and the ever decreasing time to market is becoming a real problem.
  • Decoupling programs to produce a number of threads communicating via FIFO pipelines has been used many times before: Smith (James E. Smith, “Decoupled access/execute computer architectures”, ACM Transactions Computing Systems, 2(4), 289-308, 1984) applies the technique manually to Cray assembly code; Palacharla and Smith (S. Palacharla and J. E. Smith, “Decoupling integer execution in superscalar processors”, in MICRO 28: Proc. of International Symposium on Microarchitecture, 285-290, 1995) describe the use of program slicing to automate the separation. These uses of decoupling were targeted at hiding memory latency by having one thread perform all load-store operations while the other thread performs all arithmetic operations.
  • SoC system on chip
  • a first aspect of the present invention provides a method of transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately executed and that each comprise different data processing code, said method comprising the steps of: (i) analysing said portion of said program to determine if said sequential instructions can be divided at said point indicated by said program separation indicator and in response to determining that it can: (iia) providing data communication between said separate sections indicated by said program separation indicator, such that said separate sections can be decoupled from each other, such that at least one of said sections is capable of being separately executed by an execution mechanism that is separate from an execution mechanism executing another of said separate sections, said at least one of said sections being capable of generating data and communicating said data to at least one other of said separate sections; and in response to determining it can not: (iib) not performing step (iia).
  • the present method provides a tool for analysing a portion of the program to determine if the instructions can be divided at a point indicated by a separation indicator.
  • separation indicators are provided within at least a section of the program and indicate where it is desirable to divide the program.
  • the division of the program is determined to some degree by these separation indicators and can thus, be controlled by a programmer.
  • the method of the present invention forms an analysis of a program that actually includes the separation indicators and decides if the program can indeed be separated at these points. If it is decided that it can be it provides data communication between the two sections to allow them to be decoupled from each other.
  • the program can be split into sections suitable for separate execution allowing a program to be efficiently processed by a variety of different, often complex devices. If it decides it cannot be divided at this point then it does not perform the data communication step.
  • a warning indicating an error in the computer program is output. Providing the programmer with a warning may be the most appropriate thing to do if the separation indicators are not in the correct position.
  • said step (iib) comprises amending said computer program such that said sequential instructions can be divided at said point and then performing step (iia).
  • the method can amend the computer program so that the sequential instructions can be divided at this point and then the data communication can be divided between the different sections. It may be that it is a relatively simple matter to amend the computer program so that it can be divided at the point indicated and if this is the case then the method can perform this step rather than outputting a warning.
  • said step of amending said computer program comprises inserting data transfer instructions at said point indicated by said program separation indicator.
  • the step required to amend the computer program may be one of inserting data transfer instructions at the point indicated by the program separation indicator.
  • said step (iib) comprises merging said two sections together and removing said program separation indicator.
  • said program separation indicator comprises at least one data transfer instruction, said data communication between said separate sections being provided in dependence upon said at least one data transfer instruction.
  • program separation indicators can take a number of forms it is quite efficient if they take the form of data transfer instructions.
  • providing program separation indictors in the form of data transfer instructions may facilitate their separation by providing the data communication required.
  • said step (iia) of providing data communication comprises inserting at least one “put data into a data store” instruction and at least one “get data from said data store” instruction into said instruction stream, and dividing said computer program between said put and get instructions to form said at least one separate section.
  • the step of providing data communication can be done by inserting a put data into data store and a get data from said data store instructions into the instruction stream. This allows data to be removed from one section of the program and then input into the other section via a data store. Thus, the two sections are in effect decoupled from each other but data can travel between the two via this data store.
  • said data store comprises a FIFO buffer.
  • the data store may comprise a FIFO buffer as this is clearly the simplest arrangement where the first data to exit from a section of the program is the first data to enter the next section, it may be that the data is not required in a particular order or indeed that all the data generated by one section is not required by the other.
  • a variety of different data stores and different arrangements can be used in some embodiments. For example, a stack which has a last in first out semantics could be used, one advantage of this is that a stack is simple to implement.
  • said step (iia) comprises providing cyclic data communication between said separate sections.
  • the decoupling of threads can be further extended to use where communication between threads is cyclic. Cyclic thread dependencies can lead to deadlock that is, two threads may not run in parallel because of data dependencies between them and thus, in devices of the prior art decoupling is limited to acyclic thread dependencies. Embodiments of the present invention address this problem and provide cyclic dependencies. This may be done, for example, by using put and get instructions and not requiring the number of puts to be equal to the number of gets. This is in contrast to the prior art where put and get operations are always inserted in corresponding places in each thread. Allowing put operations to be inserted in places that do not correspond to get operations in other threads, means that code such as is illustrated in FIG. 4 can be produced.
  • said separate sections comprise the same control code.
  • control code is the same in the two sections as the computer program is divided such that different data processing steps are performed under the same control in each divided section. Duplicating control code in this way enables the program to be divided.
  • control code will be different. This is because it may be advantageous occasionally to slightly modify the control code in one of the sections such that, for example, a conditional code that is no longer required is not present.
  • said portion of said computer program comprises a plurality of program separation indicators each indicating a point where said sequential instructions may be divided to form separate sections, each of said separate sections being capable of being separately executed and comprising different data processing code, said method providing data communication between said separate sections indicated by said plurality of program separation indicators.
  • An instruction loop having several data processing steps for example can be divided by embodiments of the present invention into two sections by allowing the different sections to have different data processing codes. This can increase the performance of a system significantly. Generally this is done by duplicating the control code and in effect performing two loops, one performing one or more of the data processing steps of the original loop and the other performing the rest of the steps.
  • said transformed computer program is suitable for execution upon respective execution mechanisms of a heterogeneous system having a complex asymmetric memory hierarchy and a plurality of execution mechanisms.
  • Embodiments of the present invention although applicable to symmetric systems are particularly valuable in asymmetric heterogeneous systems wherein it is often difficult to separately execute sections of a program, particularly where at least a portion of the program is written sequentially.
  • a section of code is executed by a single execution mechanisms
  • said control code of at least one of said sections is operable to be processed by a processor of said heterogeneous system and said data processing code of said section is operable to be processed by an execution mechanism under control of said control code processed by said processor.
  • An execution mechanism may be a simple mechanism designed for a particular function, such as a memory transfer unit (colloquially known as a “DMA engine”) and in such cases it may be that the control code is performed on a separate processor, while the data processing operations are performed on the simpler mechanism.
  • DMA engine memory transfer unit
  • the plurality of execution mechanisms can take a number of forms, including a general purpose processor; a direct memory access unit; a coprocessor; a VLIW processor; a digital signal processor; and a hardware accelerator unit.
  • said method step comprises an initial step performed before step (i) of: defining said portion of said computer program by marking said computer program with indications delimiting said portion of said sequential instructions within which said at least two sections are to be located.
  • said computer program comprises said portion having a number of instructions to be executed sequentially and at least one further portion having instructions to be performed in parallel with each other.
  • a computer program may have different portions, some for execution sequentially and some already written for parallel processing. In such a case, it is the portion that has the instructions for sequential execution that is analysed to see if it can be divided into sections for separate execution. It should be noted that a portion to be analysed may be within a section that is to be executed in parallel. Furthermore, a portion to be analysed may also contain two or more sections that are to be executed in parallel.
  • said portion of said computer program comprises an instruction loop comprising at least two data processing instructions, and said at least two sections each comprise said instruction loop each section comprising at least one of said at least two data processing instructions, said at least two sections comprising different data processing instructions.
  • An instruction loop having several data processing steps can be divided into two sections, and thereby increase the performance of a system significantly.
  • the present method is able to duplicate the control code and perform in effect two loops, one performing one or more of the data processing steps of the initial loop and the other performing the rest of the steps.
  • said portion of said computer program comprises a whole computer program.
  • a second aspect of the present invention provides a computer-readable storage medium comprising a computer program for controlling a computer to perform the method of the first aspect of the present invention.
  • a third aspect of the invention provides a computer executing a computer program to perform the method of a first aspect of the present invention.
  • a further aspect of the present invention provides a method of transforming a portion of a computer program comprising a list of sequential instructions and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately executed and that each comprise different data processing code, said list of instructions comprising control code and data processing code, said method comprising the step of:
  • the program comprises program separation indictors indicating points where they may be divided then the program can be transformed by providing data communication between the separate sections at the points indicated so that they can be decoupled from each other. This allows the program to be split into sections suitable for separate execution and allows the program to be efficiently processed by a variety of different often complex devices. This enables future analysis of the program via a programmer to be relatively straight forward and yet still enable it to execute efficiently on a parallel system.
  • said method comprises a further initial step (0) performed before step (i) of in response to said program separation indicator, analysing said portion of said computer program and determining which of said sequential instructions should be in which of said separate sections prior to providing said data communication.
  • FIGS. 1 a to 1 c show flow diagrams of methods according to embodiments of the present invention
  • FIG. 2 a to 2 d schematically shows the splitting into separately executable sections of a computer program according to an embodiment of the present invention
  • FIG. 3 a to 3 b schematically shows a method of splitting and then merging sections of a computer program
  • FIG. 4 schematically shows data communication between two sections of a program
  • FIG. 5 a shows a simple computer program annotated according to an embodiment of the present invention
  • FIG. 5 b shows the maximal set of threads for the program of FIG. 4 a.
  • FIG. 6 schematically illustrates an asymmetric multiprocessing apparatus with an asymmetric memory hierarchy
  • FIG. 7 illustrates an architectural description
  • FIG. 8 illustrates a communication requirement
  • FIG. 9 illustrates communication support
  • FIG. 1 a shows a flow diagram illustrating a method according to an embodiment of the present invention.
  • a first step is performed in which a portion of a computer program comprising a list of sequential instructions and a program separation indicator indicating a point where the sequential instructions may be divided to form separate sections that are capable of being separately executed is analysed. The analysis determines if the sequential instructions can be split at the point indicated by the separation indicator into separate sections that can be processed on different execution mechanisms. If it determines it can the sequential instructions are divided into the separate sections at the point indicated by the program separation indicator. If it determines they cannot be separated at this point then a warning is output to the programmer to indicate an error in the program.
  • FIG. 1 b illustrates an alternative embodiment in which rather than outputting a warning if the program cannot be decoupled and separated at the indicated point, the program is amended by inserting data communication instructions into the list of sequential instructions, these data communication instructions enabling the different sections to be decoupled and thus, separated. The separation can then be performed.
  • FIG. 1 c provides an alternative embodiment in which in response to determining that the program cannot be separated at the indicated point the two sections are merged together and the program separation indicator removed.
  • the three embodiments provide different solutions to an analysis that determines that it is not possible to separate a program into sections at the point indicated. Different ones of these embodiments may be used in the same analysis of a program for different separation indicators depending on circumstances. Thus, it may be that the preferred course of action is to amend the program to make it separable at he indicated point, if this cannot be done then it may be chosen to merge the two portions, or if this would result in an unacceptably large portion then a warning may be output.
  • FIG. 2 a shows a portion of a computer program comprising a loop in which data items are processed, function f operating on the data items, and function g operating on the data items output by function f and then function h operating on these items. These functions being performed n times in a row for values of i from 1 to n.
  • control flow can be seen as following the solid arrows while data flow follows the dotted arrows.
  • decouple or program separation indications are inserted into the data flow where it is seen as being desirable to split the portion into sections that are decoupled from each other and can thus, be executed on separate execution mechanisms.
  • a decouple indication is provided between the data processing operations f and g. This can be seen as being equivalent to inserting a buffer in the data flow, as the two sections are decoupled by providing a data store between then so that the function f can produce its results which can then be accessed at a different time by function g.
  • the program is then analysed to see if it can indeed be decoupled at the point indicated by the separation indicators. If it can then the method proceeds to FIG. 2 c . If it cannot then a warning may be output to the programmer, the program may be amended to enable it to be decoupled at this point, or the decouple indication may be removed from the program and the two sections merged.
  • FIG. 2 c shows how the separate sections of the program are decoupled by the insertion of “put” and “get” instructions into the data stream. These result in the data being generated by the f function being put into a data store, from which it is retrieved by the get instruction to be processed by function g.
  • the two sections of the program are in effect decoupled from each other and can be executed on separate executions mechanisms.
  • one of the functions may be a function suitable for processing by an accelerator in which case it can be directed to an accelerator, while the other portion is processed by say, the CPU of the apparatus.
  • the splitting of the program results in the control code of the program being duplicated in both section, while the data processing code is different in each section.
  • the put and get operations used in FIG. 2 c can be used in programs both for scalar and non-scalar values but they are inefficient for large (non-scalar) values as they require a memory copy.
  • a different embodiment of the invention applies this idea to the channel interface, by replacing the simple ‘put’ operation with two functions: put_begin obtains the address of the next free buffer in the channel and put end makes this buffer available to readers of the channel:
  • sequences of code such as:
  • Cyclic thread dependencies can lead to deadlock—that is, two threads may not run in parallel because of data dependencies between them and thus, in devices of the prior art decoupling is generally limited to acyclic thread dependencies.
  • FIGS. 3 a and 3 b schematically illustrate the program code shown in FIG. 2 .
  • a data store is provided to decouple functions f and g, but one is not provided between g and h.
  • analysis of the program to decouple it is performed automatically and several potential sections are provided, in this case these are loops having functions f, g and h in them. The automatic analysis then checks that each loop can be executed separately and in this case identifies a missing data path between functions g and h. Thus, these two functions are remerged to provide two sections with a data path between.
  • a further example of a code fragment that can be split by an embodiment of the present invention is provided below. Since communication lies at the boundaries between threads, the compiler's job is to “color in” the code that lies between the boundaries. This is done through a dependency analysis to decide the set of operations that are on the “producer” side of a channel and the set of operations on the “consumer” side of a channel. The compiler then partitions the operations according to that analysis; and generates a separate thread for each equivalence class.
  • the PIPELINE annotation on line 1 identifies the region of code to be split into threads.
  • the FIFO annotation on line 5 identifies that the communication between threads is to be performed between f and g.
  • the compiler performs a data and control flow analysis to determine that the call to g has a data dependency on the FIFO operation and also has control dependencies on the if statement (line 4) and the for loop (line 2). This results in the following thread:
  • the data and control flow analysis also determines that the FIFO operation (line 5) has a data dependency on the call to f (line 3) and also has control dependencies on the if statement (line 4) and the for loop (line 2). This results in the following thread:
  • Decoupling must make two essential decisions: “What variables and operations to replicate?” and “What operations to place in the same thread?”.
  • the task of decoupling is to split the region of code into as many threads as possible, without introducing timing-dependent behaviour, using channels to communicate between threads.
  • the generated threads do not strictly partition the statements in the original code: some variables and operations (principally those used for control) are duplicated between threads.
  • the choice of what to duplicate is an essential part of the transformation: if too much code or data is duplicated, the transformed program can run slower and use much more memory than the original program. While these decisions could be controlled using annotations on every variable and statement, some simple default rules can be used that give the programmer control without requiring excessive annotation.
  • variables to be duplicated are determined by the location of their declaration (variables declared inside the PIPELINE annotation may be duplicated) and their size (scalar variables may be duplicated). Operations other than function calls may be duplicated unless they have side-effects or modify a non-duplicable variable.
  • the dependency analysis stage forms a large number of “pre-threads” by computing a backward data and control slice (see Mark Weiser, “Program slicing”, in ICSE '81: Proc. of International Conference on Software Engineering, 439-449, 1981) from each unduplicated operation ignoring data dependencies on FIFO operations but including all duplicable and unduplicable operations in the slice. That is, we repeatedly apply rules (1) and (2) to form prethreads. In our running example, there are three prethreads: one each for f( ), FIFO(2,x), and g(x).
  • the prethread for f( ) is:
  • the merging stage combines “prethreads” by merging threads that contain the same non-duplicable operation or variable. For example, the prethread for f( ) is merged with the prethread for FIFO(2,x) because they both contain the operation f( ), resulting in the prethread:
  • the thread production stage converts prethreads to threads by inserting channel declarations and initialization, privatizing duplicable variables, replacing FIFO operations with fifo_put operations and inserting a fifo_get operation in every thread that contains an operation dependent on a FIFO operation. If multiple threads contain operations dependent on the same FIFO operation, a separate channel has to be introduced for each fifo_get operation introduced and the FIFO operation is replaced with a fifo_put operation on each channel.
  • the problem can be fixed by moving the FIFO operation to before the if-statement or by arranging to pass the if-condition through a channel by changing the if-statement to if (FIFO(2,x>0)) ⁇ . . . ⁇ .
  • Decoupling can be used with all channel types except non-blocking FIFOs.
  • FIG. 4 shows a further example of how an original piece of code can be split into two threads to be executed in parallel using of put and get instructions.
  • Parallelizing at a coarse granularity allows the duplication of more control code between threads which reduces and simplifies inter-thread communication allowing the generation of distributed schedules. That is, we can distribute the control code across multiple processors both by putting each control thread on a different processor and by putting different parts of a single control thread onto different processors.
  • the transfer of data may be done by, writing the data to a particular buffer such as a FIFO. Alternatively it may simply be done by providing the other section of the program with information as to where the data has been stored.
  • the way of transferring the data depends on the system the program is executing on.
  • the architecture does not have shared memory, it is necessary to insert DMA copies from a buffer in one memory to a buffer in a different memory. This can lead to a lot of changes in the code: declaring both buffers, performing the copy, etc.
  • an analysis is performed to determine which buffers need to be replicated in multiple memory regions and to determine exactly which form of copy should be used.
  • DMA copies are also inserted automatically subject to some heuristics when the benefit from having the programmer make the decision themselves is too small.
  • Atomic channels provide atomic access to an element: an atomic_get operation acquires a copy of the element and makes the element unavailable to other threads (i.e., it “locks” the variable) and an atomic_put operation makes the variable available for use by other threads (i.e., it “unlocks” the variable).
  • an atomic_get operation acquires a copy of the element and makes the element unavailable to other threads (i.e., it “locks” the variable) and an atomic_put operation makes the variable available for use by other threads (i.e., it “unlocks” the variable).
  • atomic channels are equivalent to a fifo channel of maximum length 1.
  • Nonblocking put and get channels are a variant on fifo channels where the nbpfifo_put operation returns an error code if the channel is full instead of blocking as fifo channels do. These channels are for use in interrupt handlers since it is possible to block a thread but not an interrupt. We also provide channels that provide a non-blocking nbgfifo_get operation.
  • Timed channels provide time-indexed access to data.
  • a timestamp is specified:
  • the ts_get operation returns the entry with the closest timestamp to that specified. All ts_put operations must use strictly increasing times and all ts_get operations must use strictly increasing times. This restriction allows entries to be discarded when they can no longer be accessed.
  • Timed channels allow for more parallelism between threads since, after the first ts_put is performed, ts_get operations never block because there is always an entry with a closest timestamp.
  • the cost of this increased performance is less precise synchronization between threads than with FIFO channels: applications that use timed channels are unlikely to give deterministic results.
  • Timed channels are useful for implementing time-sensitive information where it is important to use current data.
  • mobile telephones implementing the “3rd generation” W-CDMA protocol use rake receivers to increase the bandwidth of links subject to multipath fading (i.e., where the signal contains delayed echoes of the transmitted signal typically due to reflections off buildings).
  • Rake receivers estimate the strength and delay of these reflections and use these estimates to combine delayed copies of the received signal to maximize the amount of received signal energy.
  • the best estimate to use is the one closest in time to the data arrived which may be different from the next estimate generated.
  • Timed channels are an example of a channel type which makes sense in some domains or applications but not in others. Rather than fix the set of channel types in the language, our compiler allows new channel types to be added using annotations to identify channel types and put and get operations.
  • the only properties on which SoC-C relies are that operations are atomic, directional and obey a copy semantics. That is, put operations atomically copy data into a channel and get operations atomically copy data out of a channel.
  • FIG. 5 a shows a simple computer program annotated according to an embodiment of the present invention. An analysis of this program is performed initially and parts of the program are identified by programmer annotation in this embodiment although it could be identified by some other analysis including static analysis, profile driven feedback, etc. The parts identified are as follows:
  • the “replicatable objects” that is variables and operations which it is acceptable to replicate.
  • a simple rule of thumb is that scalar variables (i.e., not arrays) which are not used outside the scope, scalar operations which only depend on and only modify replicatable variables, and control flow operations should be replicated but more sophisticated policies are possible.
  • the algorithm splits the operations in the scope into a number of threads whose execution will produce the same result as the original program under any scheduling policy that respects the FIFO access ordering of the channels used to communicate between threads.
  • the particular decoupling algorithm used generates a maximal set of threads such that the following properties hold:
  • FIG. 5 b shows the maximal set of threads for the program of FIG. 5 a .
  • One way to generate the set of threads shown in FIG. 5 b is as follows:
  • Each replicatable variable must be initialized at the start of each thread with the value of the original variable before entering the scope and one of the copies of each replicatable variable should be copied back into the master copy on leaving the scope. (Executing all these protothreads is highly unlikely to give the same answer as the original program, because it lacks the necessary synchronization between threads. This is fixed by the next steps.)
  • Another way is to pick an operation, identify all the operations which must be in the same thread as that operation by repeatedly adding operations which would be merged (in step 2 above). Then pick the next operation not yet assigned to a thread and add all operations which must be in the same thread as that operation. Repeat until there are no more non-replicatable operations. It should be noted that this is just one possible way of tackling this problem: basically, we are forming equivalence classes based on a partial order and there are many other known ways to do this.
  • the above method splits a program into a number of sections which can be executed in parallel. There are many possible mechanisms that can be used to accomplish this task.
  • FIG. 6 shows a flow diagram of a method according to an embodiment of the present invention.
  • An initial step of the method comprises analysing the computer program that contains sequential code and program separation indicators. For each program separation indicator the program is analysed to determine how it can be divided into separate sections around this separation indicator. First of all it is checked that it is reasonable to divide it there. If it can be divided at this point then data communication between the two sections is provided and this may be done in a number of ways including the insertion of put and get instructions as was discussed earlier and then the program is analysed to determine if there are further program separation indicators. If there is then the program at this point is analysed to determine if it can be divided. If it cannot in its present state then it is checked to determine if it requires further data transfer instructions to divide it.
  • Program separation indicators can take a number of forms. They may simply be some sort of indicator such as a split indicating that the program needs to be divided there or they can in fact be data transfer functions which do by themselves provide a data communication between the two sections. Thus, they may be fifo instructions indicating that data should be sent fifo to transfer the data between the two sections as was discussed earlier or they may be put and get instructions. It may be that several variables need to be transferred between the two sections and that there are not sufficient data transfer instructions within the program. In such a case then the further data transfer instructions for these variables which have not been addressed can be inserted into the program and then the data communication between the two sections is provided and can then be separated before separate execution on separate execution mechanisms.
  • the compilation tools can take a program that is either sequential or contains few threads and map it onto the available hardware, introducing parallelism in the process.
  • the task of programming a SoC is to map different parts of an application onto different parts of the hardware.
  • blocks of code must be mapped onto processors, data engines, accelerators, etc. and data must be mapped onto various memories.
  • the mapping process is both tedious and error-prone because the mappings must be consistent with each other and with the capabilities of the hardware. We reduce these problems using program analysis which:
  • the number of legal mappings is usually large but once the programmer has made a few choices, the number of legal options usually drops significantly so it is feasible to ask the programmer to make a few key choices and then have the tool fill in the less obvious choices automatically.
  • Programmable accelerators may have limited program memory so it is desirable to upload new code while old code is running. For correctness, we must guarantee that the new code is uploaded (and I-caches made consistent) before we start running it.
  • Our compiler uses program analysis to check this and/or to schedule uploading of code at appropriate places.
  • mappings of an application For applications with highly variable load, it is desirable to have multiple mappings of an application and to switch dynamically between different mappings.
  • annotations which provide the semantics we want.
  • the primary annotations are on data and on code. If a tag is repeated, it indicates alternative mappings.
  • the tags associated with data include:
  • the tags associated with code include:
  • processor P1 is to execute fft followed by P1.
  • the semantics is similar to that of a synchronous remote procedure call: when control reaches this code, free variables are marshalled and sent to processor P1, processor P1 starts executing the code and the program continues when the code finishes executing.
  • the tags associated with functions are:
  • An error such as mapping a piece of code to a fixed-function accelerator that does not support that function should probably just be reported as an error that the programmer must fix.
  • Errors such as omitting synchronization can sometimes be fixed by automatically inserting synchronization. Errors such as requiring more variables to a memory bank than will fit can be solved, to some extent, using overlay techniques. Errors such as mapping an overly large variable to a memory can be resolved using software managed paging though this may need hardware support or require that the kernel be compiled with software paging turned on (note: software paging is fairly unusual so we have to implement it before we can turn it on!). Errors such as omitting memory barriers, cache flush/invalidate operations or DMA transfers can always be fixed automatically though it can require heuristics to insert them efficiently and, in some cases, it is more appropriate to request that the programmer fix the problem themselves.
  • Our compiler uses information about the SoC architecture, extracted from the architecture description, to determine how to implement the communication requirements specified within the program. This enables it to generate the glue code necessary for communication to occur efficiently and correctly. This can include generation of memory barriers, cache maintenance operations, DMA transfers and synchronisation on different processing elements.
  • This automation reduces programming complexity, increases reliability and flexibility, and provides a useful mechanism for extended debugging options.
  • RPCs Remote Procedure Calls
  • RPC abstraction can be expressed as functions mapped to particular execution mechanisms:
  • This provides a simple mechanism to express invocation of functions, and the associated resourcing, communication and synchronisation requirements.
  • Code can be translated to target the selected processing elements, providing the associated synchronisation and communication. For example, this could include checking the resource is free, configuring it, starting it and copying the results on completion.
  • the compiler can select appropriate glue mechanisms based on the source and target of the function call. For example, an accelerator is likely to be invoked primarily by glue on a processor using a mechanism specific to the accelerator.
  • the glue code may be generated automatically based on a high level description of the accelerator or the programmer may write one or more pieces of glue by hand.
  • processor on which the operation runs can be determined statically or can be determined dynamically. For example, if there are two identical DMA engines, one might indicate that the operation can be mapped onto either engine depending on which is available first.
  • the compiler optimisations based on the desired RPC interface can range from a dynamically linked interface to inter-procedural specialisation of the particular RPC interface.
  • RPC calls may be synchronous or asynchronous.
  • Asynchronous calls naturally introduce parallelism, while synchronous calls are useful as a simpler function call model, and may be used in conjunction with fork-join parallelism. In fact, parallelism is not necessary for efficiency; a synchronous call alone can get the majority of the gain when targeting accelerators. Manually and automatically selecting between asynchronous and synchronous options can benefit debugging, tracing and optimisation.
  • RPC calls may be re-entrant or non-reentrant, and these decisions can be made implicitly, explicitly or through program analysis to provide benefit such as optimisation where appropriate.
  • This mechanism enables a particular function to have a number of different execution targets within a program, but each of those targets can be associated back to the original function; debugging and trace can exploit this information.
  • This enables a user to set a breakpoint on a particular function, and the debug and trace mechanisms be arranged such that it can be caught wherever it executes, or on a restricted subset (e.g. a particular processing element).
  • RPC interface implementation can be abstracted away in some debugging views.
  • the datatypes are often bulk datastructures such as arrays of data, multimedia data, signal processing data, network packets, etc. and the operations may be executed with some degree of parallelism on a coprocessor, DSP processor, accelerator, etc. It is therefore possible to view programs as a series of often quite coarse-grained operations applied to quite large data structures instead of the conventional view of a program as a sequence of ‘scalar’ operations (like ‘32 bit add’) applied to ‘scalar’ values like 32-bit integers or the small sets of values found in SIMD within a register (SWAR) processing such as that found in NEON. It is also advantageous to do so because this coarse-grained view can be a good match for accelerators found in modern SoCs.
  • SWAR register
  • optimization techniques known to work on fine-grained operations and data can be adapted to operate on coarse-grained operations and data.
  • Our compiler understands the semantics associated with the data structures and their use within the system, and can manipulate them and the program to perform transformations and optimisations to enable and optimise execution of the program.
  • this might be generated automatically from a precise description of the operation (including the implementation of the operation) or it might be generated from an approximate description of the main effects of the operation or it might be provided as a direct annotation.
  • compilers do something similar for scalar variables: the value of a scalar variable ‘x’ might sometimes live on the stack, sometimes in register 3, sometimes in register 6, etc. and the compiler keeps track of which copies currently contain the live value.
  • the compiler can provide improved memory allocation through memory reuse because it can identify opportunities to place two different variables in the same memory location. Indeed, one can use many algorithms normally used for register allocation (where the registers contain scalar values) to perform allocation of data structures. One modification required is that one must handle the varying size of buffers whereas, typically, all scalar registers are the same size.
  • Compiler books list many other standard transformations that can be performed to scalar code. Some of the mapping and optimisation techniques that can be applied at the coarse-grain we discuss include value splitting, spilling, coalescing, dead variable removal, recomputation, loop hoisting and CSE.
  • Data structures will be passed as arguments, possibly as part of an ABI. Optimisations such as specialisation and not conforming to the ABI when it is not exposed can be applied.
  • Our compiler supports a variety of code generation strategies which allow the parallelized control code to run on a control processor in a real time operating system, in interrupt handlers or in a polling loop (using ‘wait for event’ if available to reduce power) and it also supports distributed scheduling where some control code runs on one or more control processors, some control code runs on programmable accelerators, some simple parts of the code are implemented using conventional task-chaining hardware mechanisms. It is also possible to design special ‘scheduler devices’ which could execute some parts of the control code. The advantage of not running all the control code on the control processor is that it can greatly decrease the load on the control processor.
  • the basic decoupling algorithm splits a block of code into a number of threads that pass data between each other via FIFO channels.
  • the algorithm requires us to identify (by programmer annotation or by some other analysis including static analysis, profile driven feedback, etc.) the following parts of the program:
  • the algorithm splits the operations in the scope into a number of threads whose execution will produce the same result as the original program under any scheduling policy that respects the FIFO access ordering of the channels used to communicate between threads.
  • the put and get operations used when decoupling can be used both for scalar and non-scalar values (i.e., both for individual values (scalars) and arrays of values (non-scalars) but they are inefficient for large scalar values because they require a memory copy. Therefore, for coarse-grained decoupling, it is desirable to use an optimized mechanism to pass data between threads.
  • get operation is split into a get_begin and get_end pair
  • the modified decoupling algorithm treats the puts and gets in much the same way that the standard algorithm treats data boundaries. Specifically, it constructs the maximal set of threads such that:
  • the modified decoupling algorithm will produce:
  • Writing code using explicit puts can also be performed as a preprocessing step. For example, we could transform:
  • a First-In First-Out (FIFO) channel preserves the order of values that pass through it: the first value inserted is the first value extracted, the second value inserted is the second value extracted, etc.
  • Other kinds of channel are possible including:
  • Exclusive access can be arranged in several ways. For example, one may ‘acquire’ (aka ‘lock) a ‘lock’ (aka ‘mutex’) before starting to access the resource and ‘release’ (aka ‘unlock’) the lock after using the resource. Exclusive access may also be arranged by disabling pre-emption (such as interrupts) while in a critical section (i.e., a section in which exclusive access is required). In some circumstances, one might also use a ‘lock free’ mechanism where multiple users may use a resource but at some point during use (in particular, at the end), they will detect the conflict, clean up and retry.
  • Some examples of wanting exclusive access include having exclusive access to a hardware accelerator, exclusive access to a block of memory or exclusive access to an input/output device. Note that in these cases, it is usually not necessary to preserve the order of accesses to the resource.
  • the basic decoupling algorithm avoids introducing race conditions by preserving all ordering dependencies on statements that access non-replicated resources. Where locks have been inserted into the program, the basic decoupling algorithm is modified as follows:
  • Decoupling can be applied to any sequential section of a parallel program. If the section communicates with the parallel program, we must determine any ordering dependencies that apply to operations within the section (a safe default is that the order of such operations should be preserved). What I'm saying here is that one of the nice properties of decoupling is that it interacts well with other forms of parallellization including manual parallelization.
  • the decoupling algorithm generates sections of code that are suitable for execution on separate processors but can be executed on a variety of different execution engines by modifying the “back end” of the compiler. That is, by applying a further transformation to the code after decoupling to better match the hardware or the context we wish it to run in.
  • the most straightforward execution model is to execute each separate section in the decoupled program on a separate processor or, on a processor that supports multiple hardware contexts (i.e., threads), to execute each separate section on a separate thread.
  • SoC System on Chip
  • DSPs digital signal processors
  • GPUs graphics processing units
  • DMA direct memory access
  • data engines programmable accelerators or fixed-function accelerators.
  • This data processing can be modelled as a synchronous remote procedure call.
  • a memory copy operation on a DMA engine can be modelled as a function call to perform a memory copy.
  • the thread will typically:
  • This mode of execution can be especially effective because one ‘control processor’ can keep a number of accelerator's busy with the control processor possibly doing little more than deciding which accelerator to start next and on what data. This mode of execution can be usefully combined with all of the following forms of execution.
  • a thread library such as operating system (OS) or real time operating system (RTOS) running on one or more processors to execute the threads introduced by decoupling.
  • OS operating system
  • RTOS real time operating system
  • transformations can be viewed as a way of transforming a thread into a state machine with each context switch point representing a state and the code that continues execution from each context switch point viewed as a transition function to determine the next state.
  • Execution of transformed threads can be viewed as having been transformed to an event-based model where all execution occurs in response to external events such as responses from input/output devices or from accelerators. It is not necessary to transform all threads: event-based execution can coexist with threaded execution.
  • Transforming threads as described above is also a good match for polling-based execution where the control processor tests for completion of tasks on a set of accelerators by reading a status register associated with each accelerator. This is essentially the same as interrupt-driven execution except that the state of the accelerators is updated by polling and the polling loop executes until all threads complete execution.
  • Distributed scheduling can be done in various ways. Some part of a program may be simple enough that it can be implemented using a simple state machine which schedules one invocation of an accelerator after completion of another accelerator. Or, a control processor can hand over execution of a section within a thread to another processor. In both cases, this can be viewed as a RPC like mechanism (“ ⁇ foo( ); bar( )@P0; ⁇ @P1”). In the first case, one way to implement it is to first transform the thread to event-based form and then opportunistically spot that a sequence of system states can be mapped onto a simple state machine and/or you may perform transformations to make it map better.
  • a system has to meet a set of deadlines and the threads within the system share resources such as processors, it is common to use a priority mechanism to select which thread to run next.
  • priorities might be static or they may depend on dynamic properties such as the time until the next deadline or how full/empty input and output queues are.
  • a long-standing problem of parallelizing compilers is that it is hard to relate the view of execution seen by debug mechanisms to the view of execution the programmer expects from the original sequential program.
  • Our tools can take an execution trace obtained from running a program on parallel hardware and reorder it to obtain a sequential trace that matches the original program. This is especially applicable to but not limited to the coarse-grained nature of our parallelization method.
  • partial reconstruction can be achieved by using points in the program that synchronize with each other to guide the matching process.
  • the resulting trace will not be sequential but will be easier to understand.
  • a useful application is to make it simpler to understand a trace of a program written using an event-based programming style (e.g., a GUI, interrupt handlers, device drivers, etc.)
  • Partial reconstruction could also be used to simplify parallel programs running on systems that use release consistency. Such programs must use explicit memory barriers at all synchronization points so it will be possible to simplify traces to reduce the degree of parallelism the programmer must consider.
  • HP has been looking at using trace to enable performance debugging of distributed protocols. Their focus is on data mining and performance not reconstructing a sequential trace.
  • each section is a node in a directed graph and there is an edge from a node M to a node N if the section corresponding to M writes to an address x and the section corresponding to N reads from address x and, in the original trace, no write to x happens between M's write to x and N's read from x.
  • This directed dataflow graph shows how different sections communicate with each other and can be used for a variety of purposes:
  • the first section talks about what you need for the general case of a program that has been parallelized and you would like to serialize trace from a run of the parallel program based on some understanding of what transformations were done during parallelization (i.e., you know how different bits of the program relate to the original program).
  • the second part talks about how you would specifically do this if the parallellization process included decoupling.
  • the sketch describes the simplest case in which it can work but it is possible to relax these restrictions significantly.
  • Condition 10 onwards relate mainly to what decoupling aims to achieve. But, some conditions are relevant such as conditions 5 and 6 because, in practice, it is useful to be able to relax these conditions slightly.
  • (5) says that kernels have exclusive access to buffers but it is obviously ok to have multiple readers of the same buffer and it would also be ok (in most real programs) for two kernels to (atomically) invoke ‘malloc’ and ‘free’ in the middle of the kernels even though the particular heap areas returned will depend on the precise interleaving of those calls and it may even be ok for debugging printfs from each kernel to be ordered.
  • Consequences of (1)-(4) We can identify each transaction with a kernel instance and we can see all transactions a kernel performs.
  • Consequences of (1)-(6) Given a trace consisting of the interleaved transactions of a set of kernel instances, we can reorder the transactions such that all transactions of a kernel are contiguous and the resulting trace satisfies all read after write data dependencies. That is, we can construct a sequentially consistent view of the transactions as though kernels executed atomically and sequentially.
  • Consequences of (7)-(9) Given a trace of the state transitions and synchronizations, we can reorder them into any of the set of legal transitions those state machines could have made where a transition is legal if it respects synchronization dependencies.
  • Consequences of (1)-(9) Given a trace of all kernel transactions and all state transitions and synchronizations, we can reorder them into any legal trace which respects the same synchronization dependencies and data dependencies.
  • Consequences of (1)-(10) We can reorder any trace to match a sequential version of the same program.
  • decoupling gives us property (10) (i.e., that any trace of the decoupled program can be reordered to give a trace of the original program and to show how to do that reordering), we need to establish a relationship between the parallel state machine and the master state machine (i.e., the original program). This relationship is an “embedding” (i.e., a mapping between states in the parallel and the master machines such that the transitions map to each other in the obvious way). It is probably easiest to prove this by considering what happens when we decouple a single state machine (i.e., a program) into two parallel state machines.
  • Extensions of decoupling allow the programmer to indicate that two operations can be executed in either order even though there is a data dependency between them (e.g., both increment a variable atomically). This mostly needs us to relax the definition of what trace reconstruction is meant to do. One major requirement is that the choice of order doesn't have any knock-on effects on control flow.
  • a sufficient (and almost necessary) condition is that a put and a get on the same channel must not be inside corresponding critical sections (in different threads):
  • a useful and safe special case is that all initialization code does N puts, a loop then contains only put_get pairs and then finalization code does at most N gets. It should be possible to prove that this special case is ok.
  • a task may have a deadline or it may require that it receive 2 seconds of CPU in every 10 second interval but tasks rarely require that they receive a particular pattern of scheduling.
  • the idea is to use the flexibility that the system provides to explore different sequences from those that a traditional scheduler would provide.
  • schedulers in common use are ‘work conserving schedulers’: if the resources needed to run a task are available and the task is due to execute, the task is started. In contrast, a non-work-conserving scheduler might choose to leave a resource idle for a short time even though it could be used. Non-work-conserving schedulers are normally used to improve efficiency where there is a possibility that a better choice of task will become available if the scheduler delays for a short time.
  • a non-work-conserving scheduler for testing concurrent systems because they provide more flexibility over the precise timing of different tasks than does a work-conserving scheduler.
  • the modification of the schedule is probably done within the constraints of the real-time requirements of the tasks. For example, when a task becomes runnable, one might establish how much ‘slack’ there is in the schedule and then choose to delay the task for at most that amount. In particular, when exploring different phases, if the second event doesn't happen within that period of slack, then the first event must be sent to the system and we will hope to explore that phase the next time the event triggers.
  • the scheduler can choose to execute the thread that would run that piece of code. (Again, it may be necessary to insert instrumentation into the code to help the scheduler figure out the status of each thread so that it can execute them in the correct order.)

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