JP5049221B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5049221B2 JP5049221B2 JP2008194670A JP2008194670A JP5049221B2 JP 5049221 B2 JP5049221 B2 JP 5049221B2 JP 2008194670 A JP2008194670 A JP 2008194670A JP 2008194670 A JP2008194670 A JP 2008194670A JP 5049221 B2 JP5049221 B2 JP 5049221B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead
- semiconductor device
- protrusions
- solder layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
1 半導体チップ
2 リード
3 ハンダ層
4 樹脂パッケージ
5 試験用端子
11 接着層
12 放熱部材
21,21a,21b,21c 突起
21A 正方形
21B 長方形
21C 円
22 凹部
22a 開口部
22b 底部
Claims (5)
- 矩形状でその外周縁が曲面によって形成されている半導体チップと、
表面に上記半導体チップを搭載する板状のリードと、
上記半導体チップと上記リードとを接着する緩衝部材と、
を備えた半導体装置であって、
上記リードの表面には、上記半導体チップとの間に上記緩衝部材が介在する複数の突起が形成されており、
上記複数の突起は、上記リードの厚み方向視において、上記半導体チップの四隅と重ならないように配置されており、
上記リードの表面の上記複数の突起の外側には、上記リードの厚み方向視において、上記半導体チップの外周と重なるように凹部が形成されており、
上記緩衝部材の外周縁が、上記凹部内に位置するとともに、
上記複数の突起は、上記リードの厚み方向視において上記半導体チップの外周縁に沿う長手方向を有する形状であることを特徴とする、半導体装置。 - 上記複数の突起は、上記半導体チップの外周縁に沿って配列されており、
上記半導体チップの外周縁に沿って互いに隣合う2つの上記突起どうしの間の距離は、これらの突起のいずれの長手方向寸法よりも小である、請求項1に記載の半導体装置。 - 上記複数の突起は、それぞれ同形である、請求項1または2に記載の半導体装置。
- 上記リードの上記半導体チップと対向する面が凸面に形成されている、請求項1ないし3のいずれかに記載の半導体装置。
- 上記リードの厚み方向視において上記複数の突起と重ならない部分での上記緩衝部材の厚みは、30μm〜70μmである、請求項1ないし4のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008194670A JP5049221B2 (ja) | 2008-07-29 | 2008-07-29 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008194670A JP5049221B2 (ja) | 2008-07-29 | 2008-07-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010034278A JP2010034278A (ja) | 2010-02-12 |
JP5049221B2 true JP5049221B2 (ja) | 2012-10-17 |
Family
ID=41738418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008194670A Expired - Fee Related JP5049221B2 (ja) | 2008-07-29 | 2008-07-29 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5049221B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6423147B2 (ja) * | 2013-12-03 | 2018-11-14 | 三菱電機株式会社 | 電力用半導体装置およびその製造方法 |
US20160322342A1 (en) * | 2014-01-15 | 2016-11-03 | Panasonic Intellectual Property Management Co. Lt | Semiconductor device |
JP7423197B2 (ja) | 2019-05-10 | 2024-01-29 | ローム株式会社 | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5492178A (en) * | 1977-12-29 | 1979-07-21 | Mitsubishi Electric Corp | Manufacture of metal substrate |
JPS56129739U (ja) * | 1980-02-29 | 1981-10-02 | ||
JPS583237A (ja) * | 1981-06-29 | 1983-01-10 | Fujitsu Ltd | 半導体装置 |
JPS6066846A (ja) * | 1983-09-24 | 1985-04-17 | Nippon Denso Co Ltd | 半導体整流装置 |
JPS60128624A (ja) * | 1983-12-15 | 1985-07-09 | Fuji Electric Co Ltd | 半導体装置 |
JPS60167347U (ja) * | 1984-04-13 | 1985-11-06 | 三菱電機株式会社 | 半導体装置 |
JPS61187258A (ja) * | 1985-02-14 | 1986-08-20 | Mitsubishi Electric Corp | 半導体集積回路チツプ |
JPH0637122A (ja) * | 1992-07-15 | 1994-02-10 | Hitachi Ltd | 半導体装置 |
JP3565114B2 (ja) * | 1999-10-29 | 2004-09-15 | 松下電器産業株式会社 | 樹脂封止型半導体装置 |
JP2006066663A (ja) * | 2004-08-27 | 2006-03-09 | Matsushita Electric Ind Co Ltd | 半導体パッケージ部品 |
JP2006351950A (ja) * | 2005-06-17 | 2006-12-28 | Rohm Co Ltd | 半導体装置及び半導体装置の製造方法 |
-
2008
- 2008-07-29 JP JP2008194670A patent/JP5049221B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2010034278A (ja) | 2010-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5729468B2 (ja) | 半導体装置 | |
JP5387685B2 (ja) | 半導体装置の製造方法 | |
JP5066529B2 (ja) | 半導体素子の実装構造体及び半導体素子の実装方法 | |
EP2784810B1 (en) | Chip packaging structure and chip packaging method | |
JP6195689B1 (ja) | パワーモジュール | |
JP2015128194A (ja) | 半導体装置 | |
JP2009076524A (ja) | 発光装置 | |
JP2010135723A (ja) | 半導体装置 | |
JP5049221B2 (ja) | 半導体装置 | |
JP2008124176A (ja) | 電力用半導体装置 | |
JP4367376B2 (ja) | 電力半導体装置 | |
JP2007048889A (ja) | 半導体装置 | |
JP2012164697A5 (ja) | ||
JP2009070907A (ja) | 半導体装置 | |
JP2013157357A (ja) | 発光装置 | |
JP6232697B2 (ja) | パワーモジュール | |
JP5381175B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
CN112335025B (zh) | 半导体装置 | |
JP2009099709A (ja) | 半導体装置 | |
US9704775B2 (en) | Method for manufacturing thermal interface sheet | |
JP2007012725A (ja) | 半導体装置 | |
JP5145168B2 (ja) | 半導体装置 | |
TWI625833B (zh) | 封裝結構 | |
JP2007227510A (ja) | 半導体装置 | |
JP4863836B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110708 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120425 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120501 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120628 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120717 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120720 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150727 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |