JP5006640B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5006640B2
JP5006640B2 JP2006346753A JP2006346753A JP5006640B2 JP 5006640 B2 JP5006640 B2 JP 5006640B2 JP 2006346753 A JP2006346753 A JP 2006346753A JP 2006346753 A JP2006346753 A JP 2006346753A JP 5006640 B2 JP5006640 B2 JP 5006640B2
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JP
Japan
Prior art keywords
chip
terminal
memory
terminals
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006346753A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008159815A5 (https=
JP2008159815A (ja
Inventor
仁志 佐藤
英俊 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2006346753A priority Critical patent/JP5006640B2/ja
Priority to KR1020070133021A priority patent/KR20080059047A/ko
Priority to TW096149165A priority patent/TW200828474A/zh
Priority to CNA2007103006847A priority patent/CN101207053A/zh
Priority to US11/962,212 priority patent/US20080153203A1/en
Publication of JP2008159815A publication Critical patent/JP2008159815A/ja
Publication of JP2008159815A5 publication Critical patent/JP2008159815A5/ja
Application granted granted Critical
Publication of JP5006640B2 publication Critical patent/JP5006640B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2006346753A 2006-12-22 2006-12-22 半導体装置の製造方法 Expired - Fee Related JP5006640B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2006346753A JP5006640B2 (ja) 2006-12-22 2006-12-22 半導体装置の製造方法
KR1020070133021A KR20080059047A (ko) 2006-12-22 2007-12-18 반도체 장치의 제조 방법
TW096149165A TW200828474A (en) 2006-12-22 2007-12-21 Semiconductor device manufacturing method
CNA2007103006847A CN101207053A (zh) 2006-12-22 2007-12-21 半导体器件制造方法
US11/962,212 US20080153203A1 (en) 2006-12-22 2007-12-21 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006346753A JP5006640B2 (ja) 2006-12-22 2006-12-22 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2008159815A JP2008159815A (ja) 2008-07-10
JP2008159815A5 JP2008159815A5 (https=) 2009-11-19
JP5006640B2 true JP5006640B2 (ja) 2012-08-22

Family

ID=39543426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006346753A Expired - Fee Related JP5006640B2 (ja) 2006-12-22 2006-12-22 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US20080153203A1 (https=)
JP (1) JP5006640B2 (https=)
KR (1) KR20080059047A (https=)
CN (1) CN101207053A (https=)
TW (1) TW200828474A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009194143A (ja) * 2008-02-14 2009-08-27 Elpida Memory Inc 半導体装置
JP5297992B2 (ja) 2009-12-15 2013-09-25 ルネサスエレクトロニクス株式会社 外部記憶装置
KR20120056018A (ko) * 2010-11-24 2012-06-01 삼성전자주식회사 범프들과 테스트 패드들이 십자 모양으로 배열되는 반도체 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2725657B2 (ja) * 1995-10-25 1998-03-11 日本電気株式会社 半導体装置およびその製造方法
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US8089142B2 (en) * 2002-02-13 2012-01-03 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
JP4580671B2 (ja) * 2004-03-29 2010-11-17 ルネサスエレクトロニクス株式会社 半導体装置
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
KR100761860B1 (ko) * 2006-09-20 2007-09-28 삼성전자주식회사 와이어 본딩 모니터링이 가능한 인터포저 칩을 갖는 적층반도체 패키지 및 이의 제조방법

Also Published As

Publication number Publication date
US20080153203A1 (en) 2008-06-26
CN101207053A (zh) 2008-06-25
JP2008159815A (ja) 2008-07-10
TW200828474A (en) 2008-07-01
KR20080059047A (ko) 2008-06-26

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