JP4952783B2 - 出力回路 - Google Patents
出力回路 Download PDFInfo
- Publication number
- JP4952783B2 JP4952783B2 JP2009503833A JP2009503833A JP4952783B2 JP 4952783 B2 JP4952783 B2 JP 4952783B2 JP 2009503833 A JP2009503833 A JP 2009503833A JP 2009503833 A JP2009503833 A JP 2009503833A JP 4952783 B2 JP4952783 B2 JP 4952783B2
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- JP
- Japan
- Prior art keywords
- signal
- circuit
- signal output
- output
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000007704 transition Effects 0.000 claims description 29
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000000872 buffer Substances 0.000 description 48
- 230000004048 modification Effects 0.000 description 48
- 238000012986 modification Methods 0.000 description 48
- 230000000630 rising effect Effects 0.000 description 36
- 238000010586 diagram Methods 0.000 description 33
- 230000008859 change Effects 0.000 description 12
- 230000004044 response Effects 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
Description
12 負荷回路
12−1乃至12−n 負荷回路
13 スイッチ回路
13−1乃至13−n スイッチ回路
14 スイッチ回路
15 スイッチ回路
16 制御回路
Claims (8)
- 第1の電位と第2の電位との間で遷移する信号を信号出力端に出力する信号出力ユニットと、
可変容量素子を含み負荷量が可変の負荷回路と、
該信号出力端と該負荷回路との間の電気的な導通/非導通を切替える第1のスイッチ回路と、
該可変容量素子と該第1のスイッチ回路との間の信号端を所定の電位に結合するスイッチ回路又は抵抗素子
を含むことを特徴とする出力回路。 - 該信号の該第1の電位と該第2の電位との間の遷移に略同期して該第1のスイッチ回路の導通/非導通が制御されるよう構成されることを特徴とする請求項1記載の出力回路。
- 該信号出力端に接続される第2のスイッチ回路と、
該第2のスイッチ回路を介して該信号出力端に結合される負荷量が可変の負荷回路
をさらに含むことを特徴とする請求項1記載の出力回路。 - 該第1のスイッチ回路と該第2のスイッチ回路とは交互に導通状態となるよう構成されることを特徴とする請求項3記載の出力回路。
- 該信号出力ユニットは、
該信号出力端と該第1の電位との間の電気的な導通/非導通を切替える第3のスイッチ回路と、
該信号出力端と該第2の電位との間の電気的な導通/非導通を切替える第4のスイッチ回路と、
を含み、該第3のスイッチ回路はPMOSトランジスタであり、該第4のスイッチ回路はNMOSトランジスタであることを特徴とする請求項1記載の出力回路。 - 該信号出力ユニットの出力をHIGHインピーダンス状態にするとともに該第1のスイッチ回路を非導通とすることにより該信号出力端をHIGHインピーダンス状態に設定可能なように構成されることを特徴とする請求項1記載の出力回路。
- 第1の電位と第2の電位との間で遷移する信号を信号出力端に出力する信号出力ユニットと、
負荷量が可変の負荷回路と、
該信号出力端と該負荷回路との間の電気的な導通/非導通を切替える第1のスイッチ回路と、
信号端と、
該信号端と該信号出力端との間を結合する第1の信号経路と、
該信号端と該負荷回路との間に設けられる第2のスイッチ回路
を含み、該信号出力端から該第1のスイッチ回路、該負荷回路、及び該第2のスイッチ回路を介して該信号端に至る第2の信号経路と該第1の信号経路とが切換可能に設けられることを特徴とする出力回路。 - 該第1の信号経路及び該第2の信号経路の何れか一方に直列に挿入された抵抗素子を更に含むことを特徴とする請求項7記載の出力回路。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/055092 WO2008111192A1 (ja) | 2007-03-14 | 2007-03-14 | 出力回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2008111192A1 JPWO2008111192A1 (ja) | 2010-06-24 |
JP4952783B2 true JP4952783B2 (ja) | 2012-06-13 |
Family
ID=39759143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009503833A Active JP4952783B2 (ja) | 2007-03-14 | 2007-03-14 | 出力回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8067964B2 (ja) |
JP (1) | JP4952783B2 (ja) |
KR (1) | KR101164308B1 (ja) |
CN (1) | CN101636906B (ja) |
GB (1) | GB2460772A (ja) |
WO (1) | WO2008111192A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210038571A (ko) | 2018-08-02 | 2021-04-07 | 닛토덴코 가부시키가이샤 | 히터 및 히터 부착 물품 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101456207B1 (ko) * | 2013-08-05 | 2014-11-03 | 숭실대학교산학협력단 | 스위칭 커패시터를 이용한 슬루 레이트 조절 장치 |
JP6264142B2 (ja) * | 2014-03-27 | 2018-01-24 | 富士通株式会社 | 送信装置 |
KR20170009213A (ko) * | 2015-07-16 | 2017-01-25 | 에스케이하이닉스 주식회사 | 입출력 회로, 입출력 네트워크 및 이들을 포함하는 입출력 시스템 |
JPWO2017085885A1 (ja) * | 2015-11-20 | 2018-02-15 | 三菱電機株式会社 | スイッチ駆動回路 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09172356A (ja) * | 1995-12-19 | 1997-06-30 | Fujitsu Ltd | 遅延回路及びデジタル位相ロック回路 |
JPH1188130A (ja) * | 1997-09-05 | 1999-03-30 | Toko Inc | 波形整形回路 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0548420A (ja) * | 1991-08-08 | 1993-02-26 | Fujitsu Ltd | 出力回路 |
US5949259A (en) * | 1997-11-19 | 1999-09-07 | Atmel Corporation | Zero-delay slew-rate controlled output buffer |
US6389092B1 (en) * | 1999-08-11 | 2002-05-14 | Newport Communications, Inc. | Stable phase locked loop having separated pole |
US6414524B1 (en) * | 2001-03-20 | 2002-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Digital output buffer for MOSFET device |
JP2005217840A (ja) * | 2004-01-30 | 2005-08-11 | Matsushita Electric Ind Co Ltd | 出力ドライバ回路 |
JP4301404B2 (ja) * | 2004-02-17 | 2009-07-22 | 川崎マイクロエレクトロニクス株式会社 | 出力バッファ回路 |
US20060038596A1 (en) * | 2004-08-18 | 2006-02-23 | Binan Wang | Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems |
-
2007
- 2007-03-14 KR KR1020097019147A patent/KR101164308B1/ko not_active IP Right Cessation
- 2007-03-14 JP JP2009503833A patent/JP4952783B2/ja active Active
- 2007-03-14 WO PCT/JP2007/055092 patent/WO2008111192A1/ja active Application Filing
- 2007-03-14 CN CN200780052151XA patent/CN101636906B/zh active Active
-
2009
- 2009-09-02 US US12/552,942 patent/US8067964B2/en active Active
- 2009-09-02 GB GB0915231A patent/GB2460772A/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09172356A (ja) * | 1995-12-19 | 1997-06-30 | Fujitsu Ltd | 遅延回路及びデジタル位相ロック回路 |
JPH1188130A (ja) * | 1997-09-05 | 1999-03-30 | Toko Inc | 波形整形回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210038571A (ko) | 2018-08-02 | 2021-04-07 | 닛토덴코 가부시키가이샤 | 히터 및 히터 부착 물품 |
Also Published As
Publication number | Publication date |
---|---|
KR101164308B1 (ko) | 2012-07-10 |
WO2008111192A1 (ja) | 2008-09-18 |
JPWO2008111192A1 (ja) | 2010-06-24 |
CN101636906A (zh) | 2010-01-27 |
GB2460772A (en) | 2009-12-16 |
KR20100005020A (ko) | 2010-01-13 |
US8067964B2 (en) | 2011-11-29 |
US20090315606A1 (en) | 2009-12-24 |
CN101636906B (zh) | 2013-01-02 |
GB0915231D0 (en) | 2009-10-07 |
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