WO2008111192A1 - 出力回路 - Google Patents

出力回路 Download PDF

Info

Publication number
WO2008111192A1
WO2008111192A1 PCT/JP2007/055092 JP2007055092W WO2008111192A1 WO 2008111192 A1 WO2008111192 A1 WO 2008111192A1 JP 2007055092 W JP2007055092 W JP 2007055092W WO 2008111192 A1 WO2008111192 A1 WO 2008111192A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
signal
output
output circuit
load
Prior art date
Application number
PCT/JP2007/055092
Other languages
English (en)
French (fr)
Inventor
Tomoyuki Numata
Norio Nagase
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009503833A priority Critical patent/JP4952783B2/ja
Priority to CN200780052151XA priority patent/CN101636906B/zh
Priority to PCT/JP2007/055092 priority patent/WO2008111192A1/ja
Priority to KR1020097019147A priority patent/KR101164308B1/ko
Publication of WO2008111192A1 publication Critical patent/WO2008111192A1/ja
Priority to US12/552,942 priority patent/US8067964B2/en
Priority to GB0915231A priority patent/GB2460772A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/12—Shaping pulses by steepening leading or trailing edges
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

　本発明は、出力信号の立ち上がりの傾きと立ち下りの傾きとを合わせるように調整可能な比較的小さな規模の出力回路を提供することを目的とする。出力回路は、第１の電位と第２の電位との間で遷移する信号を信号出力端に出力する信号出力ユニットと、負荷量が可変の負荷回路と、信号出力端と負荷回路との間の電気的な導通／非導通を切替える第１のスイッチ回路を含むことを特徴とする。
PCT/JP2007/055092 2007-03-14 2007-03-14 出力回路 WO2008111192A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009503833A JP4952783B2 (ja) 2007-03-14 2007-03-14 出力回路
CN200780052151XA CN101636906B (zh) 2007-03-14 2007-03-14 输出电路
PCT/JP2007/055092 WO2008111192A1 (ja) 2007-03-14 2007-03-14 出力回路
KR1020097019147A KR101164308B1 (ko) 2007-03-14 2007-03-14 출력 회로
US12/552,942 US8067964B2 (en) 2007-03-14 2009-09-02 Output circuit
GB0915231A GB2460772A (en) 2007-03-14 2009-09-02 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055092 WO2008111192A1 (ja) 2007-03-14 2007-03-14 出力回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/552,942 Continuation US8067964B2 (en) 2007-03-14 2009-09-02 Output circuit

Publications (1)

Publication Number Publication Date
WO2008111192A1 true WO2008111192A1 (ja) 2008-09-18

Family

ID=39759143

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055092 WO2008111192A1 (ja) 2007-03-14 2007-03-14 出力回路

Country Status (6)

Country Link
US (1) US8067964B2 (ja)
JP (1) JP4952783B2 (ja)
KR (1) KR101164308B1 (ja)
CN (1) CN101636906B (ja)
GB (1) GB2460772A (ja)
WO (1) WO2008111192A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015192204A (ja) * 2014-03-27 2015-11-02 富士通株式会社 送信装置
WO2017085885A1 (ja) * 2015-11-20 2017-05-26 三菱電機株式会社 スイッチ駆動回路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101456207B1 (ko) * 2013-08-05 2014-11-03 숭실대학교산학협력단 스위칭 커패시터를 이용한 슬루 레이트 조절 장치
KR20170009213A (ko) * 2015-07-16 2017-01-25 에스케이하이닉스 주식회사 입출력 회로, 입출력 네트워크 및 이들을 포함하는 입출력 시스템
JP7162462B2 (ja) 2018-08-02 2022-10-28 日東電工株式会社 ヒータ及びヒータ付物品

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548420A (ja) * 1991-08-08 1993-02-26 Fujitsu Ltd 出力回路
JPH09172356A (ja) * 1995-12-19 1997-06-30 Fujitsu Ltd 遅延回路及びデジタル位相ロック回路
JPH1188130A (ja) * 1997-09-05 1999-03-30 Toko Inc 波形整形回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949259A (en) 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US6389092B1 (en) * 1999-08-11 2002-05-14 Newport Communications, Inc. Stable phase locked loop having separated pole
US6414524B1 (en) * 2001-03-20 2002-07-02 Taiwan Semiconductor Manufacturing Co., Ltd Digital output buffer for MOSFET device
JP2005217840A (ja) * 2004-01-30 2005-08-11 Matsushita Electric Ind Co Ltd 出力ドライバ回路
JP4301404B2 (ja) * 2004-02-17 2009-07-22 川崎マイクロエレクトロニクス株式会社 出力バッファ回路
US20060038596A1 (en) * 2004-08-18 2006-02-23 Binan Wang Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548420A (ja) * 1991-08-08 1993-02-26 Fujitsu Ltd 出力回路
JPH09172356A (ja) * 1995-12-19 1997-06-30 Fujitsu Ltd 遅延回路及びデジタル位相ロック回路
JPH1188130A (ja) * 1997-09-05 1999-03-30 Toko Inc 波形整形回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015192204A (ja) * 2014-03-27 2015-11-02 富士通株式会社 送信装置
WO2017085885A1 (ja) * 2015-11-20 2017-05-26 三菱電機株式会社 スイッチ駆動回路
JPWO2017085885A1 (ja) * 2015-11-20 2018-02-15 三菱電機株式会社 スイッチ駆動回路

Also Published As

Publication number Publication date
GB2460772A (en) 2009-12-16
JPWO2008111192A1 (ja) 2010-06-24
GB0915231D0 (en) 2009-10-07
JP4952783B2 (ja) 2012-06-13
CN101636906A (zh) 2010-01-27
US20090315606A1 (en) 2009-12-24
KR101164308B1 (ko) 2012-07-10
US8067964B2 (en) 2011-11-29
CN101636906B (zh) 2013-01-02
KR20100005020A (ko) 2010-01-13

Similar Documents

Publication Publication Date Title
TW200735015A (en) Shift register circuit
TW200636753A (en) Pre-charge voltage supply circuit of semiconductor device
WO2007143283A3 (en) Power supply system
TW200713736A (en) Multiple output buck converter
TW200606605A (en) Circuitry and control method for charging capacitive loads
TW200735511A (en) A voltage switch apparatus
WO2008111192A1 (ja) 出力回路
WO2009058940A3 (en) A smart current attenuator for energy conservation in appliances
EP2237296A3 (en) Circuit breaker switching control system
MX2013013032A (es) Circuito de conmutacion y modulo de semiconductor.
WO2014053911A3 (en) Analog to digital converter including a pre-charge circuit
WO2011005641A3 (en) Communication mode swapping for telecommunications devices
EP2424095A3 (en) Switching device compensation circuit
WO2012078922A3 (en) A digital-to-analog converter with non-uniform resolution
TW200710784A (en) Systems and methods for generating reference voltages
PT2093737E (pt) Módulo de fim de linha ativo
WO2013066592A3 (en) A mixed voltage non-volatile memory integrated circuit with power saving
WO2011139441A3 (en) Open circuit detector and method therefore
TW201129980A (en) Read only memory cell for storing a multiple bit value
WO2009003063A3 (en) A current mode boost converter using slope compensation
WO2015024778A3 (de) Getakteter elektronischer energiewandler
GB2454438A (en) Multiple output multiple topology voltage converter
MY152084A (en) Manual reset pressure switch
TW200709564A (en) Reference voltage generating circuit
EP2717470A3 (en) Low/high voltage selector

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780052151.X

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07738562

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009503833

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 0915231

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20070314

WWE Wipo information: entry into national phase

Ref document number: 1020097019147

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

ENPC Correction to former announcement of entry into national phase, pct application did not enter into the national phase

Ref country code: GB

122 Ep: pct application non-entry in european phase

Ref document number: 07738562

Country of ref document: EP

Kind code of ref document: A1