JP4942757B2 - 低減されたゲートドーピングを用いる半導体構造体を形成する方法 - Google Patents
低減されたゲートドーピングを用いる半導体構造体を形成する方法 Download PDFInfo
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- JP4942757B2 JP4942757B2 JP2008537791A JP2008537791A JP4942757B2 JP 4942757 B2 JP4942757 B2 JP 4942757B2 JP 2008537791 A JP2008537791 A JP 2008537791A JP 2008537791 A JP2008537791 A JP 2008537791A JP 4942757 B2 JP4942757 B2 JP 4942757B2
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000000034 method Methods 0.000 title claims description 44
- 238000003860 storage Methods 0.000 claims description 51
- 239000007943 implant Substances 0.000 claims description 31
- 239000002019 doping agent Substances 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 4
- 239000007924 injection Substances 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 125000004429 atom Chemical group 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910015890 BF2 Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Description
図面における要素は簡略化及び明瞭化のために図示されており、必ずしも寸法化されていないことを当業者は理解している。例えば、図面における幾らかの要素の寸法は、本発明の実施形態の理解を容易にするために、その他の要素に対して誇張されている。
Claims (5)
- 半導体構造体を形成する方法において、
記憶領域及び論理領域を有する基板を提供する工程と、
前記基板上にゲート誘電体層を形成する工程と、
前記ゲート誘電体層上に半導体ゲート層を形成する工程と、
前記記憶領域に第一の半導体ゲートを形成し、かつ前記論理領域に第二の半導体ゲートを形成するために前記半導体ゲート層をパターン化する工程と、
前記記憶領域に拡散低減注入を実施する工程と、
前記基板の、前記第一の半導体ゲートに隣接してソース/ドレイン領域を形成する工程と、を含み、
前記第一の半導体ゲートの少なくとも一部は前記第二の半導体ゲートの少なくとも一部よりもより低いドーパント濃度の第一の導電性タイプを有し、かつ
前記記憶領域は、第一の導電性タイプのデバイスを有する第一のデバイス領域と、前記第一の導電性タイプとは異なる第二の導電性タイプのデバイスを有する第二のデバイス領域とを更に含み、前記拡散低減注入は、前記第一及び第二の半導体ゲートを形成する前に、前記記憶領域の第一のデバイス領域においてのみ半導体ゲート層に実施される、
方法。 - 請求項1に記載の方法は更に、
前記半導体ゲート層に、前記第一の導電性タイプを有する第一の注入を実施する工程を含む、方法。 - 前記第一の注入は、ブランケット注入として実施される、請求項2に記載の方法。
- 請求項2に記載の方法は更に、
前記記憶領域の半導体ゲート層をマスクした状態にて、前記論理領域の半導体ゲート層に第一の導電性タイプを有する第二の注入を実施する工程を含み、
前記第二の注入は前記第一の注入の前又は後に実施される、方法。 - 半導体構造体を形成するための方法であって、
記憶領域及び論理領域を有する基板を提供する工程と、
前記記憶領域に第一のp型デバイスを形成するとともに前記論理領域に第二のp型デバイスを形成する工程と、を含み、
前記第一のp型デバイスの半導体ゲートの少なくとも一部は前記第二のp型デバイスの半導体ゲートの少なくとも一部よりもp型ドーパントの濃度が低く、前記第一及び第二のp型デバイスの各々の半導体ゲートはp型ドーパントの濃度がゼロではなく、
前記形成工程は更に、半導体ゲート層に拡散低減注入を実施する工程を含み、
前記記憶領域は、p型デバイスを有する第一のデバイス領域とn型デバイスを有する第二のデバイス領域とを更に含み、前記拡散低減注入は、前記第一及び第二のp型デバイスの半導体ゲートを形成する前に、前記記憶領域の第一のデバイス領域においてのみ半導体ゲート層に実施される、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US11/260,849 | 2005-10-26 | ||
US11/260,849 US7488635B2 (en) | 2005-10-26 | 2005-10-26 | Semiconductor structure with reduced gate doping and methods for forming thereof |
PCT/US2006/040863 WO2007050419A2 (en) | 2005-10-26 | 2006-10-18 | Semiconductor structure with reduced gate doping and methods for forming thereof |
Publications (3)
Publication Number | Publication Date |
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JP2009514225A JP2009514225A (ja) | 2009-04-02 |
JP2009514225A5 JP2009514225A5 (ja) | 2009-11-26 |
JP4942757B2 true JP4942757B2 (ja) | 2012-05-30 |
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JP2008537791A Active JP4942757B2 (ja) | 2005-10-26 | 2006-10-18 | 低減されたゲートドーピングを用いる半導体構造体を形成する方法 |
Country Status (5)
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US (1) | US7488635B2 (ja) |
JP (1) | JP4942757B2 (ja) |
KR (1) | KR101252325B1 (ja) |
TW (1) | TWI429027B (ja) |
WO (1) | WO2007050419A2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI460827B (zh) * | 2010-03-31 | 2014-11-11 | Taiwan Memory Company | 快閃記憶體之製作方法 |
US8658506B1 (en) | 2011-04-06 | 2014-02-25 | Qualcomm Incorporated | Method and apparatus for selectively improving integrated device performance |
KR101934736B1 (ko) | 2012-08-31 | 2019-01-03 | 삼성전자 주식회사 | 반도체 장치 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04157766A (ja) * | 1990-10-20 | 1992-05-29 | Sony Corp | シリコンゲートpチャンネルMOS半導体装置の製造方法 |
JPH07176743A (ja) * | 1993-09-02 | 1995-07-14 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH10189758A (ja) * | 1996-12-20 | 1998-07-21 | Sony Corp | 半導体装置及びその製造方法 |
JPH10313098A (ja) * | 1997-05-14 | 1998-11-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5933721A (en) * | 1997-04-21 | 1999-08-03 | Advanced Micro Devices, Inc. | Method for fabricating differential threshold voltage transistor pair |
US6100568A (en) * | 1997-11-06 | 2000-08-08 | Motorola, Inc. | Semiconductor device including a memory cell and peripheral portion and method for forming same |
JP2003347429A (ja) * | 2002-05-27 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4555301A (en) * | 1983-06-20 | 1985-11-26 | At&T Bell Laboratories | Formation of heterostructures by pulsed melting of precursor material |
US5468666A (en) * | 1993-04-29 | 1995-11-21 | Texas Instruments Incorporated | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip |
US5652162A (en) | 1996-06-13 | 1997-07-29 | Taiwan Semiconductor Manufacturing, Company Ltd. | Method for fabricating flat ROM devices using memory array cells with concave channels |
US5885877A (en) * | 1997-04-21 | 1999-03-23 | Advanced Micro Devices, Inc. | Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric |
US6225151B1 (en) * | 1997-06-09 | 2001-05-01 | Advanced Micro Devices, Inc. | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion |
JP2000106401A (ja) | 1998-09-29 | 2000-04-11 | Sony Corp | メモリ素子およびその製造方法ならびに集積回路 |
US6773972B2 (en) * | 2001-01-03 | 2004-08-10 | Texas Instruments Incorporated | Memory cell with transistors having relatively high threshold voltages in response to selective gate doping |
US6894356B2 (en) * | 2002-03-15 | 2005-05-17 | Integrated Device Technology, Inc. | SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same |
US6878578B1 (en) | 2002-04-26 | 2005-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a high quality chemical oxide on a freshly cleaned silicon surface as a native oxide replacement |
US20030218218A1 (en) * | 2002-05-21 | 2003-11-27 | Samir Chaudhry | SRAM cell with reduced standby leakage current and method for forming the same |
JP4535669B2 (ja) * | 2002-09-13 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7112857B2 (en) * | 2004-07-06 | 2006-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations |
-
2005
- 2005-10-26 US US11/260,849 patent/US7488635B2/en active Active
-
2006
- 2006-10-16 TW TW095138067A patent/TWI429027B/zh active
- 2006-10-18 KR KR1020087009911A patent/KR101252325B1/ko active IP Right Grant
- 2006-10-18 JP JP2008537791A patent/JP4942757B2/ja active Active
- 2006-10-18 WO PCT/US2006/040863 patent/WO2007050419A2/en active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04157766A (ja) * | 1990-10-20 | 1992-05-29 | Sony Corp | シリコンゲートpチャンネルMOS半導体装置の製造方法 |
JPH07176743A (ja) * | 1993-09-02 | 1995-07-14 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH10189758A (ja) * | 1996-12-20 | 1998-07-21 | Sony Corp | 半導体装置及びその製造方法 |
US5933721A (en) * | 1997-04-21 | 1999-08-03 | Advanced Micro Devices, Inc. | Method for fabricating differential threshold voltage transistor pair |
JPH10313098A (ja) * | 1997-05-14 | 1998-11-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6100568A (en) * | 1997-11-06 | 2000-08-08 | Motorola, Inc. | Semiconductor device including a memory cell and peripheral portion and method for forming same |
JP2003347429A (ja) * | 2002-05-27 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
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KR20080061377A (ko) | 2008-07-02 |
JP2009514225A (ja) | 2009-04-02 |
WO2007050419A2 (en) | 2007-05-03 |
US20070093043A1 (en) | 2007-04-26 |
TWI429027B (zh) | 2014-03-01 |
KR101252325B1 (ko) | 2013-04-08 |
US7488635B2 (en) | 2009-02-10 |
TW200721393A (en) | 2007-06-01 |
WO2007050419A3 (en) | 2007-07-26 |
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