JP4898020B2 - シリアル・デバイスからメモリおよびレジスタをセット・アップする方法 - Google Patents

シリアル・デバイスからメモリおよびレジスタをセット・アップする方法 Download PDF

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JP4898020B2
JP4898020B2 JP2001176874A JP2001176874A JP4898020B2 JP 4898020 B2 JP4898020 B2 JP 4898020B2 JP 2001176874 A JP2001176874 A JP 2001176874A JP 2001176874 A JP2001176874 A JP 2001176874A JP 4898020 B2 JP4898020 B2 JP 4898020B2
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configuration data
programmable logic
configuration
address
logic device
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JP2002118459A5 (enExample
JP2002118459A (ja
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ロジャー・メイ
アンドリュー・ドラッパー
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Altera Corp
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Altera Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Microcomputers (AREA)
  • Stored Programmes (AREA)
JP2001176874A 2000-06-12 2001-06-12 シリアル・デバイスからメモリおよびレジスタをセット・アップする方法 Expired - Fee Related JP4898020B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US21109400P 2000-06-12 2000-06-12
US09/668704 2000-09-22
US09/668,704 US6732263B1 (en) 2000-06-12 2000-09-22 Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
US60/211094 2000-09-22

Publications (3)

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JP2002118459A JP2002118459A (ja) 2002-04-19
JP2002118459A5 JP2002118459A5 (enExample) 2008-08-07
JP4898020B2 true JP4898020B2 (ja) 2012-03-14

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JP2001176874A Expired - Fee Related JP4898020B2 (ja) 2000-06-12 2001-06-12 シリアル・デバイスからメモリおよびレジスタをセット・アップする方法

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US (2) US6732263B1 (enExample)
EP (1) EP1215586A3 (enExample)
JP (1) JP4898020B2 (enExample)

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US6732263B1 (en) * 2000-06-12 2004-05-04 Altera Corporation Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
NZ508052A (en) 2000-11-09 2003-06-30 Derek Ward Programmable controller
GB0228900D0 (en) * 2002-12-11 2003-01-15 Ml Lab Plc Cancer Immunotherapy
US20040117717A1 (en) * 2002-12-17 2004-06-17 Swoboda Gary L. Apparatus and method for a flush procedure in an interrupted trace stream
US7030646B1 (en) * 2003-09-02 2006-04-18 Altera Corporation Functional pre-configuration of a programmable logic device
US20050102573A1 (en) * 2003-11-03 2005-05-12 Macronix International Co., Ltd. In-circuit configuration architecture for embedded configurable logic array
US7081771B2 (en) * 2004-02-20 2006-07-25 Lattice Semiconductor Corporation Upgradeable and reconfigurable programmable logic device
US7519802B2 (en) 2004-05-05 2009-04-14 Hewlett-Packard Development Company, L.P. System and method for configuring a computer system
US7512813B2 (en) * 2004-05-28 2009-03-31 International Business Machines Corporation Method for system level protection of field programmable logic devices
EP1632825B1 (en) * 2004-09-03 2008-10-29 Derek Ward Improvements in or relating to programmable logic controller and related electronic devices
US8116209B2 (en) * 2005-05-11 2012-02-14 Alcatel Lucent Methods and apparatus for identifying errors and stranded resources in networks
US7538574B1 (en) 2005-12-05 2009-05-26 Lattice Semiconductor Corporation Transparent field reconfiguration for programmable logic devices
US7375549B1 (en) 2006-02-09 2008-05-20 Lattice Semiconductor Corporation Reconfiguration of programmable logic devices
US7627806B1 (en) * 2006-03-01 2009-12-01 Altera Corporation Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
US7822958B1 (en) * 2006-03-10 2010-10-26 Altera Corporation Booting mechanism for FPGA-based embedded system
US7554358B1 (en) 2006-04-05 2009-06-30 Lattice Semiconductor Corporation Programmable logic devices with user non-volatile memory
US7459931B1 (en) 2006-04-05 2008-12-02 Lattice Semiconductor Corporation Programmable logic devices with transparent field reconfiguration
US7378873B1 (en) 2006-06-02 2008-05-27 Lattice Semiconductor Corporation Programmable logic device providing a serial peripheral interface
US7495970B1 (en) * 2006-06-02 2009-02-24 Lattice Semiconductor Corporation Flexible memory architectures for programmable logic devices
US7570078B1 (en) 2006-06-02 2009-08-04 Lattice Semiconductor Corporation Programmable logic device providing serial peripheral interfaces
JP5045036B2 (ja) * 2006-09-05 2012-10-10 富士ゼロックス株式会社 データ処理装置
EP1967973A1 (en) * 2007-03-07 2008-09-10 Matsushita Electric Industrial Co., Ltd. A method of configuring embedded application-specific functional blocks
JP5158187B2 (ja) * 2008-02-28 2013-03-06 富士通株式会社 ストレージ装置、ストレージ制御装置およびストレージ制御方法
US8566565B2 (en) * 2008-07-10 2013-10-22 Via Technologies, Inc. Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications
US8598908B1 (en) * 2009-05-01 2013-12-03 Cypress Semiconductor Corp. Built in system bus interface for random access to programmable logic registers
EP2345968A1 (en) * 2010-01-13 2011-07-20 Panasonic Corporation Method and apparatus for reconfiguring a reconfigurable device
US9442732B2 (en) 2012-03-19 2016-09-13 Via Technologies, Inc. Running state power saving via reduced instructions per clock operation
US9673824B2 (en) * 2012-10-26 2017-06-06 Altera Corporation Techniques and circuitry for configuring and calibrating an integrated circuit
US9459672B2 (en) 2013-06-28 2016-10-04 International Business Machines Corporation Capacitance management
US9330011B2 (en) 2013-09-20 2016-05-03 Via Alliance Semiconductor Co., Ltd. Microprocessor with integrated NOP slide detector
US10019260B2 (en) 2013-09-20 2018-07-10 Via Alliance Semiconductor Co., Ltd Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match
US9755902B2 (en) 2014-05-20 2017-09-05 Via Alliance Semiconductor Co., Ltd. Dynamic system configuration based on cloud-collaborative experimentation
US9575778B2 (en) 2014-05-20 2017-02-21 Via Alliance Semiconductor Co., Ltd. Dynamically configurable system based on cloud-collaborative experimentation
US20170153892A1 (en) * 2015-11-30 2017-06-01 Intel Corporation Instruction And Logic For Programmable Fabric Hierarchy And Cache
CN107193560B (zh) * 2017-05-16 2020-08-04 奇瑞汽车股份有限公司 配置更新方法及装置
US10128851B1 (en) * 2017-11-27 2018-11-13 Intel Corporation Techniques for programming circuits using mode decoding

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DE69031257T2 (de) * 1989-09-21 1998-02-12 Texas Instruments Inc Integrierte Schaltung mit einem eingebetteten digitalen Signalprozessor
JP2544020B2 (ja) 1990-11-19 1996-10-16 川崎製鉄株式会社 プログラマブル論理素子
JPH04286213A (ja) * 1991-03-14 1992-10-12 Kawasaki Steel Corp コンフィグレーション容易なプログラマブルロジックデバイス
JP3310990B2 (ja) * 1991-04-15 2002-08-05 キヤノン株式会社 電子機器
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US6097211A (en) * 1996-07-18 2000-08-01 Altera Corporation Configuration memory integrated circuit
US6134707A (en) * 1996-11-14 2000-10-17 Altera Corporation Apparatus and method for in-system programming of integrated circuits containing programmable elements
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
WO2000031652A2 (en) * 1998-11-20 2000-06-02 Altera Corporation Reconfigurable programmable logic device computer system
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6535043B2 (en) * 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same
US6732263B1 (en) * 2000-06-12 2004-05-04 Altera Corporation Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
US6363019B1 (en) * 2000-11-03 2002-03-26 Xilinx, Inc. Method and circuit for verifying configuration of programmable logic device
US6567970B1 (en) * 2000-12-27 2003-05-20 Cypress Semiconductor Corp. PLD configuration architecture

Also Published As

Publication number Publication date
US7343483B1 (en) 2008-03-11
US6732263B1 (en) 2004-05-04
EP1215586A2 (en) 2002-06-19
EP1215586A3 (en) 2007-01-10
JP2002118459A (ja) 2002-04-19

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