JP4881557B2 - Manufacturing method of chip resistor - Google Patents

Manufacturing method of chip resistor Download PDF

Info

Publication number
JP4881557B2
JP4881557B2 JP2004380438A JP2004380438A JP4881557B2 JP 4881557 B2 JP4881557 B2 JP 4881557B2 JP 2004380438 A JP2004380438 A JP 2004380438A JP 2004380438 A JP2004380438 A JP 2004380438A JP 4881557 B2 JP4881557 B2 JP 4881557B2
Authority
JP
Japan
Prior art keywords
film
insulating substrate
laser beam
manufacturing
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004380438A
Other languages
Japanese (ja)
Other versions
JP2006186231A (en
Inventor
俊秀 吉田
英 遠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kamaya Electric Co Ltd
Original Assignee
Kamaya Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kamaya Electric Co Ltd filed Critical Kamaya Electric Co Ltd
Priority to JP2004380438A priority Critical patent/JP4881557B2/en
Publication of JP2006186231A publication Critical patent/JP2006186231A/en
Application granted granted Critical
Publication of JP4881557B2 publication Critical patent/JP4881557B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は外形の仕上りと抵抗値歩留が良好なチップ抵抗器の製造方法に関する。 The present invention relates to a method of manufacturing a chip resistor having a good outer shape and a good resistance value yield.

チップ抵抗器を製造するための従来方法としては、例えば、特開2001−118703号公報(特許文献1)に記載されたものを挙げることができる。これは、例えば、平面視で0.6mm×0.3mm以下の小型のチップ抵抗器を製造する過程において、電極部の形成後、抵抗体配設面に一対の互いに平行なガイド壁を突設するか、あるいは抵抗体配設面に略矩形枠状のガイド壁を突設し、このガイド壁内に抵抗体ペーストを印刷することにより、抵抗ペーストの印刷に伴なう滲みやダレを防止し、焼成された抵抗膜の厚みを均一にすることを目的とするものである。そして、特許文献1の製造方法では、絶縁基板に第一ブレーク溝と第二ブレーク溝とが予め形成され、所定工程において、これらブレーク溝に沿って分割されてチップ抵抗器が形成される。   As a conventional method for manufacturing a chip resistor, for example, one described in Japanese Patent Application Laid-Open No. 2001-118703 (Patent Document 1) can be cited. This is because, for example, in the process of manufacturing a small chip resistor having a size of 0.6 mm × 0.3 mm or less in plan view, a pair of mutually parallel guide walls is projected on the resistor arrangement surface after the electrode portion is formed. Alternatively, a guide wall having a substantially rectangular frame shape is projected on the resistor mounting surface, and the resistor paste is printed in the guide wall to prevent bleeding and sagging associated with the printing of the resistor paste. The purpose is to make the thickness of the fired resistive film uniform. And in the manufacturing method of patent document 1, the 1st break groove | channel and the 2nd break groove | channel are previously formed in the insulated substrate, and it divides | segments along these break grooves in a predetermined process, and forms a chip resistor.

また従来のチップ抵抗器の製造工程では、絶縁基板を縦横に切断するため、厚さ40μm、直径50mm程度の円板状ブレードを備えるダイシングソーが使用されている。アルミナセラミック等からなる絶縁基板は、比較的硬度が大きく被削性が乏しいため、これをダイシングソーで切断した場合、厚さ方向に最後まで切断されず、切断面にバリが残るという問題点があった。この問題点は、特許文献1の技術に依っては解決し得るものではない。   In a conventional chip resistor manufacturing process, a dicing saw having a disk-like blade having a thickness of about 40 μm and a diameter of about 50 mm is used to cut an insulating substrate vertically and horizontally. An insulating substrate made of alumina ceramic or the like has a relatively large hardness and poor machinability, so when it is cut with a dicing saw, it is not cut to the end in the thickness direction, leaving a burr on the cut surface. there were. This problem cannot be solved by the technique of Patent Document 1.

この問題を解決し得るものとして、特開2002−313612号公報(特許文献2)に記載されたものを挙げることができる。特許文献2では、集合基板上に複数の抵抗体が形成され、抵抗体の上面側に樹脂材料からなる20〜50μmの保護コート膜が形成され、この保護コート膜が下になるように粘着シート上に集合基板が設置され、集合基板の裏面からブレードで切断される。切断時には、ブレードを挟んで左右に押し広げようとする力が集合基板に作用するものの、基板切断の瞬間においても、保護コート膜部分は繋がっているため、切断途中における基板の割れは防止され、また保護コート膜は基板よりも被削性が優れているため、切断面のバリの発生は防止される。
特開2001−118703号公報 特開2002−313612号公報
As what can solve this problem, the thing described in Unexamined-Japanese-Patent No. 2002-313612 (patent document 2) can be mentioned. In Patent Document 2, a plurality of resistors are formed on a collective substrate, a protective coating film of 20 to 50 μm made of a resin material is formed on the upper surface side of the resistors, and an adhesive sheet so that this protective coating film is on the bottom The collective substrate is installed on the top, and is cut with a blade from the back surface of the collective substrate. At the time of cutting, although the force to spread left and right across the blade acts on the collective substrate, even at the moment of substrate cutting, the protective coat film part is connected, so the cracking of the substrate during cutting is prevented, Moreover, since the protective coat film has better machinability than the substrate, the occurrence of burrs on the cut surface is prevented.
JP 2001-118703 A JP 2002-313612 A

各種電子機器の小型化と高機能化に伴なって、超小型チップ抵抗器に対する需要も増加しており、例えば、平面的な外形寸法が0.6mm×0.3mm、あるいは0.4mm×0.2mmといったチップ抵抗器に対する要望がある。
これに対して、特許文献1に記載のチップ抵抗器の製造方法に依れば、抵抗ペーストの印刷に伴なう滲みやダレを防止し、焼成された抵抗膜の厚みを均一にすることは可能であるが、下記のように幾つかの課題が残されている。
(1)ガイド壁の形成に伴ない材料や工程が増加する。
(2)ガイド壁はガラスペーストのスクリーン印刷により形成されるため、この印刷時にガイド壁内の領域まで滲みやダレが生じ、ガイド壁内の抵抗膜の形状に影響を与えて抵抗膜にバラツキを生じさせる。
(3)保護コートは個々の抵抗膜を覆うように個々の微小領域に印刷形成するものであるため、保護コートの断面が御椀形状になり、実装機における吸着ミスを増大させる。
(4)製造プロセスの中間において、絶縁基板に予め設けられた第一及び第二のブレーク溝に沿って絶縁基板を分割するので、小型で薄い絶縁基板にあっては、製造プロセス中の焼成に伴なう加熱の繰り返しによる絶縁基板の反りや熱歪みによる分割溝間隔の不均一が生じて分割後の分割形状が安定せず、製造プロセス中の絶縁基板の破損が生じやすい。
With the miniaturization and high functionality of various electronic devices, the demand for ultra-small chip resistors is also increasing. For example, the planar external dimensions are 0.6 mm × 0.3 mm or 0.4 mm × 0. There is a demand for a chip resistor of 2 mm.
On the other hand, according to the chip resistor manufacturing method described in Patent Document 1, it is possible to prevent bleeding and sagging associated with printing of the resistive paste and to make the thickness of the fired resistive film uniform. Although it is possible, some problems remain as follows.
(1) Materials and processes increase with the formation of guide walls.
(2) Since the guide wall is formed by screen printing of glass paste, bleeding or sagging occurs in the area of the guide wall during printing, affecting the shape of the resistance film in the guide wall and causing variations in the resistance film. Cause it to occur.
(3) Since the protective coat is formed by printing on each minute area so as to cover each resistive film, the cross section of the protective coat becomes a bowl shape, increasing the adsorption mistake in the mounting machine.
(4) In the middle of the manufacturing process, the insulating substrate is divided along the first and second break grooves provided in advance on the insulating substrate. The insulating substrate warps due to repeated heating, and the division groove spacing becomes non-uniform due to thermal distortion, so that the divided shape after division is not stable, and the insulating substrate is easily damaged during the manufacturing process.

また特許文献2においても、工数の複雑化、工数時間の増加、材料費の上昇等に関して下記のような課題が残されている。
(1)絶縁基板はブレードにより縦横に切断されるため、切断に多大な時間を要する。
(2)切削されるブレード幅分を見越した大きさの絶縁基板を要するため無駄が生じる。
(3)保護コート膜面の平坦性を確保するために厳格な品質管理が求められ、また硬度と被削性の異なる材料が貼り合わされた絶縁基板の採用を余儀なくされるので材料費が上昇する。
(4)粘着シートによる材料費の上昇と、粘着シートに固定する工程が必要になる。
Also in Patent Document 2, the following problems remain regarding complication of man-hours, increase in man-hours, increase in material costs, and the like.
(1) Since the insulating substrate is cut vertically and horizontally by a blade, it takes a long time to cut.
(2) Waste is generated because an insulating substrate of a size that allows for the width of the blade to be cut is required.
(3) Strict quality control is required to ensure the flatness of the protective coating film surface, and the use of an insulating substrate bonded with materials with different hardness and machinability is unavoidable, leading to an increase in material costs. .
(4) Increase in material costs due to the pressure-sensitive adhesive sheet and a process for fixing to the pressure-sensitive adhesive sheet are required.

本発明は、上記課題を解決するものであり、その目的は、平面的な外形寸法が0.6mm×0.3mm以下で、且つ比較的薄い絶縁基板を用いた超小型チップ抵抗器を実現するに際して、所定寸法の絶縁基板から可能な限り多くのチップ抵抗器を生産することができて、抵抗ペーストの印刷に伴なう滲みやダレの防止が図れ、焼成された抵抗膜の厚さを均一にできて、保護コート膜の分断面及び絶縁基板分割に伴なう分割面の形状精度が良好で、工数の簡略化及び工数時間の圧縮が実現可能なチップ抵抗器の製造方法を提供することにある。 The present invention solves the above-described problems, and an object of the present invention is to realize a microchip resistor having a planar outer dimension of 0.6 mm × 0.3 mm or less and using a relatively thin insulating substrate. At the same time, it is possible to produce as many chip resistors as possible from an insulating substrate of a predetermined size, to prevent bleeding and sagging associated with the printing of the resistance paste, and to uniform the thickness of the fired resistive film made, the protective coating film dividing surface and the insulating substrate dividing accompanied dividing surface shape precision is good in the of the simplification and man-hour temporal compression of steps to provide a process for the preparation of possible chip resistor realized It is in.

本発明の上記課題は下記の手段によって解決される。   The above-described problems of the present invention are solved by the following means.

(1)分割溝が予め刻設されていない絶縁基板を使用し、該絶縁基板の所定領域に一対の電極膜を多数形成し、各一対の電極膜の一部に重畳するように抵抗膜を多数印刷して焼成し、該抵抗膜に抵抗値調整のトリミング溝を形成し、該トリミング溝を含む前記抵抗膜の所定領域に保護コート膜を形成するチップ抵抗器の製造方法において、前記電極膜の一部に重畳する抵抗膜の印刷が前記絶縁基板の一次方向に帯状に印刷して乾燥する工程と、
該工程で乾燥してできた前記帯状の抵抗膜の不要部をレーザービームにより除去してから該抵抗膜を焼成する工程と、該抵抗膜にトリミングしてから、前記抵抗膜の一次方向にある帯状保護コート膜を形する工程と、該保護コート膜と前記電極膜をレーザービームにより一次方向と二次方向に所定の間隔で分断すると同時に絶縁基板にも分割溝を刻設する工程とを含むことを特徴とするチップ抵抗器の製造方法。
(1) Using an insulating substrate in which the division grooves are not engraved in advance, a large number of pairs of electrode films are formed in a predetermined region of the insulating substrate , and a resistive film is formed so as to overlap a part of each pair of electrode films. In the method of manufacturing a chip resistor, the electrode film is formed by printing and firing a large number , forming a trimming groove for adjusting a resistance value in the resistance film, and forming a protective coating film in a predetermined region of the resistance film including the trimming groove. Printing the resistive film superimposed on a part of the substrate in a strip shape in the primary direction of the insulating substrate and drying,
The unnecessary portion of the strip-shaped resistive film formed by drying in the process is removed by a laser beam, and then the resistive film is baked, and after trimming the resistive film, the resistive film is in the primary direction. a step that form a belt-shaped protective coating film, Engineering you engraved also split grooves at the same time the insulating substrate when cutting at predetermined intervals in the primary direction and the secondary direction by the laser beam the electrode film and-holding protection coat film A method for manufacturing a chip resistor, comprising:

(2)前記帯状抵抗膜の不要部は、基本波又はUV波長の領域を有するレーザービームを照射して除去する工程と、前記電極膜及び前記保護コート膜を、一次方向と二次方向に所定の間隔で分断すると同時に絶縁基板への分割溝刻は、UV波長領域を有するレーザービームを照射する工程とから成ることを特徴とする請求項1に記載のチップ抵抗器の製造方法。 (2) the unnecessary portion of the strip of resistive film, and removing by irradiating a laser beam having a region of the fundamental wave or UV wavelengths, the electrode layer and the protective coating layer, the primary direction and the secondary direction given the division Mizokoku set to the same time the insulating substrate when cutting at intervals, the manufacturing method of the chip resistor according to claim 1, characterized in that comprising a step of irradiating a laser beam having a UV wavelength region.

上記(1)に記載のチップ抵抗器の製造方法では、分割溝が予め刻設されていない絶縁基板を使用し、保護コート膜及び電極膜をそれぞれ所定間隔で分断しながら、同時に絶縁基板にも分割溝を刻設するので、電極膜や抵抗膜等の要素膜形成に伴なう焼成の繰り返しによる絶縁基板の反りや分割溝間隔の歪みが抑制され、例えば、厚さ0.2mm以下等の極薄の絶縁基板を使用する自由度が大きくなることができる。
上記(1)の製造方法では、焼成前の乾燥した状態で帯状の抵抗膜の不要部を除去するので、厚膜の抵抗ペーストを使用しても、抵抗膜の幅を自由に設定することができて、チップ抵抗器に負荷できる消費電力も大きく設定することができる。
上記(1)の製造方法では、厚膜の抵抗ペーストを使用しても、ダレや滲みの発生が無くなり、抵抗膜の膜厚が両側縁に至るまで略均一に且つ良好に仕上げることができる。これにより、抵抗膜を焼成した後の抵抗値分布のバラツキを抑制できる。
In the manufacturing method of the chip resistor described in (1) above, an insulating substrate in which a dividing groove is not engraved in advance is used, and the protective coating film and the electrode film are divided at a predetermined interval, and are simultaneously applied to the insulating substrate. Since the dividing groove is engraved, warpage of the insulating substrate and distortion of the dividing groove interval due to repeated firing accompanying the formation of the element film such as the electrode film and the resistance film are suppressed. For example, the thickness is 0.2 mm or less. The degree of freedom to use an extremely thin insulating substrate can be increased.
In the manufacturing method of (1) above, unnecessary portions of the strip-shaped resistive film are removed in a dried state before firing, so that the width of the resistive film can be freely set even when a thick resistive paste is used. In addition, the power consumption that can be loaded on the chip resistor can be set large.
In the manufacturing method (1), even when a thick film resistance paste is used, no sagging or bleeding occurs, and the film thickness of the resistance film can be finished substantially uniformly and well until it reaches both side edges. Thereby, the dispersion | variation in resistance value distribution after baking a resistance film can be suppressed.

上記(2)に記載のチップ抵抗器の製造方法は、従来の製造方法のように微小領域に個々に保護コート膜を形成する際に表面が御椀型に盛り上がったものとは異なり、保護コート膜を帯状に複数形成した後にレーザービームの照射により分断するものであるため、表面を略平坦に形成することができる。このように保護コート膜が平坦であれば、実装機の吸着ミスを低減することができる。
上記(2)の製造方法では、抵抗膜のパターン化、電極膜及び保護コート膜等の分断、絶縁基板への分割溝の刻設を、レーザービームの照射により行うため、隣接するチップ抵抗器どうしの間隔を狭小にできて、一枚の絶縁基板から生産し得るチップ抵抗器の個数を増加させることができる。
上記(2)の製造方法では、UV波長領域を有するレーザービーム照射することにより、電極膜及び保護コート膜を分断するので、アブレーション効果による分断時の飛散物を大幅に抑制することができる。また厚さ0.2mm以下等の極薄の絶縁基板であっても、絶縁基板を透過して切断してしまうこと無く、安定した分割溝を刻設することができる。
上記(2)製造方法では、レーザービームの照射により電極膜及び保護コート膜をそれぞれ所定の間隔で分断し、その際にレーザービームは絶縁基板の表面まで達し、絶縁基板に分割溝をも刻設する。したがって、電極膜の分断面と絶縁基板の分割面とが略面一に形成され、また保護コート膜の分断面と絶縁基板の分割面とも略面一に形成される。
The manufacturing method of the chip resistor described in the above (2) is different from the conventional manufacturing method in which the surface is raised in a bowl shape when the protective coating film is individually formed in a minute region. Since a plurality of films are formed in a strip shape and then divided by irradiation with a laser beam, the surface can be formed substantially flat. If the protective coating film is flat as described above, it is possible to reduce a suction error of the mounting machine.
In the manufacturing method of (2) above, the patterning of the resistance film, the division of the electrode film and the protective coating film, and the formation of the dividing groove on the insulating substrate are performed by laser beam irradiation. The number of chip resistors that can be produced from a single insulating substrate can be increased.
In the manufacturing method of (2) above, the electrode film and the protective coating film are divided by irradiating a laser beam having a UV wavelength region, so that scattered matter at the time of division due to the ablation effect can be significantly suppressed. Moreover, even if it is an ultra-thin insulating substrate having a thickness of 0.2 mm or less, a stable dividing groove can be formed without passing through the insulating substrate and cutting.
In the above (2) manufacturing method, the electrode film and the protective coating film are each divided at predetermined intervals by laser beam irradiation. At that time, the laser beam reaches the surface of the insulating substrate, and the dividing groove is also engraved on the insulating substrate. To do. Therefore, the divided section of the electrode film and the dividing surface of the insulating substrate are formed substantially flush with each other, and the dividing section of the protective coating film and the divided surface of the insulating substrate are also formed substantially flush with each other.

本発明のチップ抵抗器は、予め分割溝が刻設されていないアルミナセラミックから成る絶縁基板に形成した電極膜間にメタルグレーズによる厚膜の抵抗ペーストを用いて抵抗膜を帯状に印刷し、乾燥させた後に抵抗膜の不要部をレーザービームの照射により除去し、除去後に残された抵抗膜を焼成し、その後、抵抗膜をトリミングして抵抗値調整のための溝を形成し、トリミング溝を含む抵抗膜の所定領域を保護コート膜で覆った後に、レーザービームを照射することにより、電極膜と少なくとも保護コート膜を所定の間隔でそれぞれ分断し、このとき、レーザービームは絶縁基板の表面まで達して分割溝も刻設する。
これにより、平面的な外形寸法が、例えば0.6mm×0.3mmや0.4mm×0.2mm、絶縁基板の厚さが0.2mm以下といった超小型・薄型のチップ抵抗器の製造に際して、特許文献1のようなガイド壁を不要とし、且つ厚膜の抵抗ペーストの印刷に伴なうダレや滲みを抑制し、膜厚が抵抗膜の両側部に至るまで略均一になり、抵抗膜を焼成した後の抵抗値分布のバラツキも抑制できる。絶縁基板に予め形成された分割溝が無く、且つ薄い絶縁基板であっても、製造プロセスにおける加熱の繰り返しによる絶縁基板の反りが無く、分割溝間の平行度の歪みも無く、製造プロセスにおける絶縁基板の破損が回避できて、分割に伴なう外形寸法精度を良好に維持できる。保護コート膜を個々のチップ抵抗器毎の狭小範囲に形成する従来方法に比べて、保護コート膜の両側面にダレや滲みが生じず、範囲も広く略平坦な保護コート膜が得られ、回路基板への実装に際して実装機の吸着ミスの低減ができる。
The chip resistor of the present invention prints a resistive film in a strip shape using a thick-film resistive paste made of metal glaze between electrode films formed on an insulating substrate made of alumina ceramic that is not previously engraved with a dividing groove, and then dried. Then, unnecessary portions of the resistance film are removed by laser beam irradiation, and the remaining resistance film is baked after the removal, and then the resistance film is trimmed to form a groove for adjusting the resistance value, and the trimming groove is formed. After covering a predetermined region of the resistive film with a protective coat film, the electrode film and at least the protective coat film are divided at predetermined intervals by irradiating a laser beam, and at this time, the laser beam is directed to the surface of the insulating substrate. Reach and also divide the dividing groove.
As a result, when manufacturing an ultra-small and thin chip resistor having a planar outer dimension of, for example, 0.6 mm × 0.3 mm or 0.4 mm × 0.2 mm, and an insulating substrate thickness of 0.2 mm or less, The guide wall as in Patent Document 1 is not necessary, and sagging and bleeding associated with the printing of the thick resistive paste are suppressed, and the film thickness becomes substantially uniform until both sides of the resistive film are formed. Variations in the resistance value distribution after firing can also be suppressed. Even if the insulating substrate has no split groove formed in advance and is a thin insulating substrate, there is no warping of the insulating substrate due to repeated heating in the manufacturing process, no parallelism distortion between the split grooves, and insulation in the manufacturing process Breakage of the substrate can be avoided, and the outer dimensional accuracy accompanying the division can be maintained well. Compared with the conventional method in which the protective coating film is formed in a narrow range for each chip resistor, sagging and bleeding do not occur on both sides of the protective coating film, and a broad and substantially flat protective coating film is obtained. It is possible to reduce the suction error of the mounting machine when mounting on the substrate.

以下、本発明の実施形態について、図面を参照して更に詳細に説明するが、本発明は下記の実施形態に限定されるものではない。
図1は超小型で薄型のチップ抵抗器を製造する工程を示す概略図である。図1において、一枚の絶縁基板から得られるチップ抵抗器の個数は、実際の製造工程によりも少なく図示されているが、実際の超小型チップ抵抗器の製造工程では、大型絶縁基板から数百個以上のチップ抵抗器が製造される。
図1(a)では、平面的な外形寸法が0.6×0.3mm以下の超小型チップ抵抗器を製造することを目的に、分割溝が予め刻設されていない厚さ0.2mm以下のアルミナセラミック基板11が使用される。最初に、メタルグレーズ系又はレジネートによる導体ペーストを用いて、電極膜12をアルミナセラミック基板の個々の領域毎に形成する。
なお、フェースアップ実装を目的とするチップ抵抗器を製造する場合には、表側の電極膜12に対応するように基板裏側にも電極膜(図示せず)を形成する。この裏側の電極膜は個々の領域毎又は所定の領域毎に帯状に形成する。
Hereinafter, although an embodiment of the present invention is described in detail with reference to drawings, the present invention is not limited to the following embodiment.
FIG. 1 is a schematic view showing a process of manufacturing an ultra-small and thin chip resistor. In FIG. 1, the number of chip resistors obtained from a single insulating substrate is shown to be smaller than that in an actual manufacturing process. More than one chip resistor is manufactured.
In FIG. 1A, for the purpose of manufacturing an ultra-small chip resistor having a planar outer dimension of 0.6 × 0.3 mm or less, a thickness of 0.2 mm or less in which no divisional grooves are previously engraved. The alumina ceramic substrate 11 is used. First, the electrode film 12 is formed for each region of the alumina ceramic substrate using a metal paste or resin paste made of resinate.
When manufacturing a chip resistor intended for face-up mounting, an electrode film (not shown) is also formed on the back side of the substrate so as to correspond to the front side electrode film 12. The electrode film on the back side is formed in a strip shape for each individual region or for each predetermined region.

次に、図1(b)に示したように、一対の表電極となる電極膜12の一部に重畳するように、メタルグレーズ系の厚膜の抵抗ペーストを用いて抵抗膜13aを印刷し、これを乾燥する Next, as shown in FIG. 1B, a resistive film 13a is printed using a metal glaze thick resistive paste so as to overlap a part of the electrode film 12 to be a pair of front electrodes. Dry this .

次に、印刷後に乾燥された帯状の抵抗膜13aにおいて、絶縁基板11の方向(一次方向)における帯状の抵抗膜13aの不要部、もしくは表電極となる電極膜よりも幅広の抵抗膜のダレや滲みの範囲となった不要部(図示せず)をレーザービームの照射により除去する。図1(c)では、不要部をそれぞれ除去した絶縁基板11を示した。このように不要部をレーザービームの照射で除去することにより、個々の独立した抵抗膜13bが得られ、且つ、乾燥した状態でレーザービームを照射することにより不要部を除去した抵抗膜13bの一次方向の側縁部は、特許文献1のガイド壁に優る効果を発揮する。そして、続く抵抗膜の焼成工程を経ることにより、抵抗ペーストのダレや滲みのない抵抗膜の側縁部に至る略均一な膜厚を形成することができて、絶縁基板上に複数個形成される抵抗膜間の抵抗値分布のバラツキを抑制し、抵抗膜の形成範囲、及びこれの隣接間隔配設の自由度も大きくなり、絶縁基板の有効利用が可能になる。
抵抗膜の不要部を除去するレーザービームは、Nd:YAG、Nd:YLF、Nd:YVO4などの発振装置から発振された基本波(波長がほぼ1064nm)、または基本波を波長変換したUV波長領域(波長がほぼ262〜266nm)を有するレーザーを用いることができる。基本波の場合で、出力が0.5W、Qレートが10kHz、速度40mm/秒となる。またUV波長領域を有するレーザーの場合で、出力が0.5W、Qレートが30kHz、速度40mm/秒となる。なお、レーザービームは、作業効率を考慮して出力、Qレート、速度などを適宜調整する。
乾燥した抵抗膜の不要部を、UV波長領域を有するレーザービーム照射で除去した場合にはUVレーザー特有のアブレーション、すなわち、非熱発生的な効果が得られ、一方、基本波の波長領域を有するレーザービームを照射して除去した場合には、乾燥した抵抗膜にレーザービームを照射するので、焼成した抵抗膜で見られる熱歪によるマイクロクラックが抵抗膜側縁に発生することはない。
Next, in the strip-shaped resistive film 13a dried after printing, the sacrificial portion of the resistive film wider than the unnecessary portion of the strip-shaped resistive film 13a in the lateral direction (primary direction) of the insulating substrate 11 or the electrode film serving as the surface electrode is formed. Unnecessary portions (not shown) that have become blurred areas are removed by laser beam irradiation. FIG. 1C shows the insulating substrate 11 from which unnecessary portions are removed. Thus, by removing unnecessary portions by laser beam irradiation, individual independent resistance films 13b are obtained, and the primary resistance film 13b from which unnecessary portions are removed by irradiating a laser beam in a dry state. The side edge portion in the direction exhibits an effect superior to the guide wall of Patent Document 1. Then, through the subsequent baking process of the resistance film, a substantially uniform film thickness that reaches the side edge of the resistance film without sagging or bleeding of the resistance paste can be formed, and a plurality of films are formed on the insulating substrate. The dispersion of the resistance value distribution between the resistance films is suppressed, the range in which the resistance films are formed, and the degree of freedom in arranging the adjacent spaces between them is increased, and the insulating substrate can be effectively used.
The laser beam for removing unnecessary portions of the resistive film is a fundamental wave (wavelength is approximately 1064 nm) oscillated from an oscillation device such as Nd: YAG, Nd: YLF, Nd: YVO 4 , or a UV wavelength obtained by converting the wavelength of the fundamental wave. A laser having a region (wavelength of approximately 262 to 266 nm) can be used. In the case of the fundamental wave, the output is 0.5 W, the Q rate is 10 kHz, and the speed is 40 mm / second. In the case of a laser having a UV wavelength region, the output is 0.5 W, the Q rate is 30 kHz, and the speed is 40 mm / second. Note that the output, Q rate, speed, and the like of the laser beam are appropriately adjusted in consideration of work efficiency.
When unnecessary portions of the dried resistive film are removed by irradiation with a laser beam having a UV wavelength region, ablation unique to UV laser, that is, a non-heat generation effect is obtained, while having a wavelength region of the fundamental wave. When removed by irradiating with a laser beam, the dried resistive film is irradiated with the laser beam, so that microcracks due to thermal strain seen in the fired resistive film do not occur at the side edge of the resistive film.

抵抗膜を焼成した後、図1(d)に示したように、ガラスペースト厚膜により抵抗膜の上にアンダーコート膜14を形成し、アンダーコート膜14上からレーザービームを照射して抵抗値調整のためのトリミング溝15を形成する。ここでは、トリミング溝15の溝壁及び側縁がレーザービーム照射による熱的影響を軽減し、アンダーコート膜14が、レーザービーム照射に伴う飛散物が抵抗膜上へ付着することを防止する。   After the resistance film is baked, as shown in FIG. 1D, an undercoat film 14 is formed on the resistance film with a glass paste thick film, and the resistance value is obtained by irradiating the undercoat film 14 with a laser beam. A trimming groove 15 for adjustment is formed. Here, the groove wall and side edges of the trimming groove 15 reduce the thermal influence due to the laser beam irradiation, and the undercoat film 14 prevents the scattered matter accompanying the laser beam irradiation from adhering to the resistance film.

次に、図1(e)に示したように、アンダーコート膜14を覆ってトリミング溝15を埋めるように、ガラスペースト又は樹脂ペーストを用いて保護コート膜16を帯状に形成する。   Next, as shown in FIG. 1E, a protective coat film 16 is formed in a strip shape using glass paste or resin paste so as to fill the trimming groove 15 so as to cover the undercoat film 14.

保護コート膜16の形成後、絶縁基板の横方向(一次方向)及び縦方向(二次方向)に直交するようにUV波長領域を有するレーザービームを照射すると、図1(f)及び図2に示したような分割溝17a,17bが絶縁基板11に刻設される。すなわち、レーザービームは、表面の電極膜12や保護コート膜16(帯状のアンダーコート膜14も含む)を分断し、さらに下方の絶縁基板11まで達して分割溝17a,17bを絶縁基板11へ刻設する。
なお、図2は図1(f)におけるX−X線に沿った部分的な断面図である。
ここで、レーザービームは、Nd:YAG、Nd:YLF、Nd:YVO4などのレーザー発振装置から発振された基本波を波長変換したUV波長領域を有するUVレーザー、例えば、波長領域がほぼ266nm乃至ほぼ355nm、出力が0.5W、Qレートが30kHzのものを用いることができる。UVレーザーは絶縁基板の厚さ及び分割溝の深さに応じて、出力及びQレートが適宜調整される。
このように電極膜12や保護コート膜16の分断及び刻設時に、UVレーザーを使用することにより、特に、分断・刻設箇所の周辺への飛散物を抑制することが可能であり、UVレーザービーム照射に伴なうアブレーション効果をも有効活用することができる。
After the protective coat film 16 is formed, when a laser beam having a UV wavelength region is irradiated so as to be orthogonal to the horizontal direction (primary direction) and the vertical direction (secondary direction) of the insulating substrate, FIG. 1 (f) and FIG. Divided grooves 17 a and 17 b as shown are formed in the insulating substrate 11. That is, the laser beam divides the surface electrode film 12 and the protective coating film 16 (including the belt-like undercoat film 14), and further reaches the insulating substrate 11 below to cut the dividing grooves 17a and 17b into the insulating substrate 11. Set up.
FIG. 2 is a partial cross-sectional view taken along line XX in FIG.
Here, the laser beam is a UV laser having a UV wavelength region obtained by converting the wavelength of a fundamental wave oscillated from a laser oscillation device such as Nd: YAG, Nd: YLF, Nd: YVO 4 , for example, a wavelength region of approximately 266 nm to 266 nm. The one having approximately 355 nm, an output of 0.5 W, and a Q rate of 30 kHz can be used. The output and Q rate of the UV laser are appropriately adjusted according to the thickness of the insulating substrate and the depth of the dividing groove.
In this way, when the electrode film 12 and the protective coating film 16 are divided and engraved, by using a UV laser, it is possible in particular to suppress the scattered matter around the divided and engraved locations. The ablation effect accompanying beam irradiation can also be used effectively.

絶縁基板に分割溝17a,17bを刻設した後に、横方向(一次方向)の分割溝17aに沿って絶縁基板を分割し、図1(g)に示したような短冊状の基板18を形成し、さらに、各短冊状基板18を縦方向(二次方向)の分割溝17bに沿って分割し、図1(h)に示したような個々のチップ状にする。ここで、図1(h)のチップ抵抗器は電極膜の露出部にめっき膜19を形成したものであり、フェースダウン実装に対応する超小型チップ抵抗器として使用される。   After the dividing grooves 17a and 17b are formed in the insulating substrate, the insulating substrate is divided along the dividing groove 17a in the horizontal direction (primary direction) to form a strip-shaped substrate 18 as shown in FIG. Further, each strip-shaped substrate 18 is divided along the dividing grooves 17b in the vertical direction (secondary direction) to form individual chips as shown in FIG. Here, the chip resistor of FIG. 1 (h) is obtained by forming the plating film 19 on the exposed portion of the electrode film, and is used as an ultra-small chip resistor corresponding to face-down mounting.

次に、図3(a)は図1(g)とは異なる短冊状基板20の平面図であり、これは、絶縁基板の表裏の対応する位置に電極膜を形成し、絶縁基板を短冊状に分割したものであり、各短冊状基板20には表裏の電極膜を接続するための端面電極膜21が形成されている。端面電極膜21は、保護コート膜16に応じた材質により形成される。すなわち、保護コート膜16がガラスペーストから形成されている場合には、メタルグレーズの導電性ペーストを用いて端面電極膜21を形成し、一方、保護コート膜16が樹脂ペーストから形成されている場合には、導電性樹脂ペーストを用いて端面電極膜21を形成する。また端面電極膜は、短冊状の絶縁基板を積み重ねて、蒸着法やスパッター法で形成することができる。
短冊状基板20に端面電極膜21を形成した後に、縦方向(二次方向)の分割溝17bに沿って分割し、図3(b)に示したような個々のチップ抵抗器22が製造される。
このチップ抵抗器22では、回路基板における電極ランド(図示せず)と主にチップ抵抗器の端面電極とのはんだフィレット接合を主目的とするフェースダウン又はフェースアップの両面実装が可能である。
Next, FIG. 3A is a plan view of a strip-shaped substrate 20 different from that in FIG. 1G, which is formed by forming electrode films at corresponding positions on the front and back of the insulating substrate, and forming the insulating substrate into a strip-like shape. Each strip-shaped substrate 20 is formed with an end face electrode film 21 for connecting the front and back electrode films. The end face electrode film 21 is formed of a material corresponding to the protective coat film 16. That is, when the protective coat film 16 is formed from a glass paste, the end face electrode film 21 is formed using a metal glaze conductive paste, while the protective coat film 16 is formed from a resin paste. For this, the end face electrode film 21 is formed using a conductive resin paste. The end face electrode film can be formed by stacking strip-shaped insulating substrates and using a vapor deposition method or a sputtering method.
After the end face electrode film 21 is formed on the strip-shaped substrate 20, it is divided along the dividing grooves 17b in the vertical direction (secondary direction), and individual chip resistors 22 as shown in FIG. 3B are manufactured. The
The chip resistor 22 can be mounted on both sides of the face-down or face-up mainly for solder fillet joining between an electrode land (not shown) on the circuit board and mainly an end face electrode of the chip resistor.

次に、図4(a)(b)は図1とは異なるチップ抵抗器の製造方法における一部工程を示す平面図である。
この製造方法では、図1と同様なアルミナセラミック基板30を使用し、図4(a)に示したように、最初に、この基板30に帯状の抵抗膜31を複数印刷して乾燥させる。そして、抵抗膜31の乾燥後に、図4(b)に示したように、各抵抗膜31の一部に重畳するように、複数の電極膜32を帯状に形成する。つまり、抵抗膜31と電極膜32が、図1とは逆の順序で形成されるものであり、これ以降は、図1(c)〜(h)と同様の工程を行うことによりチップ抵抗器が製造できる。
Next, FIGS. 4A and 4B are plan views showing some steps in a method of manufacturing a chip resistor different from that shown in FIG.
In this manufacturing method, an alumina ceramic substrate 30 similar to that shown in FIG. 1 is used. As shown in FIG. 4A, first, a plurality of strip-like resistive films 31 are printed on the substrate 30 and dried. Then, after the resistance film 31 is dried, a plurality of electrode films 32 are formed in a strip shape so as to overlap a part of each resistance film 31 as shown in FIG. That is, the resistance film 31 and the electrode film 32 are formed in the reverse order to that shown in FIG. 1, and thereafter, the chip resistor is formed by performing the same steps as those shown in FIGS. Can be manufactured.

(a)〜(h)は本発明の製造方法における各工程を示す平面図である。(A)-(h) is a top view which shows each process in the manufacturing method of this invention. 図1(f)におけるX−X線に沿った部分的な断面図である。FIG. 2 is a partial cross-sectional view taken along line XX in FIG. (a)(b)は図1とは異なる短冊状基板とチップ抵抗器の平面図である。(A) and (b) are the top views of the strip-shaped board | substrate and chip resistor different from FIG. 図1とは異なる製造方法における一部工程を示す平面図である。It is a top view which shows the one part process in the manufacturing method different from FIG.

符号の説明Explanation of symbols

10 チップ抵抗器
11 絶縁基板
12 電極膜
13a 抵抗膜
13b 抵抗膜
16 保護コート膜
17a 分割溝(一次方向)
17b 分割溝(二次方向)
19 電極膜
22 チップ抵抗器
31 抵抗膜
32 電極膜
DESCRIPTION OF SYMBOLS 10 Chip resistor 11 Insulating substrate 12 Electrode film 13a Resistive film 13b Resistive film 16 Protective coating film 17a Dividing groove (primary direction)
17b Dividing groove (secondary direction)
19 Electrode film 22 Chip resistor 31 Resistive film 32 Electrode film

Claims (2)

分割溝が予め刻設されていない絶縁基板を使用し、該絶縁基板の所定領域に一対の電極膜を多数形成し、各一対の電極膜の一部に重畳するように抵抗膜を多数印刷して焼成し、該抵抗膜に抵抗値調整のトリミング溝を形成し、該トリミング溝を含む前記抵抗膜の所定領域に保護コート膜を形成するチップ抵抗器の製造方法において、
前記電極膜の一部に重畳する抵抗膜の印刷が前記絶縁基板の一次方向に帯状に印刷して乾燥する工程と、
該工程で乾燥してできた前記帯状の抵抗膜の不要部をレーザービームにより除去してから該抵抗膜を焼成する工程と、
該抵抗膜にトリミングしてから、前記抵抗膜の一次方向にある帯状保護コート膜を形する工程と、該保護コート膜と前記電極膜をレーザービームにより一次方向と二次方向に所定の間隔で分断すると同時に絶縁基板にも分割溝を刻設する工程とを含むことを特徴とするチップ抵抗器の製造方法。
Using an insulating substrate that has not been previously engraved with a dividing groove, a large number of pairs of electrode films are formed in a predetermined region of the insulating substrate , and a large number of resistance films are printed so as to overlap a part of each pair of electrode films. In the manufacturing method of the chip resistor, the trimming groove for adjusting the resistance value is formed in the resistance film, and the protective coat film is formed in a predetermined region of the resistance film including the trimming groove.
Printing a resistive film overlapping a part of the electrode film, printing in a strip shape in the primary direction of the insulating substrate and drying;
Removing unnecessary portions of the strip-shaped resistive film formed by drying in the process by laser beam, and then firing the resistive film;
After trimming to the resistor film, a step that form a belt-shaped protective coating layer on the primary direction of the resistance film,-holding protection coating film and the electrode film with a laser beam by a predetermined primary direction and the secondary direction method of manufacturing a chip resistor which comprises a degree Engineering when divided to simultaneously insulating substrate you engraved dividing grooves at intervals.
前記帯状抵抗膜の不要部は、基本波又はUV波長の領域を有するレーザービームを照射して除去する工程と
前記電極膜及び前記保護コート膜を、一次方向と二次方向に所定の間隔で分断すると同時に絶縁基板への分割溝刻は、UV波長領域を有するレーザービームを照射する工程とから成ることを特徴とする請求項1に記載のチップ抵抗器の製造方法。
Unnecessary portions of the strip-shaped resistance film, a step of removing by irradiating a laser beam having a region of the fundamental wave or UV wavelengths,
Division Mizokoku setting of the electrode film and the protective coating layer, the same time the insulating substrate when cutting at predetermined intervals in the primary direction and the secondary direction, be comprised of a step of irradiating a laser beam having a UV wavelength region A method of manufacturing a chip resistor according to claim 1.
JP2004380438A 2004-12-28 2004-12-28 Manufacturing method of chip resistor Expired - Fee Related JP4881557B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004380438A JP4881557B2 (en) 2004-12-28 2004-12-28 Manufacturing method of chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004380438A JP4881557B2 (en) 2004-12-28 2004-12-28 Manufacturing method of chip resistor

Publications (2)

Publication Number Publication Date
JP2006186231A JP2006186231A (en) 2006-07-13
JP4881557B2 true JP4881557B2 (en) 2012-02-22

Family

ID=36739105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004380438A Expired - Fee Related JP4881557B2 (en) 2004-12-28 2004-12-28 Manufacturing method of chip resistor

Country Status (1)

Country Link
JP (1) JP4881557B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10734141B2 (en) 2018-09-17 2020-08-04 Samsung Electro-Mechanics Co., Ltd. Electronic component and manufacturing method thereof
US10861625B2 (en) 2018-09-17 2020-12-08 Samsung Electro-Mechanics Co Ltd Electronic component and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013214667A (en) * 2012-04-03 2013-10-17 Ngk Spark Plug Co Ltd Ceramic wiring board manufacturing method
CN116031172B (en) * 2023-01-09 2024-02-13 上海泽丰半导体科技有限公司 Manufacturing method of large-size ceramic substrate and large-size ceramic substrate

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288402A (en) * 1985-06-15 1986-12-18 沖電気工業株式会社 Manufacture of resistor array
JPH0347289Y2 (en) * 1985-06-15 1991-10-08
JPH02198872A (en) * 1989-01-27 1990-08-07 Aisin Seiki Co Ltd Trimming method of resistor of thermal head
JPH05267025A (en) * 1992-03-23 1993-10-15 Towa Electron Kk Manufacture of chip part and manufacture of electronic part
JPH07211525A (en) * 1994-01-25 1995-08-11 Matsushita Electric Ind Co Ltd Manufacture of chip resistor
JPH11111513A (en) * 1997-09-30 1999-04-23 Kyocera Corp Manufacture of chip resistor
JP2001167914A (en) * 1999-12-08 2001-06-22 Rohm Co Ltd Dividing trench shape of insulating substrate
JP2002110401A (en) * 2000-09-29 2002-04-12 Matsushita Electric Ind Co Ltd Resistor and its manufacturing method
JP2002313613A (en) * 2001-04-18 2002-10-25 Matsushita Electric Ind Co Ltd Method of manufacturing chip electronic part
JP5042420B2 (en) * 2001-09-11 2012-10-03 三菱マテリアル株式会社 Manufacturing method of chip resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10734141B2 (en) 2018-09-17 2020-08-04 Samsung Electro-Mechanics Co., Ltd. Electronic component and manufacturing method thereof
US10861625B2 (en) 2018-09-17 2020-12-08 Samsung Electro-Mechanics Co Ltd Electronic component and manufacturing method thereof

Also Published As

Publication number Publication date
JP2006186231A (en) 2006-07-13

Similar Documents

Publication Publication Date Title
US6623111B2 (en) Multilayer piezoelectric device and method of producing the same and piezoelectric actuator
WO2015019590A1 (en) Resistor and method for manufacturing same
JP4078042B2 (en) Method for manufacturing chip-type electronic component having a plurality of elements
JP4881557B2 (en) Manufacturing method of chip resistor
US20060261924A1 (en) Method of forming passive electronic components on a substrate by direct write technique using shaped uniform laser beam
JP2004276386A (en) Splitting ceramic substrate and its manufacturing method
JP6615637B2 (en) Manufacturing method of chip resistor
JP4277633B2 (en) Manufacturing method of chip resistor
JP5042420B2 (en) Manufacturing method of chip resistor
JP2007173282A (en) Method of manufacturing electronic component
JP4745027B2 (en) Manufacturing method of chip resistor
JP6731246B2 (en) Manufacturing method of chip resistor
JP3358990B2 (en) Manufacturing method of chip type resistor
TWI817476B (en) Chip resistor and method of manufacturing chip resistor
JP3065743B2 (en) Manufacturing method of ceramic insulating substrate for electronic components
JP2001118705A (en) Chip resistor
WO2022045140A1 (en) Ceramic plate and method for manufacturing same, bonding substrate and method for manufacturing same, and circuit board and method for manufacturing same
JPH0442949A (en) Semiconductor device with dicing slit
JP7370192B2 (en) Method for manufacturing circuit boards for electronic devices
WO2022131337A1 (en) Ceramic plate and method for manufacturing same, composite board and method for manufacturing same, and circuit board and method for manufacturing same
JPH11111513A (en) Manufacture of chip resistor
JP2005086131A (en) Method for manufacturing ceramic electronic component
JP2002343615A (en) Method for manufacturing thick-film chip resistor
JP3712520B2 (en) Manufacturing method of multilayer ceramic substrate
JP3766663B2 (en) Manufacturing method of chip parts

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070620

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100518

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111108

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111205

R150 Certificate of patent or registration of utility model

Ref document number: 4881557

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141209

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees