JP4873901B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4873901B2 JP4873901B2 JP2005233182A JP2005233182A JP4873901B2 JP 4873901 B2 JP4873901 B2 JP 4873901B2 JP 2005233182 A JP2005233182 A JP 2005233182A JP 2005233182 A JP2005233182 A JP 2005233182A JP 4873901 B2 JP4873901 B2 JP 4873901B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- metal wiring
- semiconductor device
- metal
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Wire Bonding (AREA)
Description
2,2A 導電性バンプ
3 電気絶縁樹脂
4 金属配線パターン
5 フリップチップボンデイング装置ヘッド
6 電気絶縁樹脂
Claims (1)
- 電子部品に設けられた導電性バンプと、前記導電性バンプの厚さより薄く、金属配線パターンの全面を被覆するソルダーレジストとを対向配置する工程と、
前記導電性バンプを前記ソルダーレジストに接触させ、前記ソルダーレジストに熱、荷重、及び超音波を印加する工程と、
前記導電性バンプを押し込み、前記ソルダーレジストの前記導電性バンプと接触する部分を排除して、前記金属配線パターンの一部を露出する工程と、
前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記電子部品と前記ソルダーレジストとの間に隙間を有する状態で、かつ前記導電性バンプの一部を前記ソルダーレジストから露出した状態で前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程とを備え、前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程の後、前記金属配線パターンの一部と前記導電性バンプとが接合された部分をアンダーフィル封止または電子部品封止をする工程を備えることを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005233182A JP4873901B2 (ja) | 2004-09-21 | 2005-08-11 | 半導体装置の製造方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004273697 | 2004-09-21 | ||
JP2004273697 | 2004-09-21 | ||
JP2005233182A JP4873901B2 (ja) | 2004-09-21 | 2005-08-11 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006121042A JP2006121042A (ja) | 2006-05-11 |
JP4873901B2 true JP4873901B2 (ja) | 2012-02-08 |
Family
ID=36538595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005233182A Expired - Fee Related JP4873901B2 (ja) | 2004-09-21 | 2005-08-11 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4873901B2 (ja) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11150150A (ja) * | 1997-11-18 | 1999-06-02 | Sumitomo Bakelite Co Ltd | 半導体搭載用基板とその製造方法及び半導体チップの実装方法 |
JP3119230B2 (ja) * | 1998-03-03 | 2000-12-18 | 日本電気株式会社 | 樹脂フィルムおよびこれを用いた電子部品の接続方法 |
JP2000036520A (ja) * | 1998-05-15 | 2000-02-02 | Nec Corp | フリップチップ実装方法及び装置 |
JP3914332B2 (ja) * | 1998-05-18 | 2007-05-16 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP4097378B2 (ja) * | 1999-01-29 | 2008-06-11 | 松下電器産業株式会社 | 電子部品の実装方法及びその装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP3533665B1 (ja) * | 2002-12-17 | 2004-05-31 | オムロン株式会社 | 電子部品モジュールの製造方法、並びに電磁波読み取り可能なデータキャリアの製造方法。 |
-
2005
- 2005-08-11 JP JP2005233182A patent/JP4873901B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006121042A (ja) | 2006-05-11 |
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