JP4851559B2 - Threshold circuit - Google Patents

Description

  The present invention relates to a threshold circuit used for a sensor node or the like, and more particularly to a technique for reducing the power consumption of the threshold circuit.

  FIG. 17 shows a configuration of a conventional sensor node system in which a threshold circuit is used (see, for example, Patent Document 1). The sensor node system includes a sensor node chip 50 and a receiving device 60. The sensor node chip 50 performs threshold processing on a sensor element 51 that detects a physical quantity to be measured, a sensor circuit 52 that amplifies and outputs a signal detected by the sensor element 51, and an output signal of the sensor circuit 52, for example. Output from the threshold circuit 53 output as detection data, a CPU 54 that performs processing for compressing detection data, processing for adding chip identification information to detection data, and the like, a memory 55 that stores a program for the CPU 54, and the CPU 54. A wireless unit 56 that wirelessly transmits detection data to the receiving device 60 and a power source 57 that supplies power to each component of the sensor node chip 50 are provided.

  A circuit diagram of a conventional threshold circuit is shown in FIG. 18 (see, for example, Non-Patent Document 1). In this threshold circuit, the first and second PMOS transistors Q100 and Q101 and the first NMOS transistor Q102 are connected in series between a first common potential VDD (power supply potential) and a second common potential (ground potential). The gate terminals of the transistors Q100, Q101, Q102 are made common and connected to the input terminal IN, and the connection point between the drain terminal of the second PMOS transistor Q101 and the drain terminal of the first NMOS transistor Q102 is It is connected to the output terminal OUT. The source terminal of the third PMOS transistor Q103 is connected to the connection point between the drain terminal of the first PMOS transistor Q100 and the source terminal of the second PMOS transistor Q101, and the gate terminal of the third PMOS transistor Q103 is output. Connected to the terminal OUT, the drain terminal of the third PMOS transistor Q103 is connected to the ground potential.

The operation of the conventional threshold circuit shown in FIG. 18 will be described using the input / output characteristics shown in FIG. In FIG. 19, the horizontal axis indicates the voltage V (IN) of the input terminal IN, and the vertical axis indicates the voltage V (OUT) of the output terminal OUT.
First, the case where the voltage V (IN) of the input terminal IN transits from Low to High will be described. When the voltage V (IN) at the input terminal IN is Low, the first NMOS transistor Q102 is in the off state, the first and second PMOS transistors Q100 and Q101 are in the on state, and the voltage V (OUT) at the output terminal OUT. Becomes High. At this time, the third PMOS transistor Q103 is in an off state.

  When the voltage V (IN) at the input terminal IN increases, the first NMOS transistor Q102 is turned on, and when the voltage V (IN) at the input terminal IN reaches the first threshold voltage Vthh, the voltage V at the output terminal OUT. (OUT) becomes Low. The first threshold voltage Vthh is determined by the ratio between the driving power of the first and second PMOS transistors Q100 and Q101 and the driving power of the first NMOS transistor Q102.

  Next, a case where the voltage V (IN) of the input terminal IN transitions from High to Low will be described. When the voltage V (IN) of the input terminal IN is High, the first and second PMOS transistors Q100 and Q101 are in an off state, the first NMOS transistor Q102 is in an on state, and the third PMOS transistor Q103 is in an on state. It is. Therefore, the connection point between the drain terminal of the first PMOS transistor Q100 and the source terminal of the second PMOS transistor Q101 is the ground potential.

  When the voltage V (IN) at the input terminal IN decreases and the first and second PMOS transistors Q100 and Q101 are turned on and the first NMOS transistor Q102 is turned off, the voltage V (OUT ) Rises, and the third PMOS transistor Q103 approaches the OFF state. When the voltage V (IN) at the input terminal IN reaches the second threshold voltage Vthl, the voltage V (OUT) at the output terminal OUT becomes High. When the voltage V (OUT) at the output terminal OUT is Low, the third PMOS transistor Q103 is in the on state, and the first and second PMOS transistors Q100 and Q101 increase the voltage V (OUT) at the output terminal OUT. Therefore, the second threshold voltage Vthl is smaller than the first threshold voltage Vthh.

  As described above, in the threshold circuit shown in FIG. 18, the threshold voltage Vthh when the voltage V (IN) at the input terminal IN transits from Low to High and the voltage V (IN) at the input terminal IN goes from High to Low. Since the threshold voltage Vthl at the time of transition is different, even if the voltage V (IN) of the input terminal IN fluctuates in the vicinity of the threshold voltage, noise called a glitch is not generated in the output signal.

Japanese Patent Laid-Open No. 2004-024551

Sung-Mo Kang, Yusuf Leblebici, “Cmos Digital Integrated Circuits: Analysis and Design”, 2nd edition, William C Brown Pub, September 1998, p. 341-345

  When the threshold circuit shown in FIG. 18 is applied to the sensor node chip shown in FIG. 17, when the output of the sensor circuit gradually transitions from Low to High, a large through current flows through the transistors Q100 to Q102 of the threshold circuit, In particular, when the output of the sensor circuit holds an intermediate potential between Low and High, a large current continues to flow during that period. Since a battery is generally used as a power supply for the sensor node chip, there is a problem that if a large through current continues to flow through the threshold circuit, the operation time of the sensor node chip operating with a limited energy source is shortened. It was.

  The present invention has been made to solve the above-described problems, and an object thereof is to reduce the power consumption of a threshold circuit.

In the threshold circuit of the present invention (first and fourth embodiments), the gate terminal is connected to the input terminal, the source terminal is connected to the first common potential, the drain terminal is connected to the output terminal, and the input A first first polarity transistor that is turned on when the voltage at the terminal is lower than a predetermined logic threshold and turned off when the voltage is higher than the logic threshold; and a drain terminal of the first first polarity transistor is the first terminal And a current limiting unit that is connected to the output terminal, has a second terminal connected to a second common potential, limits current flowing from the first terminal to the second terminal, and the first first A charge storage unit that is connected to a drain terminal of the polarity transistor and the output terminal and stores a charge by a charging current when the first first polarity transistor is in an ON state, and a current value of the current limiting unit is The sub-microampere is set, and the current limiting unit is controlled based on the voltage of the output terminal, and increases the current value from a picoampere level to a microampere level according to a voltage change of the output terminal. It is what .

In one configuration example (fifth embodiment) of the threshold circuit according to the present invention, the current limiting unit includes a drain terminal connected to the drain terminal and the output terminal of the first first polarity transistor, A first second polarity transistor having a terminal connected to the second common potential; a gate terminal connected to the drain terminal and the output terminal of the first first polarity transistor; And a second first polarity transistor connected to a common potential and having a drain terminal connected to a gate terminal of the first second polarity transistor.
In one configuration example (sixth embodiment) of the threshold circuit of the present invention, the current limiting unit controls the voltage of the gate terminal of the first second polarity transistor based on the voltage of the output terminal. A voltage control voltage source for controlling the gate terminal of the first second polarity transistor to change with a voltage change amount smaller than a voltage change amount of the output terminal. It is characterized by.

In one configuration example (seventh embodiment) of the threshold circuit of the present invention, the voltage control voltage source has a first terminal connected to the output terminal, and a second terminal connected to the first first circuit. A first capacitor connected to the gate terminal of the bipolar transistor, a first terminal connected to the gate terminal of the first second polarity transistor, and a second terminal connected to the second common potential And the second capacitor element thus formed.
In one configuration example (eighth embodiment) of the threshold circuit of the present invention, the voltage control voltage source has a gate terminal connected to the output terminal, and a drain terminal of the first second polarity transistor. It is connected to a connection point between a gate terminal and a drain terminal of the second first polarity transistor, and is composed of a second second polarity transistor whose source terminal is connected to the second common potential. To do.
Further, in one configuration example (ninth and tenth embodiments) of the threshold circuit according to the present invention, the voltage control voltage source has a drain terminal connected to the gate terminal of the first second polarity transistor and the second terminal. A second second polarity transistor having a source terminal connected to the second common potential, a gate terminal and a drain terminal connected to the output terminal, connected to a connection point with the drain terminal of the first polarity transistor; The source terminal is composed of one or more third second polarity transistors connected to the gate terminal of the second second polarity transistor.

In one configuration example of the threshold circuit according to the present invention (eleventh embodiment), the voltage control voltage source has a drain terminal connected to the gate terminal of the first second polarity transistor and the second first polarity. A second second polarity transistor connected to a connection point with the drain terminal of the transistor, a source terminal connected to the second common potential, and a source terminal connected to the gate terminal of the second second polarity transistor. A third terminal of the second polarity transistor, a gate terminal connected to the output terminal, a drain terminal connected to the first common potential, and a source terminal connected to the gate terminal and drain of the third second polarity transistor. And a fourth second polarity transistor connected to the terminal.
Further, in one configuration example (twelfth embodiment) of the threshold circuit of the present invention, the gate terminal further includes a gate terminal of the first second polarity transistor and a drain terminal of the second first polarity transistor. A third first polarity transistor having a source terminal connected to the first common potential and a drain terminal connected to a source terminal of the first first polarity transistor. It is what.
In one configuration example (thirteenth embodiment) of the threshold circuit according to the present invention, the voltage control voltage source further includes a source terminal of the second second polarity transistor and the second common potential. A fifth terminal having a gate terminal connected to the output terminal, a drain terminal connected to the source terminal of the second second polarity transistor, and a source terminal connected to the second common potential. A bipolar transistor is provided.

Further , in one configuration example (fifth embodiment) of the threshold circuit of the present invention, initialization is performed such that the voltage of the gate terminal of the first second polarity transistor is set to the second common potential during initialization. A switch is provided.
Further, in one configuration example of the threshold circuit according to the present invention (the ninth and tenth embodiments), the voltage of the gate terminal of the second second polarity transistor is further set to the second common potential during initialization. An initialization switch is provided.
Further, one configuration example (eleventh embodiment) of the threshold circuit according to the present invention is further inserted between the drain terminal of the fourth second polarity transistor and the first common potential, and is initialized. It is characterized by comprising a switch that is sometimes turned off and turned on at steady state.
Further, in one configuration example (fourteenth embodiment) of the threshold circuit of the present invention, the gate terminal is connected to the input terminal, the source terminal is connected to the first common potential, and the drain terminal is connected to the output terminal. A first first polarity transistor that is turned on when the voltage at the input terminal is lower than a predetermined logic threshold and turned off when the voltage is higher than the logic threshold; and a first terminal that has the first terminal as the first polarity transistor A current limiter that is connected to the drain terminal and the output terminal, has a second terminal connected to a second common potential, and limits a current flowing from the first terminal to the second terminal; A charge storage unit connected to the drain terminal of the first polarity transistor and the output terminal for storing charge by a charging current when the first first polarity transistor is in an ON state; the current limiting unit; And a transfer gate of the inserted ON state between the power terminal, the current value of the current limiting unit is characterized in being set below the sub-microampere.

  According to the present invention, the threshold circuit is configured such that the gate terminal is connected to the input terminal, the source terminal is connected to the first common potential, the drain terminal is connected to the output terminal, and the voltage of the input terminal is greater than the predetermined logic threshold. A first first polarity transistor that is on when it is low and off when it is above a logic threshold; a first terminal connected to a drain terminal and an output terminal of the first first polarity transistor; The terminal is connected to the second common potential, and is connected to the current limiting unit that limits the current flowing from the first terminal to the second terminal, the drain terminal and the output terminal of the first first polarity transistor, and the first And a charge storage unit that stores a charge by a charging current when the first polarity transistor is turned on, and the current value of the current limiting unit is set to be equal to or lower than the sub-microampere, Even if the voltage of the child is held at an intermediate potential between the first common potential and the second common potential, the through current of the threshold circuit is suppressed by setting the current of the current limiter to be equal to or lower than the sub-microampere. Therefore, the power consumption of the threshold circuit can be reduced. As a result, if the threshold circuit of the present invention is used, the power consumption of the sensor node chip can be reduced to the nanowatt level. Therefore, it is not necessary to increase the power generation amount of the power supply unit of the sensor node chip, and the volume of the power generation mechanism can be reduced. Therefore, downsizing of the sensor node chip is achieved, and the sensor node chip can be embedded also in an object or a human part that could not be embedded due to size restrictions until now. Furthermore, the range of ubiquitous network services using the sensor node system can be expanded, and services with improved user convenience can be provided, which is highly effective.

  In the present invention, the current limiting unit is connected to the second common potential or a fixed potential set in a range from the second common potential to the threshold voltage of the second polarity transistor, and the drain terminal is connected to the first common potential. The gate of the first second polarity transistor is constituted by the first second polarity transistor connected to the drain terminal and the output terminal of one first polarity transistor and having the source terminal connected to the second common potential. When the terminal is connected to the second common potential, the through current of the threshold circuit can be reduced to about picoamperes, and the potential of the gate terminal of the first second polarity transistor is reduced to the threshold voltage of the second polarity transistor. When the range is larger than the second common potential, the threshold processing can be speeded up.

  Further, in the present invention, the current limiting unit is controlled based on the voltage of the output terminal, and the current value is increased according to the voltage change of the output terminal, thereby maintaining the effect of reducing the through current of the threshold circuit. The threshold processing can be speeded up.

  In the present invention, the current limiting unit is provided with a voltage control voltage source that controls the voltage of the gate terminal of the first second polarity transistor based on the voltage of the output terminal, and the voltage control voltage source is the voltage of the output terminal. By controlling so that the voltage of the gate terminal of the first second polarity transistor changes with a voltage change amount smaller than the change amount, it is possible to suppress a decrease in the logic threshold value of the threshold circuit, and the voltage range of the input terminal Even when the threshold value is high, the threshold processing can be performed.

  In the present invention, the voltage control voltage source is connected at the connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, the gate terminal being connected to the output terminal. By configuring the second second polarity transistor connected and having the source terminal connected to the second common potential, the second second polarity transistor can change the voltage at the gate terminal of the first second polarity transistor. Since it can be suppressed to a small value, a decrease in the logic threshold value of the threshold circuit can be suppressed, and even when the voltage range of the input terminal is high, the threshold processing can be performed.

  In the present invention, the voltage control voltage source is connected to the connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, and the source terminal is connected to the second terminal. A second second polarity transistor connected to the common potential; and one or more third polarity transistors having a gate terminal and a drain terminal connected to the output terminal, and a source terminal connected to the gate terminal of the second second polarity transistor. By comprising the second polarity transistor, the discharge time can be shortened even when the charge discharge time from the charge storage section is long, and the time for the voltage at the output terminal to transition from High to Low can be shortened. Can do.

  In the present invention, the gate terminal is further connected to a connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, and the source terminal is connected to the first common potential. By providing a third first polarity transistor whose drain terminal is connected to the source terminal of the first first polarity transistor, it is held near the logic threshold value of the threshold circuit when the voltage at the input terminal rises, Even when the first first polarity transistor is in an incompletely off state and the discharge of the charge in the charge storage unit does not proceed, the discharge of the charge in the charge storage unit is advanced, and the voltage of the output terminal is quickly changed from High to Low. The threshold value processing malfunction can be prevented.

  In the present invention, the voltage control voltage source is further inserted between the source terminal of the second second polarity transistor and the second common potential, the gate terminal is connected to the output terminal, and the drain terminal is the first terminal. By providing a fifth second polarity transistor connected to the source terminal of the second second polarity transistor and having the source terminal connected to the second common potential, the second second polarity transistor and the second polarity transistor after the threshold processing operation are provided. The current flowing through the second first polarity transistor can be suppressed, and the power consumption of the threshold circuit can be reduced.

  Further, in the present invention, the parasitic capacitance of the drain terminal of the first second polarity transistor can be separated from the charge storage unit by providing an on-state transfer gate between the current limiting unit and the output terminal. Therefore, it is possible to shorten the discharge time of the charge in the charge storage unit, and to shorten the time for the voltage at the output terminal to transition from High to Low.

  In the present invention, the threshold circuit can be initialized by providing an initialization switch that sets the voltage of the gate terminal of the first second polarity transistor to the second common potential at the time of initialization.

  Further, in the present invention, the threshold circuit can be initialized by providing an initialization switch for setting the voltage of the gate terminal of the second second polarity transistor to the second common potential at the time of initialization.

  The present invention further provides a switch between the drain terminal of the fourth second polarity transistor and the first common potential, which is turned off at the time of initialization and turned on at the time of steady state. Since the parasitic capacitance of the drain terminal of the second polarity transistor can be disconnected from the output terminal, the charge discharge time of the charge storage section can be shortened, and the time for the voltage of the output terminal to transition from High to Low is shortened. be able to.

It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 8th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 10th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 11th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 12th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 13th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 14th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 15th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold circuit based on the 16th Embodiment of this invention. It is a block diagram which shows the structure of the conventional sensor node system. It is a circuit diagram which shows the structure of the conventional threshold circuit. It is a figure which shows the input-output characteristic of the threshold circuit of FIG.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a threshold circuit according to the first embodiment of the present invention.
The threshold circuit of this embodiment includes a first PMOS transistor Q1 having a gate terminal connected to the input terminal IN, a source terminal connected to the power supply potential VDD, and a drain terminal connected to the output terminal OUT. A current limiter I1 having a terminal connected to the drain terminal and output terminal OUT of the first PMOS transistor Q1, and a second terminal grounded, and a first terminal serving as the drain terminal and output terminal of the first PMOS transistor Q1 The charge storage unit C1 is connected to OUT and the second terminal is grounded. As the current limiting unit I1, a current source that supplies a current of sub-microamperes or less is used, and as the charge storage unit C1, a capacitive element is used. Note that the current below sub-microampere means a current below 100 nA.

  The operation of this embodiment will be described. When the threshold circuit of this embodiment is applied to the sensor node chip 50 shown in FIG. 17, the voltage of the input terminal IN becomes Low when the sensor node chip 50 is initialized, the first PMOS transistor Q1 is turned on, Charge is stored in the charge storage portion C1, and the voltage at the output terminal OUT becomes High.

  When the output voltage of the sensor circuit 52 of the sensor node chip 50 increases from Low and the voltage at the input terminal IN rises, the first PMOS transistor Q1 approaches the off state. Here, when the threshold voltage of the first PMOS transistor Q1 is Vth, the voltage of the input terminal IN reaches a voltage near (VDD−Vth) when the current of the current limiter I1 is set to about sub-microamperes. By the way, the source-drain current of the first PMOS transistor Q1 becomes smaller than the current of the current limiting unit I1, and the charge charged in the charge storage unit C1 starts to flow to the current limiting unit I1. As a result, the voltage at the output terminal OUT decreases, and after the discharge time determined by the capacitance value of the charge storage unit C1 and the current value of the current limiting unit I1, the voltage at the output terminal OUT becomes Low. In this way, the threshold value processing operation using (VDD−Vth) as the logical threshold value is performed. Needless to say, when the voltage at the input terminal IN transitions from High to Low, the first PMOS transistor Q1 is turned on, and the voltage at the output terminal OUT transitions from Low to High.

  As described above, in the present embodiment, the charge accumulated in the charge accumulation unit C1 is extracted by the current limiting unit I1 with a current value of sub-microamperes or less. In the conventional threshold circuit shown in FIG. 18, when the voltage at the input terminal IN is held at an intermediate potential between the power supply potential VDD and the ground potential, a through current of several tens of microamperes flows through the transistors Q100 to Q102. . On the other hand, in the present embodiment, when the voltage at the input terminal IN is an intermediate potential between the power supply potential VDD and the ground potential, the through current flowing through the first PMOS transistor Q1 and the current limiting unit I1 is limited to the current. The current can be reduced to sub-microamperes or less set in the section I1. Therefore, if the threshold circuit of this embodiment is used, the power of the sensor node chip on which the threshold circuit is mounted can be reduced to the nanowatt level limit.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing a configuration of a threshold circuit according to the second embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the charge storage unit C1, the gate terminal and the source terminal are grounded, and the drain terminal is connected to the drain terminal and the output terminal OUT of the first PMOS transistor Q1. And the first NMOS transistor Q2.

  In the present embodiment, a first NMOS transistor Q2 is used as a current limiting unit instead of the current limiting unit I1 of the first embodiment. In the present embodiment, when the voltage at the input terminal IN is an intermediate potential between the power supply potential VDD and the ground potential, the through current flowing through the first PMOS transistor Q1 and the first NMOS transistor Q2 is converted into the first NMOS transistor. The magnitude of the leakage current of Q2 can be set, and the through current can be reduced to about picoampere compared to the through current of several tens of microamperes of the conventional threshold circuit.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of a threshold circuit according to the third embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the charge storage unit C1, the gate terminal is connected to the fixed potential terminal REF, the source terminal is grounded, and the drain terminal is the first PMOS transistor Q1. The first NMOS transistor Q3 is connected to the drain terminal and the output terminal OUT.

  In the present embodiment, by arbitrarily adjusting the voltage of the fixed potential terminal REF, that is, the gate voltage of the first NMOS transistor Q3 constituting the current limiting unit, in the range from the ground potential to the threshold voltage of the NMOS transistor, The current of the current limiting unit can be arbitrarily adjusted in the range of picoamperes to submicroamperes. In the present embodiment, by setting the current of the current limiting unit to about sub-microamperes, the discharge time of the charge storage unit C1 can be shortened compared to the second embodiment, and the voltage of the input terminal IN Since the time at which the voltage at the output terminal OUT transitions from High to Low can be shortened in response to transition from Low to High, threshold processing can be performed at high speed.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of a threshold circuit according to the fourth embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the charge storage unit C1, the first terminal is connected to the drain terminal and the output terminal OUT of the first PMOS transistor Q1, and the second terminal is The current limiter I2 is connected to the ground terminal and the current control terminal is connected to the drain terminal of the first PMOS transistor Q1 and the output terminal OUT.

  In the present embodiment, the current of the current limiting unit I2 is controlled by the voltage of the output terminal OUT, and the current of the current limiting unit I2 increases as the voltage of the output terminal OUT decreases. And different. In the present embodiment, until the voltage at the input terminal IN rises and the first PMOS transistor Q1 approaches the off state, the charge storage unit C1 is discharged as small as a sub-microampere equivalent to the first embodiment. The first implementation is performed by making the current of the current limiter I2 larger than the sub-microampere when the voltage at the input terminal IN is sufficiently high and the first PMOS transistor Q1 is turned off. The operation of the threshold processing can be speeded up while maintaining the effect of reducing the through current of the form.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of a threshold circuit according to the fifth embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the charge storage unit C1, the drain terminal is connected to the drain terminal and the output terminal OUT of the first PMOS transistor Q1, and the source terminal is grounded. 1 NMOS transistor Q4, its gate terminal is connected to the drain terminal and output terminal OUT of the first PMOS transistor Q1, its source terminal is connected to the power supply potential VDD, and its drain terminal is connected to the gate terminal of the first NMOS transistor Q4. The connected second PMOS transistor Q5, the first terminal is connected to the connection point between the gate terminal of the first NMOS transistor Q4 and the drain terminal of the second PMOS transistor Q5, and the second terminal is grounded. The switch SW1 has a control terminal connected to the initialization terminal RST.

  In the present embodiment, the current limiting unit I2 of the fourth embodiment is composed of a first NMOS transistor Q4, a second PMOS transistor Q5, and a switch SW1, and the gate terminal of the first NMOS transistor Q4 The voltage is controlled by the switch SW1 and the second PMOS transistor Q5.

  The operation of this embodiment will be described. When the sensor node is initialized, the switch SW1 is turned on by an initialization signal given from the control circuit (not shown) to the initialization terminal RST, the gate terminal of the first NMOS transistor Q4 becomes the ground potential, and the first NMOS transistor Q4 is turned off. At this time, the current of the current limiting unit is set to the leakage current of the first NMOS transistor Q4. Thereafter, the control circuit turns off the switch SW1, and the threshold circuit waits for an input signal.

  As described in the first embodiment, when the voltage at the input terminal IN rises from Low to High, the first PMOS transistor Q1 approaches the off state, and the voltage at the output terminal OUT falls from High to Low. As the voltage at the output terminal OUT decreases, the second PMOS transistor Q5 approaches the on state, and the gate voltage of the first NMOS transistor Q4 increases. Thereby, since the current of the first NMOS transistor Q4 increases, the discharge time of the charge in the charge storage unit C1 can be shortened, and the time for the voltage of the output terminal OUT to transition from High to Low can be shortened. it can. That is, in the present embodiment, it is possible to speed up the threshold processing while maintaining the effect of reducing the through current of the second embodiment.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a threshold circuit according to the sixth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, and a first terminal connected to the first NMOS transistor Q4. The voltage control voltage source V1 is connected to a connection point between the gate terminal of the second PMOS transistor Q5 and the drain terminal of the second PMOS transistor Q5, the second terminal is grounded, and the control terminal is connected to the output terminal OUT.

  In the present embodiment, the current limiting unit I2 of the fourth embodiment is composed of a first NMOS transistor Q4, a second PMOS transistor Q5, and a voltage control voltage source V1, and the first NMOS transistor Q4 The voltage of the gate terminal is controlled by the voltage control voltage source V1 and the second PMOS transistor Q5. The present embodiment is different from the fifth embodiment in that the voltage at the gate terminal of the first NMOS transistor Q4 is controlled by the voltage control voltage source V1.

  As described in the first embodiment, when the voltage at the input terminal IN is Low, the first PMOS transistor Q1 is turned on, and the voltage at the output terminal OUT is High. At this time, the voltage control voltage source V1 sets the gate terminal of the first NMOS transistor Q4 to the ground potential. Thereby, the current of the current limiting unit is set to the leakage current of the first NMOS transistor Q4.

  Next, when the voltage at the input terminal IN rises from Low to High, the first PMOS transistor Q1 approaches an off state, and the voltage at the output terminal OUT falls from High to Low. As the voltage at the output terminal OUT decreases, the second PMOS transistor Q5 approaches the on state, and the gate voltage of the first NMOS transistor Q4 increases. At this time, the voltage control voltage source V1 performs control so that the gate voltage of the first NMOS transistor Q4 rises with a voltage change amount smaller than the voltage change amount from High to Low of the output terminal OUT.

  As described above, in the present embodiment, when the voltage at the output terminal OUT rises, the amount of voltage change at which the gate terminal of the first NMOS transistor Q4 rises from the ground potential is compared with that in the fifth embodiment. It can be kept small. As a result, it is possible to suppress a decrease in the logic threshold value of the threshold circuit as compared with the fifth embodiment. As a result, in this embodiment, even when the voltage range of the input terminal IN, that is, the output voltage range of the sensor circuit 52 shown in FIG.

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a threshold circuit according to the seventh embodiment of the present invention.
The threshold circuit according to the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a switch SW1, and a first terminal serving as an output terminal. The first capacitor C2 is connected to OUT, the second terminal is connected to the gate terminal of the first NMOS transistor Q4, and the first terminal is connected to the gate terminal of the first NMOS transistor Q4. And a second capacitive element C3 having two terminals grounded.

In the present embodiment, the voltage control voltage source V1 of the sixth embodiment is configured by a switch SW1, a first capacitive element C2, and a second capacitive element C3.
In this embodiment, as described in the fifth embodiment, after the switch SW1 is turned on at the time of initialization of the sensor node, the switch SW1 is turned off. After the sensor node is initialized, when the voltage at the input terminal IN increases from Low to High, the voltage at the output terminal OUT decreases from High to Low. As the voltage at the output terminal OUT decreases, the second PMOS transistor Q5 approaches the on state, and the gate voltage of the first NMOS transistor Q4 increases. At this time, the voltage of the gate terminal of the first NMOS transistor Q4 is controlled so that the potential between the output terminal OUT and the ground is divided by the capacitors C2 and C3.

  In this way, in this embodiment, when the voltage at the output terminal OUT rises, the amount of voltage change at which the gate terminal of the first NMOS transistor Q4 rises from the ground potential can be suppressed to a small level. Similar effects can be obtained.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a threshold circuit according to the eighth embodiment of the present invention.
The threshold circuit according to the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a gate terminal connected to the output terminal OUT, and a drain. The second NMOS transistor Q6 has a terminal connected to a connection point between the gate terminal of the first NMOS transistor Q4 and the drain terminal of the second PMOS transistor Q5, and a source terminal grounded.

In the present embodiment, the voltage control voltage source V1 of the sixth embodiment is configured by a second NMOS transistor Q6.
As described in the first embodiment, when the voltage at the input terminal IN is Low, the voltage at the output terminal OUT is High, so that the second NMOS transistor Q6 is turned on, and the first NMOS transistor Q4 The gate terminal is at ground potential.

  Next, when the voltage at the input terminal IN increases from Low to High, the voltage at the output terminal OUT decreases from High to Low, and the gate voltage of the first NMOS transistor Q4 increases as the voltage at the output terminal OUT decreases. . At this time, the second NMOS transistor Q6 approaches an off state as the voltage at the output terminal OUT decreases, but functions to suppress a voltage increase at the gate terminal of the first NMOS transistor Q4 until the second NMOS transistor Q6 is completely off. To do.

  In the present embodiment, the second NMOS transistor Q6 can suppress a change in voltage at the gate terminal of the first NMOS transistor Q4, so that the same effect as in the sixth embodiment can be obtained.

[Ninth Embodiment]
Next, a ninth embodiment of the present invention will be described. FIG. 9 is a circuit diagram showing a configuration of a threshold circuit according to the ninth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, and a drain terminal that is the gate of the first NMOS transistor Q4. A second NMOS transistor Q6 connected to a connection point between the terminal and the drain terminal of the second PMOS transistor Q5, the source terminal grounded, a gate terminal and a drain terminal connected to the output terminal OUT, and a source terminal connected to the first terminal A third NMOS transistor Q7 connected to the gate terminal of the second NMOS transistor Q6, a first terminal connected to the gate terminal of the second NMOS transistor Q6, a second terminal grounded, and a control terminal initially And a switch SW2 connected to the conversion terminal RST.

This embodiment differs from the eighth embodiment in that a diode-connected third NMOS transistor Q7 is inserted between the gate terminal of the second NMOS transistor Q6 and the output terminal OUT.
In the present embodiment, as in the fifth embodiment, the switch SW2 is turned on by an initialization signal given to the initialization terminal RST from a control circuit (not shown) at the time of initialization of the sensor node, and then the switch SW2 is turned off. Put it in a state.

  As described in the eighth embodiment, when the voltage at the input terminal IN increases from Low to High, the voltage at the output terminal OUT decreases from High to Low, and as the voltage at the output terminal OUT decreases, the first NMOS The gate voltage of transistor Q4 increases. In the present embodiment, a voltage that is smaller than the voltage of the output terminal OUT by the threshold voltage of the third NMOS transistor Q7 is used as the gate voltage of the second NMOS transistor Q6. Therefore, as compared with the eighth embodiment. The gate voltage of the first NMOS transistor Q4 can be increased. As a result, in this embodiment, even when the discharge time of the charge from the charge storage unit C1 is long, the discharge time can be shortened compared to the eighth embodiment, and the voltage of the output terminal OUT is changed from High. The transition time to Low can be shortened.

[Tenth embodiment]
Next, a tenth embodiment of the present invention will be described. FIG. 10 is a circuit diagram showing a configuration of a threshold circuit according to the tenth embodiment of the present invention.
The threshold circuit according to the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, and a source terminal. The third NMOS transistor Q7 connected to the gate terminal of the second NMOS transistor Q6, the gate terminal and the drain terminal are connected to the output terminal OUT, and the source terminal is connected to the gate terminal and the drain terminal of the third NMOS transistor Q7. A fourth NMOS transistor Q8 and a switch SW2 are connected.

In the present embodiment, a fourth diode-connected NMOS transistor Q8 is inserted between the gate terminal of the second NMOS transistor Q6 and the output terminal OUT in addition to the diode-connected third NMOS transistor Q7. This differs from the ninth embodiment.
In the present embodiment, the voltage obtained by reducing the voltage of the output terminal OUT by the sum of the threshold voltages of the third and fourth NMOS transistors Q7 and Q8 is used as the gate voltage of the second NMOS transistor Q6. Compared to the ninth embodiment, the gate voltage of the first NMOS transistor Q4 can be increased. As a result, in the present embodiment, even when the discharge time of the charge from the charge storage unit C1 is long, the discharge time can be shortened compared to the ninth embodiment, and the voltage of the output terminal OUT is changed from High. The transition time to Low can be shortened.

[Eleventh embodiment]
Next, an eleventh embodiment of the present invention will be described. FIG. 11 is a circuit diagram showing a configuration of a threshold circuit according to the eleventh embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, NMOS transistor Q7, fourth NMOS transistor Q9 whose gate terminal is connected to output terminal OUT, and whose source terminal is connected to the gate terminal and drain terminal of third NMOS transistor Q7, switch SW2, and first terminal Is connected to the power supply potential VDD, the second terminal is connected to the drain terminal of the fourth NMOS transistor Q9, and the switch SW3 is connected to the control terminal RSTN.

This embodiment is different from the tenth embodiment in that the drain terminal of the fourth NMOS transistor Q9 is connected to the power supply potential VDD via the second switch SW3.
In the present embodiment, the switch SW3 is turned on at the same time as the switch SW2 is turned on by an initialization signal supplied from the control circuit (not shown) to the initialization terminal RST when the sensor node is initialized. Subsequently, after the potential of the input terminal IN becomes a steady state, the control circuit turns off the switch SW2, and simultaneously turns on the switch SW3 by giving a steadying signal to the steadying terminal RSTN, thereby causing the threshold circuit Is in a state waiting for an input signal.

  With the configuration as described above, in this embodiment, the parasitic capacitance of the drain terminal of the fourth NMOS transistor Q9 can be separated from the output terminal OUT, so that the charge discharge time of the charge storage unit C1 is shortened. The time for the voltage of the output terminal OUT to transition from High to Low can be shortened.

[Twelfth embodiment]
Next, a twelfth embodiment of the present invention will be described. FIG. 12 is a circuit diagram showing a configuration of a threshold circuit according to the twelfth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, The NMOS transistor Q7, the fourth NMOS transistor Q9, the gate terminal is connected to the connection point between the gate terminal of the first NMOS transistor Q4 and the drain terminal of the second PMOS transistor Q5, and the source terminal is set to the power supply potential VDD. A third PMOS transistor Q10 is connected and has a drain terminal connected to the source terminal of the first PMOS transistor Q1 and switches SW2 and SW3.

  In the present embodiment, a third PMOS transistor Q10 is inserted between the source terminal of the first PMOS transistor Q1 and the power supply potential VDD, and the gate terminal of the third PMOS transistor Q10 is connected to the first NMOS transistor Q4. The point of controlling by the voltage of the gate terminal is different from the eleventh embodiment.

  In the present embodiment, when the voltage at the input terminal IN rises from Low, it is held near the logic threshold value of the threshold circuit, and the first PMOS transistor Q1 becomes incompletely off and the charge in the charge storage portion C1 is reduced. Even when the discharge does not proceed, the third PMOS transistor Q10 is turned off by a slight voltage drop at the output terminal OUT, and the same state as that when the first PMOS transistor Q1 is turned off can be obtained. The voltage of the output terminal OUT can be quickly changed from High to Low by proceeding with the discharge of the electric charge, and the malfunction of the threshold processing can be prevented.

[Thirteenth embodiment]
Next, a thirteenth embodiment of the present invention will be described. FIG. 13 is a circuit diagram showing a configuration of a threshold circuit according to the thirteenth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, The NMOS transistor Q7, the fourth NMOS transistor Q9, the third PMOS transistor Q10, the gate terminal is connected to the output terminal OUT, the drain terminal is connected to the source terminal of the second NMOS transistor Q6, and the source terminal is It is composed of a grounded fifth NMOS transistor Q11 and switches SW1, SW2 and SW3.

  In the present embodiment, a fifth NMOS transistor Q11 is inserted between the source terminal of the second NMOS transistor Q6 that controls the voltage of the gate terminal of the first NMOS transistor Q4 and the ground potential, and a fifth NMOS transistor is inserted. The point that the voltage of the gate terminal of the transistor Q11 is controlled by the voltage of the output terminal OUT, and the point that the switch SW1 for initializing the gate terminal of the first NMOS transistor Q4 is provided as in the fifth embodiment. Different from the twelve embodiments.

  In the present embodiment, the fifth NMOS transistor Q11 is turned off when the voltage at the output terminal OUT changes from High to Low in response to the voltage at the input terminal IN changing from Low to High. The current flowing through the second NMOS transistor Q6 and the second PMOS transistor Q5 after the processing operation can be suppressed, and the power consumption of the threshold circuit can be reduced.

[Fourteenth embodiment]
Next, a fourteenth embodiment of the present invention will be described. FIG. 14 is a circuit diagram showing a configuration of a threshold circuit according to a fourteenth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, The NMOS transistor Q7, the fourth NMOS transistor Q9, the third PMOS transistor Q10, the fifth NMOS transistor Q11, and the transfer inserted between the drain terminal and the output terminal OUT of the first NMOS transistor Q4. It comprises a gate T1 and switches SW1, SW2, SW3.

  This embodiment is different from the thirteenth embodiment in that an on-state transfer gate T1 is inserted between the drain terminal of the first NMOS transistor Q4 and the output terminal OUT. That is, the transfer gate T1 includes the NMOS transistor Q12 and the PMOS transistor Q13, the gate terminal of the NMOS transistor Q12 is connected to the power supply potential VDD, and the gate terminal of the PMOS transistor Q13 is grounded. The drain terminal of the NMOS transistor Q12 and the source terminal of the PMOS transistor Q13 are connected to the output terminal OUT, and the source terminal of the NMOS transistor Q12 and the drain terminal of the PMOS transistor Q13 are connected to the drain terminal of the first NMOS transistor Q4. Has been. The transfer gate T1 is always on while the power supply potential VDD is supplied.

  When the parasitic capacitance of the drain terminal of the first NMOS transistor Q4 is large, the discharge time of the charge in the charge storage unit C1 becomes long. In this embodiment, the drain terminal and the output terminal OUT of the first NMOS transistor Q4 are used. Since the transfer gate T1 is inserted between and the parasitic capacitance of the drain terminal of the first NMOS transistor Q4 is disconnected from the charge storage unit C1 connected to the output terminal OUT, the charge of the charge storage unit C1 , And the time for the voltage at the output terminal OUT to transition from High to Low can be shortened.

[Fifteenth embodiment]
Next, a fifteenth embodiment of the present invention is described. FIG. 15 is a circuit diagram showing a configuration of a threshold circuit according to the fifteenth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, The NMOS transistor Q7, the fourth NMOS transistor Q9, the third PMOS transistor Q10, the fifth NMOS transistor Q11, the transfer gate T1, the switches SW1, SW2, SW3, and the first terminal are connected to the power supply potential VDD. , A switch SW4 having a second terminal connected to the output terminal OUT and a control terminal connected to the initialization terminal RST.

This embodiment is different from the fourteenth embodiment in that an output switch OUT is provided with a switch SW4 for initialization.
In the first to fourteenth embodiments, when the voltage of the input terminal IN is not completely low at the time of initialization of the sensor node, the first potential is the intermediate potential between the power supply potential VDD and the ground potential. The PMOS transistor Q1 may be incompletely turned on, and the voltage at the output terminal OUT may not become high.

  On the other hand, in the present embodiment, the switch SW4 is turned on by an initialization signal given from the control circuit (not shown) to the initialization terminal RST at the time of initialization, so that the voltage at the input terminal IN becomes completely low. Even if not, the voltage of the output terminal OUT can be made high, and the output terminal OUT can be initialized. After that, the control circuit turns off the switches SW1, SW2 and SW4, and at the same time turns on the switch SW3 to put the threshold circuit in a state waiting for an input signal.

[Sixteenth embodiment]
Next, a sixteenth embodiment of the present invention will be described. FIG. 16 is a circuit diagram showing a configuration of a threshold circuit according to the sixteenth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a charge storage unit C1, a first NMOS transistor Q4, a second PMOS transistor Q5, a second NMOS transistor Q6, NMOS transistor Q7, fourth NMOS transistor Q9, third PMOS transistor Q10, fifth NMOS transistor Q11, transfer gate T1, switches SW1, SW2, SW3, SW4, charge storage section C1 and output The buffer circuit BUFF1 is inserted between the terminal OUT.

This embodiment is different from the fifteenth embodiment in that the output terminal OUT includes a buffer circuit BUFF1 whose input gate capacitance is a gate capacitance value (100 fF or less) of a transistor having a minimum size.
In the present embodiment, even when the load capacitance of the output terminal OUT is large, by using the buffer circuit BUFF1, the charge discharge time of the charge storage unit C1 can be shortened, and the voltage of the output terminal OUT is changed from High to Low. It is possible to shorten the transition time to.

  In the first to sixteenth embodiments, the example in which the threshold circuit is applied to the sensor node has been described. However, the present invention is not limited to this, and the present invention can also be applied to other than the sensor node. .

  The present invention can be applied to a threshold circuit used for a sensor node or the like.

  Q1, Q5, Q10 ... PMOS transistors, Q2, Q3, Q4, Q6, Q7, Q8, Q9, Q11 ... NMOS transistors, I1, I2 ... current limiting unit, C1 ... charge storage unit, C2, C3 ... capacitive element, SW1 , SW2, SW3, SW4, switch, V1, voltage control voltage source, T1, transfer gate, BUFF1, buffer circuit, IN, input terminal, OUT, output terminal, RST, initialization terminal, RSTN, steady terminal.

Claims (13)

The gate terminal is connected to the input terminal, the source terminal is connected to the first common potential, the drain terminal is connected to the output terminal, and is turned on when the voltage of the input terminal is lower than a predetermined logic threshold value. A first first polarity transistor that is turned off when high;
A first terminal is connected to a drain terminal and the output terminal of the first first polarity transistor, a second terminal is connected to a second common potential, and the first terminal is connected to the second terminal. A current limiting unit for limiting the flowing current;
A charge storage unit that is connected to a drain terminal and the output terminal of the first first polarity transistor, and stores charge by a charging current when the first first polarity transistor is in an ON state;
The current value of the current limiting unit is set to sub-microamperes or less ;
The threshold value circuit , wherein the current limiter is controlled based on a voltage of the output terminal and increases a current value from a picoampere level to a microampere level according to a voltage change of the output terminal . The threshold circuit according to claim 1 , wherein
The current limiting unit is
A first second polarity transistor having a drain terminal connected to the drain terminal and the output terminal of the first first polarity transistor, and a source terminal connected to the second common potential;
A gate terminal is connected to the drain terminal and the output terminal of the first first polarity transistor, a source terminal is connected to the first common potential, and a drain terminal is connected to the gate terminal of the first second polarity transistor. A threshold circuit comprising: a connected second first polarity transistor. The threshold circuit according to claim 2 , wherein
The current limiting unit includes a voltage control voltage source that controls the voltage of the gate terminal of the first second polarity transistor based on the voltage of the output terminal,
The threshold voltage circuit, wherein the voltage control voltage source controls the voltage of the gate terminal of the first second polarity transistor to change with a voltage change amount smaller than the voltage change amount of the output terminal. The threshold circuit according to claim 3 , wherein
The voltage control voltage source is:
A first capacitive element having a first terminal connected to the output terminal and a second terminal connected to a gate terminal of the first second polarity transistor;
A first terminal is connected to a gate terminal of the first second polarity transistor, and a second terminal is constituted by a second capacitor element connected to the second common potential. Threshold circuit. The threshold circuit according to claim 3 , wherein
The voltage control voltage source has a gate terminal connected to the output terminal, and a drain terminal connected to a connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor. A threshold circuit comprising a second polarity transistor having a source terminal connected to the second common potential. The threshold circuit according to claim 3 , wherein
The voltage control voltage source is:
A drain terminal is connected to a connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, and a source terminal is connected to the second common potential. A second polarity transistor;
One or more third second polarity transistors having a gate terminal and a drain terminal connected to the output terminal and a source terminal connected to a gate terminal of the second second polarity transistor, Threshold circuit. The threshold circuit according to claim 3 , wherein
The voltage control voltage source is:
A drain terminal is connected to a connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, and a source terminal is connected to the second common potential. A second polarity transistor;
A third second polarity transistor having a source terminal connected to the gate terminal of the second second polarity transistor;
A fourth second polarity in which a gate terminal is connected to the output terminal, a drain terminal is connected to the first common potential, and a source terminal is connected to a gate terminal and a drain terminal of the third second polarity transistor. A threshold circuit comprising a transistor. The threshold circuit according to any one of claims 2 to 7 ,
Further, the gate terminal is connected to a connection point between the gate terminal of the first second polarity transistor and the drain terminal of the second first polarity transistor, the source terminal is connected to the first common potential, and the drain A threshold circuit comprising: a third first polarity transistor having a terminal connected to a source terminal of the first first polarity transistor. The threshold circuit according to any one of claims 5 to 8 ,
The voltage control voltage source is further inserted between a source terminal of the second second polarity transistor and the second common potential, a gate terminal connected to the output terminal, and a drain terminal connected to the second terminal. A threshold circuit comprising: a fifth second polarity transistor connected to a source terminal of the second polarity transistor of which the source terminal is connected to the second common potential. The threshold circuit according to claim 2 , wherein
The threshold circuit further comprises an initialization switch for setting the voltage of the gate terminal of the first second polarity transistor to the second common potential at the time of initialization. The threshold circuit according to claim 6 , wherein
The threshold circuit further comprises an initialization switch that sets the voltage of the gate terminal of the second second polarity transistor to the second common potential at the time of initialization. The threshold circuit according to claim 7 ,
The threshold circuit further comprises a switch inserted between the drain terminal of the fourth second polarity transistor and the first common potential and turned off at initialization and turned on at steady state. The gate terminal is connected to the input terminal, the source terminal is connected to the first common potential, the drain terminal is connected to the output terminal, and is turned on when the voltage of the input terminal is lower than a predetermined logic threshold value. A first first polarity transistor that is turned off when high;
A first terminal is connected to a drain terminal and the output terminal of the first first polarity transistor, a second terminal is connected to a second common potential, and the first terminal is connected to the second terminal. A current limiting unit for limiting the flowing current;
A charge storage unit connected to a drain terminal of the first first polarity transistor and the output terminal, and for storing charge by a charging current when the first first polarity transistor is in an on state;
An on-state transfer gate inserted between the current limiter and the output terminal;
The threshold value circuit, wherein a current value of the current limiting unit is set to be equal to or less than sub-microamperes .

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