JP4851560B2 - Threshold circuit - Google Patents

Description

  The present invention relates to a threshold circuit used for a sensor node or the like, and more particularly to a technique for reducing the power consumption of the threshold circuit.

  A configuration of a conventional sensor node system in which a threshold circuit is used is shown in FIG. 9 (see, for example, Patent Document 1). The sensor node system includes a sensor node chip 50 and a receiving device 60. The sensor node chip 50 performs threshold processing on a sensor element 51 that detects a physical quantity to be measured, a sensor circuit 52 that amplifies and outputs a signal detected by the sensor element 51, and an output signal of the sensor circuit 52, for example. Output from the threshold circuit 53 output as detection data, a CPU 54 that performs processing for compressing detection data, processing for adding chip identification information to detection data, and the like, a memory 55 that stores a program for the CPU 54, and the CPU 54. A wireless unit 56 that wirelessly transmits detection data to the receiving device 60 and a power source 57 that supplies power to each component of the sensor node chip 50 are provided.

  A circuit diagram of a conventional threshold circuit is shown in FIG. 10 (see, for example, Non-Patent Document 1). In this threshold circuit, the first and second PMOS transistors Q100 and Q101 and the first NMOS transistor Q102 are connected in series between a first common potential VDD (power supply potential) and a second common potential (ground potential). The gate terminals of the transistors Q100, Q101, Q102 are made common and connected to the input terminal IN, and the connection point between the drain terminal of the second PMOS transistor Q101 and the drain terminal of the first NMOS transistor Q102 is It is connected to the output terminal OUT. The source terminal of the third PMOS transistor Q103 is connected to the connection point between the drain terminal of the first PMOS transistor Q100 and the source terminal of the second PMOS transistor Q101, and the gate terminal of the third PMOS transistor Q103 is output. Connected to the terminal OUT, the drain terminal of the third PMOS transistor Q103 is connected to the ground potential.

The operation of the conventional threshold circuit shown in FIG. 10 will be described using the input / output characteristics shown in FIG. In FIG. 11, the horizontal axis represents the voltage V (IN) of the input terminal IN, and the vertical axis represents the voltage V (OUT) of the output terminal OUT.
First, the case where the voltage V (IN) of the input terminal IN transits from Low to High will be described. When the voltage V (IN) at the input terminal IN is Low, the first NMOS transistor Q102 is in the off state, the first and second PMOS transistors Q100 and Q101 are in the on state, and the voltage V (OUT) at the output terminal OUT. Becomes High. At this time, the third PMOS transistor Q103 is in an off state.

  When the voltage V (IN) at the input terminal IN increases, the first NMOS transistor Q102 is turned on, and when the voltage V (IN) at the input terminal IN reaches the first threshold voltage Vthh, the voltage V at the output terminal OUT. (OUT) becomes Low. The first threshold voltage Vthh is determined by the ratio between the driving power of the first and second PMOS transistors Q100 and Q101 and the driving power of the first NMOS transistor Q102.

  Next, a case where the voltage V (IN) of the input terminal IN transitions from High to Low will be described. When the voltage V (IN) of the input terminal IN is High, the first and second PMOS transistors Q100 and Q101 are in an off state, the first NMOS transistor Q102 is in an on state, and the third PMOS transistor Q103 is in an on state. It is. Therefore, the connection point between the drain terminal of the first PMOS transistor Q100 and the source terminal of the second PMOS transistor Q101 is the ground potential.

  When the voltage V (IN) at the input terminal IN decreases and the first and second PMOS transistors Q100 and Q101 are turned on and the first NMOS transistor Q102 is turned off, the voltage V (OUT ) Rises, and the third PMOS transistor Q103 approaches the OFF state. When the voltage V (IN) at the input terminal IN reaches the second threshold voltage Vthl, the voltage V (OUT) at the output terminal OUT becomes High. When the voltage V (OUT) at the output terminal OUT is Low, the third PMOS transistor Q103 is in the on state, and the first and second PMOS transistors Q100 and Q101 increase the voltage V (OUT) at the output terminal OUT. Therefore, the second threshold voltage Vthl is smaller than the first threshold voltage Vthh.

  As described above, in the threshold circuit shown in FIG. 10, the threshold voltage Vthh when the voltage V (IN) of the input terminal IN transits from Low to High and the voltage V (IN) of the input terminal IN changes from High to Low. Since the threshold voltage Vthl at the time of transition is different, even if the voltage V (IN) of the input terminal IN fluctuates in the vicinity of the threshold voltage, noise called a glitch is not generated in the output signal.

Japanese Patent Laid-Open No. 2004-024551

Sung-Mo Kang, Yusuf Leblebici, “Cmos Digital Integrated Circuits: Analysis and Design”, 2nd edition, William C Brown Pub, September 1998, p. 341-345

  When the threshold circuit shown in FIG. 10 is applied to the sensor node chip shown in FIG. 9, when the output of the sensor circuit gradually transitions from Low to High, a large through current flows through the transistors Q100 to Q102 of the threshold circuit, In particular, when the output of the sensor circuit holds an intermediate potential between Low and High, a large current continues to flow during that period. Since a battery is generally used as a power supply for the sensor node chip, there is a problem that if a large through current continues to flow through the threshold circuit, the operation time of the sensor node chip operating with a limited energy source is shortened. It was.

  The present invention has been made to solve the above-described problems, and an object thereof is to reduce the power consumption of a threshold circuit.

The threshold circuit of the present invention (first and fourth embodiments) includes a first first polarity transistor having a gate terminal connected to an input terminal and a source terminal connected to a first common potential, and a gate terminal. Is connected to the input terminal, the source terminal is connected to the drain terminal of the first first polarity transistor, the drain terminal is connected to the output terminal, and the gate terminal is the output terminal The source terminal is connected to the connection point between the drain terminal of the first first polarity transistor and the source terminal of the second first polarity transistor, and the drain terminal is connected to the second common potential. A third first polarity transistor, a first terminal connected to the output terminal, a second terminal connected to the second common potential, and a current flowing from the first terminal to the second terminal The A current limiting unit for limiting, and the current limiting unit is controlled based on a voltage of the input terminal, and increases a current value from a picoampere level to a microampere level according to a voltage change of the input terminal. It is a feature .

In one configuration example (fifth embodiment) of the threshold circuit of the present invention, the current limiting unit has a drain terminal connected to the output terminal and a source terminal connected to the second common potential. One or more second second polarity transistors having a first second polarity transistor, a gate terminal and a drain terminal connected to the input terminal, and a source terminal connected to the gate terminal of the first second polarity transistor It is comprised from these.
In one configuration example (sixth embodiment) of the threshold circuit of the present invention, the current limiting unit has a drain terminal connected to the output terminal and a source terminal connected to the second common potential. A first second polarity transistor, a gate terminal connected to the input terminal, a drain terminal connected to the first common potential, and a source terminal connected to the gate terminal of the first second polarity transistor; And a second second polarity transistor.
In one configuration example (seventh embodiment) of the threshold circuit according to the present invention, the current limiting unit further includes a source terminal of the second second polarity transistor and a first second polarity transistor. One or more inserted between the gate terminal, the gate terminal and the drain terminal are connected to the source terminal of the second second polarity transistor, and the source terminal is connected to the gate terminal of the first second polarity transistor The third second polarity transistor is provided.
Further, in one configuration example (eighth embodiment) of the threshold circuit of the present invention, initialization is performed such that the voltage of the gate terminal of the first second polarity transistor is set to the second common potential during initialization. A switch is provided.

  According to the present invention, a first first polarity transistor having a gate terminal connected to an input terminal, a source terminal connected to a first common potential, a gate terminal connected to the input terminal, and a source terminal connected to the first terminal. The first polarity transistor is connected to the drain terminal of the first polarity transistor, the drain terminal is connected to the output terminal, the gate terminal is connected to the output terminal, and the source terminal is connected to the first polarity transistor. A third first polarity transistor connected to the connection point between the drain terminal and the source terminal of the second first polarity transistor, the drain terminal connected to the second common potential, and the first terminal as the output terminal And a second current terminal connected to the second common potential, and a current limiter configured to limit a current flowing from the first terminal to the second terminal. The through current flowing through the first and second first polarity transistors and the current limiting unit is reduced to the current set by the current limiting unit even if the voltage is held at an intermediate potential between the first and second common potentials. And the power consumption of the threshold circuit can be reduced. As a result, if the threshold circuit of the present invention is used, the power consumption of the sensor node chip can be reduced to the nanowatt level. Therefore, it is not necessary to increase the power generation amount of the power supply unit of the sensor node chip, and the volume of the power generation mechanism can be reduced. Therefore, downsizing of the sensor node chip is achieved, and the sensor node chip can be embedded also in an object or a human part that could not be embedded due to size restrictions until now. Furthermore, the range of ubiquitous network services using the sensor node system can be expanded, and services with improved user convenience can be provided, which is highly effective.

  In the present invention, the current limiter is connected to the second common potential or a fixed potential set in the range from the second common potential to the threshold voltage of the second polarity transistor, and the drain terminal outputs When the gate terminal of the first second polarity transistor is connected to the second common potential by constituting the first second polarity transistor connected to the terminal and having the source terminal connected to the second common potential. In the case where the through current of the threshold circuit can be reduced to about picoamperes, and the potential of the gate terminal of the first second polarity transistor is made larger than the second common potential in the range up to the threshold voltage of the second polarity transistor. The threshold processing can be speeded up.

  In the present invention, the current limiter is controlled based on the voltage at the input terminal, and the current value is increased according to the voltage change at the input terminal, thereby maintaining the effect of reducing the through current of the threshold circuit. The threshold processing can be speeded up.

  In the present invention, the current limiting unit includes a first second polarity transistor having a drain terminal connected to the output terminal, a source terminal connected to the second common potential, and a gate terminal connected to the input terminal. Since the drain terminal is connected to the first common potential and the source terminal is formed from the second second polarity transistor connected to the gate terminal of the first second polarity transistor, the input capacitance of the threshold circuit is reduced. can do.

  In the present invention, the current limiting unit is further inserted between the source terminal of the second second polarity transistor and the gate terminal of the first second polarity transistor, and the gate terminal and the drain terminal are the second terminal. By including one or more third second polarity transistors connected to the source terminal of the second polarity transistor, the source terminal being connected to the gate terminal of the first second polarity transistor, the first second polarity transistor Current flowing in the capacitor can be reduced, and the power consumption of the threshold circuit can be reduced.

  In the present invention, the current flowing through the first second polarity transistor is increased by providing the initialization switch that sets the voltage of the gate terminal of the first second polarity transistor to the second common potential at the time of initialization. This can be prevented, and an increase in power consumption of the threshold circuit can be prevented.

It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the threshold value circuit which concerns on the 8th Embodiment of this invention. It is a block diagram which shows the structure of the conventional sensor node system. It is a circuit diagram which shows the structure of the conventional threshold circuit. It is a figure which shows the input-output characteristic of the threshold circuit of FIG.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a threshold circuit according to the first embodiment of the present invention.
In the threshold circuit of this embodiment, the first PMOS transistor Q1 whose gate terminal is connected to the input terminal IN, the source terminal is connected to the power supply potential VDD, the gate terminal is connected to the input terminal IN, and the source terminal is The second PMOS transistor Q2 is connected to the drain terminal of the first PMOS transistor Q1, the drain terminal is connected to the output terminal OUT, the gate terminal is connected to the output terminal OUT, and the source terminal is the first PMOS transistor Q1. A third PMOS transistor Q3 having a drain terminal connected to a ground potential and a first terminal connected to a connection point between the drain terminal of the second PMOS transistor Q2 and the source terminal of the second PMOS transistor Q2. The current control is connected to the drain terminal and the output terminal OUT, and the second terminal is connected to the ground potential. Consisting of part I1 Metropolitan.

This embodiment differs from the conventional threshold circuit in that it includes a current limiting unit I1 instead of the NMOS transistor Q102 shown in FIG.
The operation of the threshold circuit of this embodiment will be described. First, the case where the voltage of the input terminal IN transitions from Low to High will be described. When the threshold circuit of this embodiment is applied to the sensor node chip 50 shown in FIG. 9, the voltage of the input terminal IN becomes Low when the sensor node chip 50 is initialized. When the voltage at the input terminal IN is Low, the first and second PMOS transistors Q1 and Q2 are turned on, and the voltage at the output terminal OUT is High. At this time, a current flows through the current limiting unit I1, but this current is extremely small with respect to a current that can be flowed with the combined driving force of the first and second PMOS transistors Q1 and Q2, and therefore the output terminal OUT Is never low.

  When the output voltage of the sensor circuit 52 of the sensor node chip 50 increases from Low and the voltage of the input terminal IN rises, the first and second PMOS transistors Q1 and Q2 are turned off, and the first and second PMOS transistors When the current flowing through Q1 and Q2 becomes smaller than the current of the current limiting unit I1, the voltage at the output terminal OUT starts to drop, and the voltage at the output terminal OUT becomes Low.

  Next, a case where the voltage at the input terminal IN transitions from High to Low will be described. When the voltage at the input terminal IN is High, the first and second PMOS transistors Q1 and Q2 are in an off state, and the third PMOS transistor Q3 is in an on state. Therefore, the connection point between the drain terminal of the first PMOS transistor Q1 and the source terminal of the second PMOS transistor Q2 is the ground potential.

  When the voltage at the input terminal IN decreases and the first and second PMOS transistors Q1 and Q2 are turned on, the voltage at the output terminal OUT rises and the third PMOS transistor Q3 approaches the off state. When the voltage at the input terminal IN reaches the second threshold voltage Vthl, the voltage at the output terminal OUT becomes High. When the voltage of the output terminal OUT is low, the third PMOS transistor Q3 is in the on state, and the first and second PMOS transistors Q1 and Q2 are prevented from raising the voltage of the output terminal OUT. The second threshold voltage Vthl is smaller than the first threshold voltage Vthh when the IN voltage V transitions from Low to High.

  As described above, in the present embodiment, the through current flowing through the first and second PMOS transistors Q1 and Q2 can be limited by providing the current limiting unit I1. In the conventional threshold circuit shown in FIG. 10, a large through current of several tens of microamperes flows through the transistors Q100 to Q102 when the voltage at the input terminal IN is held at an intermediate potential between the power supply potential VDD and the ground potential. End up.

  On the other hand, in the present embodiment, when the voltage at the input terminal IN is an intermediate potential between the power supply potential VDD and the ground potential, the first and second PMOS transistors Q1, Q2 and the current limiting unit I1 pass through. The current can be reduced to the current set by the current limiting unit I1. For example, if a current source that supplies a current of sub-microamperes (100 nA) or less is used as the current limiting unit I1, the through current can be reduced to sub-microamperes or less. Therefore, if the threshold circuit of this embodiment is used, the power of the sensor node chip on which the threshold circuit is mounted can be reduced to the nanowatt level limit.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing a configuration of a threshold circuit according to the second embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the second PMOS transistor Q2, the third PMOS transistor Q3, the gate terminal and the source terminal are connected to the ground potential, and the drain terminal is the second one. The first NMOS transistor Q4 is connected to the drain terminal of the PMOS transistor Q2 and the output terminal OUT.

  In the present embodiment, a first NMOS transistor Q4 is used as a specific example of the current limiting unit I1 of the first embodiment. In the present embodiment, the through current flowing through the first and second PMOS transistors Q1 and Q2 and the first NMOS transistor Q4 when the voltage at the input terminal IN is an intermediate potential between the power supply potential VDD and the ground potential, The magnitude of the leakage current of the first NMOS transistor Q4 can be set, and the through current can be reduced to about picoampere compared to the through current of several tens of microamperes of the conventional threshold circuit.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of a threshold circuit according to the third embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the second PMOS transistor Q2, the third PMOS transistor Q3, the gate terminal is connected to the fixed potential terminal REF, and the source terminal is set to the ground potential. The first NMOS transistor Q5 is connected and has a drain terminal connected to the drain terminal of the second PMOS transistor Q2 and the output terminal OUT.

As in the second embodiment, this embodiment is a specific example of the first embodiment. The first NMOS transistor Q5 is used as the current limiting unit I1, and the gate of the first NMOS transistor Q5. A configuration in which a fixed potential is input to the terminal is used.
In the present embodiment, the voltage of the fixed potential terminal REF, that is, the gate voltage of the first NMOS transistor Q5 constituting the current limiting unit is arbitrarily adjusted in the range from the ground potential to the threshold voltage of the NMOS transistor, The current of the current limiting unit can be arbitrarily adjusted in the range of picoamperes to submicroamperes. In the present embodiment, the current flowing through the current limiting unit can be increased compared to the second embodiment by setting the current of the current limiting unit to about sub-microamperes. Can be speeded up, and threshold processing can be performed at high speed.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of a threshold circuit according to the fourth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a second PMOS transistor Q2, a third PMOS transistor Q3, and a first terminal that is a drain terminal and an output terminal of the second PMOS transistor Q2. The current limiter I2 is connected to the OUT, the second terminal is connected to the ground potential, and the current control terminal is connected to the input terminal IN.

In the present embodiment, the current of the current limiting unit I2 is controlled by the voltage of the input terminal IN, and the current of the current limiting unit I2 increases as the voltage of the input terminal IN increases. And different.
In the present embodiment, the current of the current limiting unit I2 is equal to that in the first embodiment until the voltage at the input terminal IN rises and the first and second PMOS transistors Q1 and Q2 approach the off state. The current of the current limiting unit I2 when the voltage at the input terminal IN is sufficiently high and the first and second PMOS transistors Q1 and Q2 are turned off is sub-microampere. By making it larger than this, the transition of the voltage at the output terminal OUT can be speeded up while maintaining the effect of reducing the through current of the first embodiment, and the threshold processing can be performed at high speed.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of a threshold circuit according to the fifth embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the second PMOS transistor Q2, the third PMOS transistor Q3, and the drain terminal are connected to the drain terminal and the output terminal OUT of the second PMOS transistor Q2. A first NMOS transistor Q6 having a source terminal connected to the ground potential, a gate terminal and a drain terminal connected to the input terminal IN, and a source terminal connected to the gate terminal of the first NMOS transistor Q6; 2 NMOS transistors Q7.

  This embodiment is a specific example of the fourth embodiment, and the current limiting unit I2 includes a first NMOS transistor Q6 and a second NMOS transistor Q7, and a diode-connected second NMOS transistor Q7. The voltage of the input terminal IN is applied to the gate terminal of the first NMOS transistor Q6 via In the present embodiment, the current of the first NMOS transistor Q6 is controlled by a voltage that is dropped from the voltage of the input terminal IN by the threshold voltage of the NMOS transistor.

The operation of this embodiment will be described. As described in the first embodiment, when the voltage at the input terminal IN is Low, the first and second PMOS transistors Q1 and Q2 are turned on, but the first NMOS transistor Q6 is turned off. . At this time, the current of the current limiting unit is set to the leakage current of the first NMOS transistor Q6.
When the voltage at the input terminal IN increases from Low to High, the first and second PMOS transistors Q1 and Q2 approach the off state, and the voltage at the output terminal OUT decreases from High to Low. As the voltage at the input terminal IN increases, the gate voltage of the first NMOS transistor Q6 increases and the current of the first NMOS transistor Q6 increases. The effect of this embodiment is the same as that of the fourth embodiment.

  If the number of second NMOS transistors Q7 is increased by connecting a plurality of diode-connected second NMOS transistors Q7 in series, the gate voltage of the first NMOS transistor Q6 can be lowered. The current flowing through the NMOS transistor Q6 can be reduced, and the power consumption of the threshold circuit can be reduced.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a threshold circuit according to the sixth embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the second PMOS transistor Q2, the third PMOS transistor Q3, the first NMOS transistor Q6, and the gate terminal are connected to the input terminal IN. The second NMOS transistor Q8 has a drain terminal connected to the power supply potential VDD and a source terminal connected to the gate terminal of the first NMOS transistor Q6.

  This embodiment is different from the fifth embodiment in that the drain terminal of the second NMOS transistor Q8 is connected to the power supply potential VDD. The operation as a threshold circuit is the same as in the fifth embodiment. By connecting the drain terminal of the second NMOS transistor Q8 to the power supply potential VDD in this way, the parasitic capacitance of the drain terminal of the second NMOS transistor Q8 can be disconnected from the input terminal IN. The input capacitance of the threshold circuit can be reduced as compared with the configuration.

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a threshold circuit according to the seventh embodiment of the present invention.
In the threshold circuit of the present embodiment, the first PMOS transistor Q1, the second PMOS transistor Q2, the third PMOS transistor Q3, the first NMOS transistor Q6, and the gate terminal are connected to the input terminal IN. A second NMOS transistor Q8 having a drain terminal connected to the power supply potential VDD, a gate terminal and a drain terminal connected to the source terminal of the second NMOS transistor Q8, and a source terminal connected to the gate terminal of the first NMOS transistor Q6. And a third NMOS transistor Q9 connected to the first NMOS transistor Q9.

In the sixth embodiment, the third NMOS transistor Q9 connected in a diode connection is inserted between the source terminal of the second NMOS transistor Q8 and the gate terminal of the first NMOS transistor Q6. And different.
In the present embodiment, the current of the first NMOS transistor Q6 is controlled by a voltage that is two stages lower than the threshold voltage of the NMOS transistor from the voltage of the input terminal IN. With this configuration, in the present embodiment, the current flowing through the first NMOS transistor Q6 can be made smaller than in the sixth embodiment, and the power consumption of the threshold circuit can be reduced.

  Note that if the number of third NMOS transistors Q9 is increased by connecting a plurality of diode-connected third NMOS transistors Q9 in series, the gate voltage of the first NMOS transistor Q6 can be lowered. The current flowing through the NMOS transistor Q6 can be further reduced.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a threshold circuit according to the eighth embodiment of the present invention.
The threshold circuit of the present embodiment includes a first PMOS transistor Q1, a second PMOS transistor Q2, a third PMOS transistor Q3, a first NMOS transistor Q6, a second NMOS transistor Q8, 3 NMOS transistor Q9, the first terminal is connected to the connection point between the gate terminal of the first NMOS transistor Q6 and the source terminal of the third NMOS transistor Q9, the second terminal is connected to the ground potential, The control terminal is composed of a switch SW1 connected to the initialization terminal RST.

This embodiment is different from the seventh embodiment in that it includes a switch SW1 that initializes the voltage of the gate terminal of the first NMOS transistor Q6.
The operation of this embodiment will be described. When the sensor node is initialized, the switch SW1 is turned on by an initialization signal supplied from the control circuit (not shown) to the initialization terminal RST, the gate terminal of the first NMOS transistor Q6 becomes the ground potential, and the first NMOS transistor Q6 is turned off. Thereafter, the control circuit turns off the switch SW1, and the threshold circuit waits for an input signal. Subsequent operations are the same as those in the fifth to seventh embodiments.

  In the present embodiment, even when the voltage at the gate terminal of the first NMOS transistor Q6 becomes high due to noise or the like, the gate terminal of the first NMOS transistor Q6 is initialized when the sensor node is initialized. By doing so, it is possible to prevent an increase in the current flowing through the first NMOS transistor Q6.

  In the first to eighth embodiments, the example in which the threshold circuit is applied to the sensor node has been described. However, the present invention is not limited to this, and the present invention can also be applied to other than the sensor node. .

  The present invention can be applied to a threshold circuit used for a sensor node or the like.

  Q1, Q2, Q3 ... PMOS transistor, Q4, Q5, Q6, Q7, Q8, Q9 ... NMOS transistor, I1, I2 ... Current limiting unit, SW1 ... Switch, IN ... Input terminal, OUT ... Output terminal, RST ... Initialization Terminal.

Claims (5)

A first first polarity transistor having a gate terminal connected to the input terminal and a source terminal connected to a first common potential;
A second first polarity transistor having a gate terminal connected to the input terminal, a source terminal connected to the drain terminal of the first first polarity transistor, and a drain terminal connected to the output terminal;
A gate terminal is connected to the output terminal, a source terminal is connected to a connection point between the drain terminal of the first first polarity transistor and the source terminal of the second first polarity transistor, and the drain terminal is a second terminal. A third first polarity transistor connected to a common potential;
A first terminal connected to the output terminal; a second terminal connected to the second common potential; and a current limiting unit configured to limit a current flowing from the first terminal to the second terminal. ,
The current limiting unit is controlled based on a voltage of the input terminal, and increases a current value from a picoampere level to a microampere level according to a voltage change of the input terminal . The threshold circuit according to claim 1 , wherein
The current limiting unit is
A first second polarity transistor having a drain terminal connected to the output terminal and a source terminal connected to the second common potential;
One or more second second polarity transistors having a gate terminal and a drain terminal connected to the input terminal and a source terminal connected to a gate terminal of the first second polarity transistor, Threshold circuit. The threshold circuit according to claim 1 , wherein
The current limiting unit is
A first second polarity transistor having a drain terminal connected to the output terminal and a source terminal connected to the second common potential;
And a second second polarity transistor having a gate terminal connected to the input terminal, a drain terminal connected to the first common potential, and a source terminal connected to the gate terminal of the first second polarity transistor. A threshold circuit characterized by comprising. The threshold circuit according to claim 3 , wherein
The current limiting unit is further inserted between a source terminal of the second second polarity transistor and a gate terminal of the first second polarity transistor, and a gate terminal and a drain terminal are the second second terminal. A threshold circuit comprising: one or more third second polarity transistors connected to a source terminal of a polarity transistor, the source terminal being connected to a gate terminal of the first second polarity transistor. The threshold circuit according to any one of claims 2 to 4 ,
The threshold circuit further comprises an initialization switch for setting the voltage of the gate terminal of the first second polarity transistor to the second common potential at the time of initialization.

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