JPH01138808A - Voltage comparator circuit - Google Patents

Abstract

PURPOSE:To attain the voltage comparison between a holding signal and a reference signal is excellent way by bringing an output of a 1st capacitor to a low impedance state and holding an input signal from a 2nd switch circuit with high accuracy. CONSTITUTION:With switch circuits SW2, SW3 and SW4 turned on, since the output terminal of the capacitor C1 is in a low impedance because a constant voltage source 3 is connected thereto, even if an input signal Vin2 sampled by the circuit SW2 is a high frequency signal, it is held in the capacitor C1 with high accuracy. A potential difference between a potential at other terminal of the capacitor C1 and that at an operating point of an inverted amplifier circuit 2 is charged in the capacitor C2. Then the switch circuits SW2, SW3 and SW4 are turned off and the input signal Vin1 being a reference of voltage comparison is sampled, then the circuit SW1 is turned on and a potential being the sum of the signals Vin1 and Vin2 to the potential at the operating point of the circuit 2 appears at the input terminal of the circuit 2. Thus, a potential being the amplification of the potential difference between the signals Vin1 and Vin2 is obtained at the output terminal of the circuit 2 and then excellent voltage comparison is applied.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a voltage comparison circuit used in an analog-to-digital conversion circuit for high frequency signals such as television video signals. In particular, the present invention relates to a voltage comparison circuit that switches and supplies two input signals to one capacitor.

(Prior Art) This type of conventional voltage comparator circuit is, for example, “Mono
lithic Expandable 6 Bit 2
0MHz 0MO8/5O8AID Convert
r” IEEE J,of S,S,C,vol,5
c-14rA6 e December 1979 e
It is constructed as shown in FIG. 19, as shown in pp, 926-932, etc. That is, the first input signal voltage vln1 is selected by the first CMOS switch SWt and supplied to one end of the capacitor C, and the second input signal voltage vin2 is selected by the second CMOS switch SWt. and is supplied to one end of the capacitor C. The other end of this capacitor C is connected to the input end of an inverting amplifier circuit (for example, a CMOS inverter) ff, and a third CM is connected between the output node of this inverting amplifier circuit Iv and the human power node.
OS switch SW3 is connected. Each of the above CMOS
The switches g'ii1*gVi2*SWs each have a Pf-y channel transistor and an N-channel transistor connected in parallel, respectively, and receive complementary lock signals φl and φs, respectively, as shown in the figure (see FIG. 20). is given to the dart, and the on and off states are reversed for the first CMOS switch SWIS(fgWz) and the third CMOS switch SW.

Note that DD is a high-potential side power supply voltage, and vss is a low-potential side power supply voltage.

In the above circuit, when the second CMOS switch sw2 is on, the direct voltage vCl' at one end of the capacitor C (node Nl)
1vC="ln2. At the same time, the third CMOS switch SW is also turned on, so the output 'direct voltage vout' of the inverting amplifier circuit IV is connected to the other end (node Nz) of the capacitor C.
is fed back, and the voltage V at this node N2 is the operating point voltage v0. of the inverting amplifier circuit v. becomes. At this time, the capacitance C
The potential difference between both ends of is (Vop-"in2).

This means that the input signal voltage vin2 is held at the capacitance tC. Next, the second CMOS switch SW
CMOS switch SW3 of snow SWs is not turned off, 1st
0MO8swiy f swx: 11>” Off K
Then, vo=v1n1. At this time, the potential difference between both ends of the capacitor C does not change, vl = (■!ni
−”l n2 ) +vop.

Here, the voltage gain of the inverting amplifier circuit IV is −K(K)0)
Then, the output voltage V. at--K(vlnl-vi
n2 ) + vop and input signal voltage vln1 ”
An output is obtained by amplifying the potential difference of ln2, and vinl,
You can see the size relationship of vin2.

By the way, in order to perform the above voltage comparison with high accuracy, the third
When the CMOS switch SW is on, the voltage vi of the 7-domain is accurately v. First of all, it is necessary that the value is p. The equivalent circuit at this time is shown in Figure 21.
V1U2 is the input signal source, and Rout is the resistance of the feedback path including the on-resistance of the third CMOS switch SW3. Here, to simplify the explanation, vin2 is a sine wave with an angular frequency ω, and vo.

-0, the steady solution (the solution after a sufficient period of time has elapsed since the third CMOS switch 3 was turned on) is as follows. Here, vl is the potential at the input terminal of the inverting amplifier circuit IV, Iv1n21 is the amplitude of vln□, and v
-1v21 ej” (j is a complex number, t is time)
It is n2. The input terminal of the inverting amplifier circuit IV must be vo, but it shows that an error occurs by the amount expressed by equation (1), υ, ω = 0, that is, when υvln2 is a DC voltage, K is vi = 0, the error is zero, but it can be seen that as ω increases, the steady error becomes smaller.

If we try to reduce this error, C2Rout'1
It is possible to reduce vin21, but C2
It is technically difficult to reduce Rout, and 1v
If ln21'to is made smaller, a problem arises in that the accuracy of the voltage comparator circuit must be increased because the input signal becomes smaller.

Therefore, when a high frequency signal such as a TV broadcast video signal is input as the second input signal voltage vin2, it is impossible to maintain the voltage ``ln2'' with high precision in the capacity, so that a good voltage comparison can be made. was difficult.

(Problems to be Solved by the Invention) As described above, the present invention has a problem in that when a high frequency signal is input, it becomes impossible to accurately hold the input signal voltage in the capacitor for holding the input signal voltage. This was done to solve the problem of not being able to compare voltages.
It is an object of the present invention to provide a voltage comparison circuit which is capable of accurately holding a high-frequency signal input such as a video signal in a capacitor, and capable of performing an accurate voltage comparison.

[Structure of the Invention] (Means for Solving the Problems) The 'sl voltage comparator circuit of the present invention connects the first input signal and the second input signal to the first switch circuit and the second switch circuit, respectively. The other ends of both switch circuits are connected together, and the output is input to the inverting amplifier circuit through the first capacitor and the second capacitor in series. A third switch circuit is connected between the input and output terminals, and a fourth switch circuit is connected between the other end of the first capacitor and a constant voltage source (including the ground potential terminal). shall be.

Further, the second voltage comparison circuit of the present invention is an impedance conversion circuit having high input impedance/low output power/bead/s between the first capacitance and the second capacitance of the first voltage comparison circuit. It is characterized by inserting.

(Function) In the first voltage comparison circuit, the second switch circuit to which the input signal to be compared is input and the inverting amplifier circuit are turned on, and the third switch circuit between the output terminal is turned on, and the fourth switch circuit is turned on. When turned on, the output end of the first capacitor is in a low impedance state, so even if the input signal sent/brought by the second switch circuit is a high frequency signal, it will be sent to the first capacitor with high accuracy. Retained. At this time, the second capacitor is charged with the potential difference between the other end of the first capacitor and the operating point of the inverting amplifier circuit. Next, 1 second switch circuit,
Turn off the third switch circuit and the fourth switch circuit,
Furthermore, when the first switch circuit is turned on to sample an input signal that serves as a reference for voltage comparison, the input terminal of the inverting amplifier circuit receives the first input signal and the second input signal at the operating point of the inverting amplifier circuit. The potential added to the potential difference with the signal appears.

Therefore, an amplified potential difference between the first input signal and the second input signal is obtained at the output end of the inverting amplifier circuit.
A good voltage comparison will now be made.

In addition, in the second voltage comparison circuit, in addition to obtaining the same operation as the first voltage comparison circuit, the presence of the impedance conversion circuit allows charge to be transferred between the first capacitor and the second capacitor. This prevents the sensitivity of the voltage comparator circuit from decreasing.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, s'w1 is the first input signal vin.

The first switch circuit inputs s′w! is a second switch circuit to which the second input signal vin2 is input, and the respective output terminals of both switch circuits SW1 and SW2 are connected together and connected to one end of the first capacitor C1. The output terminal of the first capacitor C1 is connected to the impedance conversion circuit 1 having high input impedance/low output impedance and the second capacitor C! are sequentially connected to the input end of the inverting amplifier circuit 2, and a third switch circuit SW3 is connected between the output end and the input end of the inverting amplifier circuit 2. Further, the output end of the first capacitor C1 is connected to a low impedance constant voltage source 3 via a fourth switch circuit SW4.

Next, the operation of the voltage comparison circuit will be explained. Second switch circuit Sw2, third switch circuit SW3 and fourth switch circuit
When the first switch circuit SW is turned on and the first switch circuit SWl is turned off, the equivalent circuit becomes as shown in FIG. Here, v1n2 is the input signal source, Rout
is the resistance between the input and output terminals of the inverting amplifier circuit including the on-resistance of the third switch circuit SW3, and Rout2 is the resistance looking at the constant voltage source 3 including the on-resistance of the fourth switch circuit SW4, The input terminal of 2 is the output voltage v0. is being fed back, so the operating point voltage v0. become. Now, to simplify the explanation, vin2 is assumed to be a sine wave with an angular frequency ω, and the output voltage vr of the constant voltage source 3 in a no-load state and the operating point voltage v0. If we calculate a steady solution (that is, a solution after a sufficient period of time has passed since the second, third, and fourth switch circuits are turned on) with each of
The voltage V! at the output end (node Ns) of At the same time, the second capacitance C becomes the input terminal (node N, ) of the snow. here,
K2 is the voltage gain of the impedance conversion circuit 1. Also, the second capacity C! The voltage v4 at the output terminal (node N4) of the inverting amplifier circuit 2 and the input terminal of the inverting amplifier circuit 2 becomes as follows, where the voltage gain of the inverting amplifier circuit 2 is expressed by -K (K>O). At this time, the first capacitance C! The potential difference between both ends of vc
1. The potential difference vc2 between both ends of the second capacitor c3 is "1-"
-vin2... (5). Next, contrary to the above, the second switch circuit SW,
, the third switch circuit sws and the fourth switch circuit SW are turned off, and the first switch circuit SW1 is turned off.
When turned on, the voltage v2 at node N and the voltage v4 at node N4 are ``vCt +vin, .
・(7) becomes. The second term in the above equation (8) corresponds to an error, but it is found that it is smaller by the amount of error compared to both equations (1). The above equation (9) takes a value of 1 or less, and can actually be set sufficiently smaller than 1, so it can be almost ignored. For example, Izl-x
, c plate=1pF, Rout2=2Ω, ω=2πX4X
10 rad/s@e, the value of the above equation (9) is approximately 0.05. Therefore, the output voltage of the inverting amplifier circuit 2 is vout = KxK1 (vinl - vin2)
"'Q') and input signal v1nj"
An output is obtained by amplifying the potential difference of ln2, and vinl,
You can see the size relationship of vin□.

That is, according to the voltage comparison circuit, most of the input signal is held in the first capacitor C1, which is charged by the potential difference between the input signal and the constant voltage source 3, and when the constant voltage source 3 is input, Due to the potential difference between the output of the impedance conversion circuit 1 and the operating point voltage of the inverting amplifier circuit 2 and the slight input signal component that could not be held by the first capacitor C, the second capacitor C! The alternating current component added to the inverting amplifier circuit 2 becomes small, and the input terminal of the inverting amplifier circuit 2 is not exactly at the operating point voltage.Even if the input signal vln2 is a high frequency signal, it is possible to temporarily hold the sampling signal with high precision. This makes it possible to perform a good voltage comparison between this holding voltage and another input signal vin1 that is newly input.

The inverting amplifier circuit 2 may have various configurations as shown in FIGS. 3 to 7, and the impedance conversion circuit 1 may have various configurations as shown in FIGS. 3 to 13, for example. Various configurations are possible. That is, the inverting amplifier circuit shown in FIG. 3 is a CMOS inverter in which a P-channel transistor P and an N-channel transistor N are connected in series, and each r''-gate is connected in common. The inverting amplifier circuit consists of a constant current source 1 and an N channel resistor N connected in series.
This is a channel MOS inverter. The inverting amplifier circuit shown in FIG. 5 is a P-channel MOS inverter in which a P-channel MOS transistor P and a current source 12 are connected in series. Furthermore, the inverting amplifier circuit shown in FIG. 6 has a P channel transistor P and a resistance element R connected in series.
This is a channel MOS inverter. The inverting amplifier circuit shown in FIG. 7 is an N-channel MOS inverter in which a resistance element R and an N-channel MO8 transistor N are connected in series.

On the other hand, the impedance conversion circuit shown in FIG. 8 is formed by connecting in series a load P-channel transistor P and an N-channel transistor N whose drains are connected to each other. Moreover, the impedance conversion circuit in FIG.
A channel transistor P and an N-channel transistor N whose drains and darts are connected to each other are connected in series. The impedance conversion circuit of FIG. 10 also includes an N-channel inverter IVN in which a current source 11 and an N-channel transistor N are connected in series, and a P-channel inverter in which a P-channel transistor P and a current source L2 are connected in series. IV, are connected in cascade. Further, in the impedance conversion circuit shown in FIG. 11, the connection order between the N-channel i/verter IV and the P-channel i/verter vP shown in FIG. 10 is reversed. The impedance conversion circuit shown in FIG. 12 is a cascade connection of the impedance conversion circuit shown in FIG. 8 and the impedance conversion circuit shown in FIG. 9. The impedance conversion circuit shown in FIG. 13 is obtained by reversing the connection of each circuit stage of the impedance conversion circuit shown in FIG. 12.

It should be noted that the constant current sources 11 and 12 described above may each be a P-channel transistor or an N-channel transistor, as shown in FIGS. 14 and 15, respectively. -) is given a bias voltage vBt equal to v'B.

Further, the constant voltage source 3 in FIG. 1 may be one that supplies a constant voltage at least during a certain period of time during which the switch circuit SW4 is on; for example, in FIG.
), the r-) and drains are connected to each other as shown in P
A channel transistor P and an N-channel transistor N whose drains and r-tones are connected to each other may be connected in series, or as shown in FIG. A voltage dividing resistor R1JR may be connected in series with the source node.

Also, the second section in FIG. Third. The fourth switch circuits SW2 + SW3 and SW4 each receive a lock signal φ1 complementary to a CMOS switch (transfer ff-), as shown in FIG. 17(a), for example.
．． φzi'r) is given as a signal,
The first switch circuit history is a CMOS switch as shown in FIG. 17(b). Third. The fourth switch circuit is complementary to the clock signal φ2. φ1 is given as a dart signal.

However, the impedance conversion circuit 10 in the above embodiment
The input bias is provided by a constant voltage source 3, but if the input bias can be a ground potential, the constant voltage source 3 may be used as a ground potential terminal. Furthermore, even if the impedance conversion circuit in the voltage comparison circuit shown in FIG. 1 is omitted, as in the voltage comparison circuit shown in FIG. Effects can be obtained. However, in this case, although the circuit configuration is simple, there is a risk that the sensitivity of the voltage comparator circuit will drop because charges will move between 01101 due to stray capacitance at the input terminal of the inverting amplifier circuit 2. .

[Effects of the Invention] As described above, according to the voltage comparator circuit of the present invention, even high-frequency signal input can be held in the capacitor with high accuracy, and the voltage comparison between this held signal and the reference signal can be made well. can be done. Furthermore, by adding an impedance conversion circuit, the sensitivity of the voltage comparison circuit can be improved.

Therefore, the circuit of the present invention is suitable for use in, for example, an analog-to-digital conversion circuit for high frequency signals such as a telepino signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the voltage comparison circuit of the present invention, FIG. 2 is a diagram showing both circuits when the circuit of FIG. 1 samples and holds a comparison input signal, and FIG. 7 to 7 are circuit diagrams showing different specific examples of the inverting amplifier circuit in FIG. 1, and FIGS. 8 to 13 are circuit diagrams showing different specific examples of the impedance conversion circuit in FIG. Figures 14 and 15 are circuit diagrams showing specific examples of the constant current sources in Figures 4 and 5, and Figures 16 (a) and (b) are circuit diagrams showing different examples of the constant voltage sources in Figure 1, respectively. Schematic diagram showing an example, 1st
7(&), (b) is a circuit diagram showing a specific example of the switch circuit in FIG. 1, FIG. 18 is a configuration explanatory diagram showing another embodiment of the present invention, and FIG. 19 is a conventional voltage comparison A circuit diagram showing the circuit, FIG. 20, shows the clock signal φ1. in FIG. 19. FIG. 21 is a waveform diagram showing the waveform of φ and is a diagram showing the circuit when the circuit of FIG. 1 samples and holds the comparison input signal. l... Impedance conversion circuit, 2... Inverting amplifier circuit, 3... Constant voltage source, 11.12... Constant current source, C
1°C2...capacitance, SW, ~SW4...switch circuit, R...resistance, P, N...-transistor, vln
...Input voltage, Vout...Output voltage. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4 Foil Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Trace 13 Figure 14 Figure 15 Figure 16 (a) (b) Figure 17 (a) (b) Figure 18

Claims (2)

[Claims] (1) A first switch circuit to which an input signal serving as a reference for voltage comparison is given to one end side, a second switch circuit to which one end side is given an input signal to be subjected to voltage comparison, and both switch circuits. A first capacitor with one end commonly connected to the other end, a second capacitor with one end connected to the other end of the first capacitor, and an input terminal connected to the other end of the second capacitor. a third switch circuit connected between the input and output terminals of the inverting amplifier circuit; and a fourth switch circuit connected at one end to the connection point between the first capacitor and the second capacitor.
A voltage comparison circuit comprising: a switch circuit; and a constant voltage source connected to the other end of the fourth switch circuit. (2) A first switch circuit to which an input signal serving as a reference for voltage comparison is given to one end side, a second switch circuit to which one end side is given an input signal to be the subject of voltage comparison, and both of the above-mentioned switch circuits. The first end is commonly connected to the other end.
an impedance conversion circuit having a high input impedance/low output impedance whose input end is connected to the other end of this first capacitor, and a second impedance conversion circuit whose one end is connected to the output end of this impedance conversion circuit. a capacitor, an inverting amplifier circuit whose input terminal is connected to the other end of the second capacitor, a third switch circuit connected between the input and output terminals of the inverting amplifier circuit, and an input of the impedance conversion circuit. a fourth switch circuit with one end connected to the end;
and a constant voltage source connected to the other end of the switch circuit.