JP4559908B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier widely applied to electric / electronic devices, and more particularly to an operational amplifier that optimizes current consumption of a buffer circuit connected between operational amplifier circuits on an input side and an output side.

Figure 2 is a circuit diagram of a conventional operational amplifier 10 which is described in Patent Document 1, which includes a buffer circuit A _B between the input of the differential amplifier circuit A ₁ outputs an output amplifier circuit A ₂ It is. That is, the operational amplifier 10 includes a differential amplifier circuit A ₁ and an output amplifier circuit A _2, and a buffer circuit _{AB connected} in series between the output terminal of the differential amplifier circuit A _{1 and} the input terminal of the output amplifier circuit A _2. Connected to and configured. Further, a resistor having a resistance value R _C and a capacitor having a capacitance C _C are provided between the output terminal of the differential amplifier circuit A ₁ and the connection between the buffer circuit A _B and the output terminal of the output amplifier circuit A _2. A phase compensation circuit configured to be connected in series is provided. Examples of the differential amplifier circuit A _1, is considered a circuit as in FIG. 8, and amplifies the voltage difference Vin of the input V + and V-, and outputs a V _x. Also, Ci ₂ are input capacitance of the output amplifier circuit _{A 2,} Ci _B is the input capacitance of the buffer circuit _{A B, C L} is output capacitance, IL the output current (output load current), Vin is to the differential amplifier circuit input voltage, Vout is the output voltage from the output terminal of the output amplifier circuit, V _X and Vy is the operating voltage.

  The small signal equivalent circuit of the above circuit is as shown in FIG. 3, and the transfer function H (S) is obtained as in the following equation (1).

However, the DC gain A ₀ , the poles P _{1 to} P ₄ , and the zero point Z are as shown in the following equations (2) to (7).

here,
gm1: transconductance of the differential amplifier circuit _{A 1} gm2: output amplifier transconductance of the circuit _{A 2} Ro1: output impedance of the differential amplifier circuit _{A 1} Ro2: a buffer circuit _{A B:} Output amplifier _{A 2} output impedance P ₄ pole Ro _B caused by adding: output impedance Ci of the buffer circuit _{a B B:} input capacitance of the buffer circuit _{a B} G _B: DC gain of the buffer circuit _{a B} (in the case of the buffer, usually 1)
That is, the resistance value _{R C} and the capacitance value _{C C} pole _P by the value 1 to P _3, and the zero point Z may be set anywhere. A general design method for securing the phase margin is to set the pole P ₂ to a high frequency with respect to the GB product expressed by the product of the DC gain A ₀ and the pole P ₁ .

The resistance value R _C and the resistance value C _C are determined so as to satisfy this equation (8), and the pole P ₂ and the zero point Z are set to a high range. That is, the following equation (9) is obtained from the equations (2) to (7).

Further, with respect to the pole _{P 3} (5), a (8) the following equation from the equation (10).

となる。ここで、通常Ｃｉ_Ｂ≪Ｃ_Ｃ、Ｃ_Ｌであるので上式（９）は、

It becomes. Here, since usually Ci _B << C _C , C _L , the above equation (9) is

The equation (11) and, since the pole P ₃ will be present in sufficient high frequency with respect to GB product, which does not degrade the phase characteristic.
With respect to the pole _{P 4} occurring in the output of the buffer circuit _{A B,} condition of the output impedance Ro _B is the formula of the buffer circuit _{A B} (12)

を満足する時、Ａ_０・Ｐ_１＜Ｐ_４となるので極Ｐ_４は高域に存在することになる。ここで、上式（１２）を満足するには、差動増幅回路Ａ_１の伝達コンダクタンスｇｍ_１を小さくする、あるいは、バッファ回路Ａ_Ｂの出力インピーダンスＲｏ_Ｂを小さくすれば良い。

When satisfying A ₀ , P ₁ <P ₄ , the pole P ₄ exists in the high frequency range. Here, in order to satisfy the above equation (12), to reduce the transfer conductance gm ₁ of the differential amplifier circuit _{A 1,} or may be low output impedance Ro _B of the buffer circuit _{A B.}

FIG. 4 shows an example of the buffer circuit. Normally, a circuit for supplying a bias current IB is connected to the source terminal of the PMOS (not shown). The buffer circuit _{A B} is a PMOS source follower, the output impedance Ro _B is represented by 1 / gm. Where gm is the transconductance of the buffer circuit A _B.
Generally, since the transfer conductance gm of the MOS being in the saturation region is proportional to the square root of the drain current, the output impedance Ro _B of the buffer circuit A _B will be inversely proportional to the square root of the bias current Ib. As described above, the output impedance of the buffer circuit generally depends on the bias current.

Therefore, in order to reduce the output impedance Ro _B may Increasing the bias current of the buffer circuit A _B. Similarly, to reduce the transfer conductance gm ₁ of the differential amplifier circuit A ₁ may reducing the bias current of the differential amplifier circuit A _1.
The phase characteristics at this time are shown in FIG. However, in FIG. 5, the vertical axis is gain and phase, and the horizontal axis is frequency (Frq). As shown in FIG. 5, it can be seen that the pole P ₄ that deteriorates the phase characteristic is shifted to a higher frequency than the unity gain frequency f ₀ . Here, the zero point Z, pole P ₂ and pole P ₃ are not shown because they are still higher range than the pole P _4. In this way, the phase margin can be secured by shifting the pole (here, the pole P ₄ ) that deteriorates the phase characteristics to a higher frequency than the unity gain frequency f ₀ . That is, the phase characteristic can be regarded as a primary system expressed only by the DC gain A ₀ and the pole P ₁ up to the vicinity of the unity gain frequency f ₀ , and the phase characteristic can be improved.
JP 2004-320156 A

By the way, the conventional operational amplifier 10 is used for a regulator or the like, but the output current of the operational amplifier 10 for such a purpose has a wide range from 0 to a large current. Output current I _L is zero state of the operational amplifier 10, for example, load circuit or the like while powered down. For this reason, there is a demand for reducing the current consumption of the operational amplifier 10 itself.
Here, as shown in FIG. 6, the output amplifier circuit A ₂ is generally realized by a source-grounded P-type MOS transistor (simply abbreviated as PMOS) and supplies a bias current to the PMOS 11. 12 is provided. For example, when the output current _{I L} of the operational amplifier 10 is zero, the current flowing through the PMOS11 since a small current of only the bias current supplied from the bias current source 12, the transfer conductance gm ₂ of PMOS11 is reduced. As a result, the pole P ₂ represented by the equation (4) moves to a lower frequency range than f ₀ and the phase margin cannot be obtained.

Therefore, it is general that the zero point Z expressed by the above equation (7) is not moved to a high frequency, but moved to a low frequency, so that the decrease in phase due to the pole P ₂ is offset and the phase margin is secured. It is. The phase characteristics at this time are shown in FIG. However, in FIG. 7, the vertical axis is gain and phase, and the horizontal axis is frequency (Frq).
As can be seen from Figure 7, the zero point Z is located in the low frequency rather than in a high frequency range, it can be seen that by offsetting the decrease in phase by pole P ₂ in that further in the vicinity of if pole P ₂ terms. In this case, as can be seen from the above equation (7), the resistance value R _C of the resistor and the capacitance C _C of the capacitor may be increased.

Further, the resistor is constituted by a PMOS, and the resistance value _RC of the resistor is changed according to the fluctuation of the PMOS transfer conductance gm ₂ of the output amplifier circuit. That is, like the pole P _2, by changing the zero point Z in accordance with a variation in the transfer conductance gm _2, the phase compensation technique to ensure a phase margin while maintaining the gulp relative relationship P ₂ and zeros Z are used .

However, as shown in FIG. 7, there pole P ₂ is the low range than unity gain frequency f _0, because the unity gain frequency f ₀ as compared with the case of FIG. 5 is moved to the low frequency, the high frequency band the shifted pole P ₄ was would have little effect on the phase margin. Therefore, the output impedance Ro _B of the buffer circuit _{A B} is not always necessary to satisfy the above equation (12). From this fact, it is increasing the bias current of the buffer circuit A _B which has been performed in order to satisfy the above equation (12), particularly when the output current I _L is small, with a larger amount consumed current than necessary content Will be.
The present invention has been made in view of such problems, and an object of the present invention is to provide an operational amplifier capable of further reducing current consumption without deteriorating phase compensation characteristics.

In order to achieve the above object, an operational amplifier according to claim 1 of the present invention includes a differential amplifier circuit, a buffer circuit, and an output amplifier circuit connected in series with each other, and a connection point between the differential amplifier circuit and the buffer circuit. And a bias current of the buffer circuit is generated based on a current flowing through an output stage of the output amplifier circuit in an operational amplifier having a resistor and a capacitor connected in series between the output amplifier circuit and the output terminal of the output amplifier circuit And a bias current generating circuit for supplying the bias current as a bias of the buffer circuit.
According to this configuration, since the bias current supplied to the buffer circuit depends on the current flowing through the output amplifier circuit, that is, the output current of the operational amplifier, when the output current is zero or small, the buffer circuit As a result, the current consumption of the operational amplifier can be reduced.

The operational amplifier according to claim 2 of the present invention is characterized in that, in claim 1, the output impedance of the buffer circuit varies according to the transfer conductance of the output amplifier circuit.
According to this configuration, maintaining the relative relationship between the zero point Z and pole P ₂ that varies according to the transfer conductance can remain securing the phase margin. Therefore, the current consumption when the output current of the operational amplifier is small can be reduced while securing the phase margin.
The operational amplifier according to a third aspect of the present invention is the operational amplifier according to the first or second aspect, wherein the buffer circuit is constituted by a source follower, and the bias current is supplied to a source terminal of the buffer circuit. .
An operational amplifier according to a fourth aspect of the present invention is the operational amplifier according to any one of the first to third aspects, wherein the bias current generating circuit includes a current proportional to a current flowing through an output stage of the output amplifier circuit and a current source. The current is added, and the added current is generated as the bias current.

  As described above, according to the present invention, there is an effect that current consumption can be further reduced without deteriorating the phase compensation characteristic.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
FIG. 1 is a circuit diagram showing a configuration of an operational amplifier according to an embodiment of the present invention.
In the operational amplifier 20 shown in FIG. 1, _{A 1} is a differential amplifier circuit, _{A B} is the buffer circuit, _{A 2} is an output amplifier circuit comprised of PMOS21 which is grounded source, supplying a bias current to the buffer circuit _{A B} A bias current generating circuit B is provided.

Bias current generating circuit B includes a PMOS22 and the current source 23, the gate terminal of the PMOS22 is connected to the gate terminal of the PMOS21 of the output amplifier circuit _{A 2,} further adding the current flowing through the drain current and the current source 23 of the PMOS22 It is, which is adapted to the bias current Ib of the buffer circuit a _B. However, Ci _B is the input capacitance of the buffer circuit _{A B,} the _{C L} is output capacitance.

Buffer circuit _{A B,} the output voltage Vout is provide a gate voltage to the PMOS21 to be a desired value. Since the gate voltage of the PMOS 22 is the same as that of the PMOS 21, the drain current of the PMOS 22 has a value proportional to the drain current of the PMOS 21. The drain current of the PMOS 22 is added to the current of the current source 23 which can take 0 regardless of the drain current of the PMOS 21, and this becomes the bias current Ib. The bias current Ib is supplied to the source terminal of the buffer circuit A _B shown in FIG.

Thus, the bias current Ib to be supplied to the buffer circuit _{A B,} a current flowing through the PMOS21 constituting the output amplifier _{A 2,} that is, depends on the output current _{I L} of the operational amplifier 20, the output current _{I L} 0 by the time or a slight or even in, the bias current Ib to be supplied to the buffer circuit a _B requires less, as a result, it is possible to reduce the current consumption of the operational amplifier 20.

As described above, since the output impedance Ro _B of the buffer circuit _{A B} depends on the bias current Ib, the current flowing through the PMOS21 buffer circuit _A output impedance Ro _B output amplifier circuit _{A 2} of _B, that the output amplifier circuit It is possible to vary according to the transfer conductance gm ₂ of A ₂ . Therefore, as can be seen from the above equation (6), the pole P ₄ can be changed according to the transfer conductance gm ₂ of the output amplifier circuit A ₂ .

Here, when the output current I _L or a small or a zero, the bias current Ib to be supplied to the buffer circuit A _B, a current flowing through the PMOS21 constituting the output amplifier A _2, i.e. of the operational amplifier 20 Since it depends on the output current I _L , it is less and the pole P ₄ moves to the low band.
However, since the pole P ₄ varies according to the transfer conductance gm ₂ of the output amplifier circuit A ₂ , the relative relationship between the zero Z and the pole P ₂ that similarly varies according to the transfer conductance gm ₂ is maintained, and the phase margin Can remain secure.

As described above, according to the operational amplifier 20 of this embodiment, the output current I _L of the operational amplifier 20 is small, as shown in FIG. 7 the poles P ₂ represented by the above formula (2) is in the low range In this case, it is possible to move the pole P ₄ represented by the above formula (6) to a low frequency within a range in which the phase margin can be secured, and the current consumption of the operational amplifier 20 can be reduced. In other words, the current consumption can be further reduced without deteriorating the phase compensation characteristics.

It is a circuit diagram which shows the structure of the operational amplifier which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the conventional operational amplifier. It is a circuit diagram showing the small signal equivalent circuit of the conventional operational amplifier shown in FIG. It is a circuit diagram showing an example of a buffer circuit. It is a figure showing the phase characteristic of the conventional operational amplifier shown in FIG. It is a figure showing the general example of the output amplifier circuit of an operational amplifier. Pole P ₂ is in a conventional operational amplifier shown in FIG. 2 is a diagram representing the phase characteristics when a low frequency. It is a circuit diagram showing an example of a differential amplifier circuit.

Explanation of symbols

10, 20 Operational amplifiers 11, 21, 22 P-type MOS transistors 12, 23 Current source A ₁ Differential amplification circuit A ₂ Output amplification circuit A _B Buffer circuit B Bias current generation circuit Ib Bias current I _L Output load current C _L output Load capacitance R _C resistance value C _C capacitance Ci ₂ parasitic capacitance (input capacitance of output amplifier circuit)
Ci _B parasitic capacitance (input capacitance of buffer circuit)
I _L output load current C _L output terminal capacitance V _in Input voltage to differential amplifier circuit V _out Output voltage from output amplifier circuit V _X , V _y Operating voltage gm ₁ Transfer conductance of differential amplifier circuit gm ₂ Output amplifier circuit output impedance Vds drain of the output impedance Ro ₂ output amplifier circuit of the transconductance Ro ₁ differential amplifier circuit - DC gain of the output impedance G _B buffer circuit of the source voltage Vdd drain supply voltage Ro _B buffer circuit

Claims (4)

A differential amplifier circuit, a buffer circuit, and an output amplifier circuit connected in series with each other, and a resistor connected in series between a connection point of the differential amplifier circuit and the buffer circuit and an output terminal of the output amplifier circuit And an operational amplifier having a capacitor,
An operational amplifier comprising a bias current generating circuit that generates a bias current of the buffer circuit based on a current flowing through an output stage of the output amplifier circuit and supplies the bias current as a bias of the buffer circuit.   2. The operational amplifier according to claim 1, wherein an output impedance of the buffer circuit varies according to a transfer conductance of the output amplifier circuit. The buffer circuit is composed of a source follower,
The operational amplifier according to claim 1, wherein the bias current is supplied to a source terminal of the buffer circuit. 2. The bias current generation circuit adds a current proportional to a current flowing through an output stage of the output amplifier circuit and a current of a current source, and generates the added current as the bias current. 4. The operational amplifier according to any one of 3 above.

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