JP2006279172A - Offset eliminating circuit and differential amplifier using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an offset eliminating circuit improved so as to conquer the problem such as an increase in a power consumption, the lowering of an output impedance, a large output offset in the case of the off of an offset-eliminating operation in conventional techniques. <P>SOLUTION: The currents of a differential pair 110 for eliminating an offset and a CMFB circuit 109 are used in common, and changed so as to consume low power and use currents effectively. The output impedance as a current source is increased by cascade-connecting the CMFB circuit 109 under the differential pair 110, and an effect on an output-current offset by the relative dispersion of the CMFB circuit 109 is reduced. The phase of a CMFB loop is compensated easily by largely setting the transconductance of transistors 105 and 106. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an offset removal circuit, and more particularly to an offset removal circuit improved so as to reduce power consumption. The present invention also relates to a differential amplifier having such an offset removal circuit.

  In order to operate the differential circuit using a current load, a common mode feedback (CMFB) circuit is essential. At the same time, the relative variation of the current sources used in the differential circuit becomes the variation of the differential output current as it is. That is, it is necessary to pay close attention to the differential matching accuracy. In the conventional current mode circuit design, the differential offset removal circuit and the CMFB circuit are connected in parallel (for example, see Non-Patent Document 1).

  FIG. 5 is a circuit diagram of a conventional differential amplifier disclosed in the above document and having an offset removing function. The conventional differential amplifier 500 includes a differential pair 501 for signal input, a tail current source 502, a CMFB circuit 503, and a differential offset removal circuit 504.

  In the conventional differential amplifier 500, a control voltage is input to the CMFB voltage input terminal 518 to stabilize the common mode voltage at the output terminals 509 and 510 of the differential amplifier 500. Further, a differential control signal is input to the differential offset control terminals 519 and 520 from an external circuit block (not shown) so that the difference between the output terminals 509 and 510 of the differential amplifier 500 becomes zero. Is controlling. In the figure, reference numerals 505, 506, 515, and 516 denote NOMS transistors, and reference numerals 511 and 512 denote PMOS transistors. Reference numerals 513 and 514 denote current sources, and 517 denotes a resistor.

“A 5-GHz CMOS Transceiver for IEEE 802.11a Wireless LAN Systems” IEEE JSSC VOL.37. NO.12. DECEMBER2002

  In the conventional differential amplifier 500, since the CMFB circuit 503 and the offset removal circuit 504 are arranged in parallel, current consumption is required separately, and power consumption increases.

  In addition, the sum of the current of the CMFB circuit 503 and the current of the offset removal circuit 504 is equal to the current of the tail current source 502, but the designer needs to determine these current values, which makes design difficult. There is a trade-off regarding the determination of the current value. Specifically, if the amount of current flowing through the offset removal circuit 504 is increased, the offset removal amount increases, but the current consumption increases. Conversely, if the amount of current flowing through the offset removal circuit 504 is reduced, the current consumption can be reduced, but the offset removal amount is reduced.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide an offset removal circuit improved so that low power consumption can be efficiently performed.

  Another object of the present invention is to eliminate the difficulty of design due to the trade-off between the offset removal amount and current consumption.

  Still another object of the present invention is to provide an improved differential amplifier so as to eliminate the difficulty of design due to the trade-off between offset removal amount and current consumption.

  The present invention is an offset removal circuit used in a differential circuit, which is composed of two differential first transistors, and controls the current flowing through the two first transistors, whereby the differential circuit described above is used. A first differential pair for controlling a current offset generated in the first differential pair, and the two first transistors for controlling a common mode of the differential circuit by supplying a desired current to the two first transistors. And a pair of current sources provided corresponding to each of the above.

  With the configuration described above, the currents of the first differential pair and the pair of current sources are shared, and the power consumption is reduced. In addition, since the currents of the first differential pair and the pair of current sources are common, the effect of increasing the offset removal amount according to the current is obtained, and the design of the current value for offset removal becomes easy.

  According to a preferred embodiment of the present invention, the pair of current sources includes two differential second transistors and an impedance element. The impedance element is inserted between one drain end and the other drain end of the two second transistors. Further, the drain ends of the two second transistors are connected to correspond to the source ends of the two first transistors, respectively.

  With the configuration described above, the offset removal circuit has a configuration in which the current source and the impedance element are inserted in parallel at the source ends of the two transistors of the first differential pair. There is an advantage that the impedance is increased. The value of the impedance element mainly determines the transfer function for removing the differential offset. Therefore, the transfer function for removing the differential offset can be determined without depending on the variation in the parameters of the two transistors of the first differential pair, and the design is facilitated.

  According to a further preferred embodiment of the present invention, the impedance element is a circuit including at least a resistor. With this configuration, the influence on the output current variation due to the relative variation of the pair of current sources is reduced. For example, even when the offset removal signal cannot be obtained for some reason, the output offset of the differential circuit Can be reduced as much as possible.

  According to a further preferred embodiment of the present invention, the impedance element is a parallel circuit of a resistor and a capacitor. With this configuration, there is an effect of reducing the degree to which the differential offset removal gain drops at high frequencies.

  According to another preferred embodiment of the present invention, a differential voltage signal is input to the respective gate terminals of the two first transistors constituting the first differential pair, whereby the two first transistors It is characterized by controlling the current flowing through the. With this configuration, the differential circuit offset can be removed by the differential voltage signal.

  According to a further preferred embodiment of the present invention, a common mode control voltage is input to each gate terminal of the two second transistors constituting the pair of current sources. . With the above configuration, the common mode of the differential circuit can be controlled by a voltage signal.

  According to a further preferred embodiment of the present invention, the two second transistors constituting the pair of current sources have their source ends grounded at a low impedance, and a common mode control signal is input to their gate ends. The drain ends of the first differential pair are connected to correspond to the source ends of the two first transistors of the first differential pair. With the above configuration, the voltage gain from the common mode control signal to the common mode output can be increased, and the phase compensation of the common mode loop can be effectively performed by the large voltage gain.

  According to a further preferred embodiment of the present invention, the offset removal circuit has a differential transconductor and a first circuit block for detecting a differential offset from a differential output terminal of the differential transconductor, A differential output terminal of the differential transconductor is connected to a differential output terminal of the first differential pair, and a common mode control signal necessary for common mode stability is transmitted from the first circuit block to the pair of current sources. To stabilize the common mode potential of the differential output terminal of the differential transconductor.

  With the above-described configuration, even if the bias current of the differential transconductor fluctuates, the common-mode operating potential of the offset removal circuit is stabilized by adjusting the current of the current source.

  According to a further preferred embodiment of the present invention, the offset elimination circuit includes terminals for supplying a common mode control signal to the pair of current sources, and each of the terminals and the two output terminals of the differential transconductance. Between the capacitor and the resistor connected in series. With the above configuration, it is possible to prevent the common mode potential of the differential transconductor from oscillating even at high frequencies.

  A differential amplifier according to another aspect of the present invention includes a differential circuit for signal input and two differential first transistors, and by controlling a current flowing through the two first transistors, The common mode of the differential circuit is controlled by supplying a desired current to the first differential pair for controlling the current offset generated in the differential circuit and the two first transistors. And a pair of current sources provided corresponding to each of the first transistors.

  With the configuration described above, the currents of the first differential pair and the pair of current sources are shared, and the power consumption is reduced. In addition, since the currents of the first differential pair and the pair of current sources are common, the effect of increasing the offset removal amount according to the current is obtained, and the design of the current value for offset removal becomes easy. As a result, a differential amplifier can be obtained in which the difficulty of design due to the trade-off between the offset removal amount and the current consumption is eliminated.

  According to the present invention, the currents of the differential pair for offset removal and the current source for CMFB are shared, and the power consumption is reduced. In addition, since the current of the differential pair for offset removal and the current of the CMFB current source are common, the effect of increasing the offset removal amount according to the current for CMFB (that is, the current of the entire differential circuit) is obtained. Current value design for offset removal becomes easy.

  The purpose of providing an offset elimination circuit improved so as to achieve low power consumption is to share the currents of the differential pair for offset elimination and the current source for CMFB and effectively use the current. It was realized. Further, the CMFB circuit is cascade-connected under the differential pair for offset removal, thereby increasing the output impedance as a current source and reducing the influence on the output current offset due to the relative variation of the CMFB circuit. Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a typical embodiment of the offset removal circuit of the present invention.

  Referring to FIG. 1, a CMFB control voltage is applied to transistors 105 and 106 from terminal 103, and a differential offset removal voltage signal is applied to transistors 107 and 108 from differential signal input terminals 101 and 102. The current is drawn from the terminals 111 and 112. The terminals 111 and 112 are connected to an arbitrary circuit that requires a differential current. The impedance element 104 is connected between the sources of the transistors 107 and 108, and determines a transfer function to the current output from the voltage signal for offset removal. The transistors 105, 106, 107, and 108 can be realized by MOS transistors or bipolar transistors. The value of the impedance element 104 may be zero [Ω].

  The operation of reducing current consumption will be described with reference to FIGS. In the conventional example shown in FIG. 5, since the CMFB circuit 503 and the offset removal circuit 504 are arranged in parallel, current is consumed separately. However, in this embodiment shown in FIG. 1, since the CMFB circuit 109 and the offset removal circuit 110 are stacked vertically, the current is shared. Therefore, current consumption is reduced as compared with the conventional example.

  1, the value of the impedance element 104 is Ze [Ω], the transconductance of the differential pair 110 is gm [S], and the differential current at the terminals 111 and 112 from the differential offset removal signal applied to the terminals 101 and 102 Assuming that the transfer function to be converted into a signal is H, H = 1 / (1 / (1 / gm) + Ze). It can be seen that a desired transfer function can be obtained if Ze is appropriately designed.

  Consider the case where the impedance element 104 is only a resistor in FIG. The resistance value is Re [Ω], and the reduction of differential variation caused by the process variation of the constant current source will be described. In the conventional example shown in FIG. 5, since the relative variation of the constant current sources 505 and 506 directly becomes the current variation of the differential pair 501, the circuit easily falls into a state where the circuit does not operate unless the offset removal signal is continuously input. End up. On the other hand, the relative variation of the currents of the constant current sources 105 and 106 shown in FIG. 1 is reduced even when the offset removal signal is not input because the impedance variation cancels the current variation. This indicates that it is useful for applications where a differential DC offset removal signal is not always input.

Then, the effect of this differential offset is quantitatively shown using FIG. The block 207 has the same configuration as that of the conventional example shown in FIG. 5, and the block 206 has the same configuration as that of the present embodiment shown in FIG. However, the differential offset removal signal is not input to the blocks 206 and 207, and the same potential is applied to the input terminals 208, 209, 210, and 211 of the differential offset removal signal. The transconductance of the transistors 212, 213, 214, and 215 is Gm1 [S], the transconductance of the transistors 201 and 204 is Gm2 [S], the impedance element 203 is composed of only an actual resistance, the resistance value is Re [Ω], and the process variation , 216 and 217 in the figure, and the input offset voltage is ΔV [V]. In the conventional example indicated by 207 in the figure, the variation amount of the output current is ΔI = Gm1 · ΔV, but in this example of 206 in the figure, ΔI = Gm
1 · ΔV / (1 + 2 / (Gm 2 · Re)), and it can be seen that the differential offset of the output current is reduced in inverse proportion to the value of Gm 2 · Re.

  The improvement of the output impedance will be described with reference to FIG. In the block 207 which is a conventional example, if the output impedance as a current source is Zout1 and the drain resistance of the transistor denoted by 214 in the figure is Rds1 [Ω], Zout1 = Rds1. In 206, the output impedance Zout2 [Ω], the drain resistance of 204 in the figure (the collector-emitter resistance in the case of NPN) is Rds2 [Ω], the transconductance is Gm2 [S], and the resistance of 203 in the figure is Re [Ω], the drain resistance of 201 in the figure (collector-emitter resistance in the case of NPN) is Rds1, and the parallel resistance of Rds1 and (Re / 2) is Rs = Rds1 // (Re / 2) Zout to Rs + [1 + Gm2 · Rs] · Rds2, and by appropriately setting the values of Gm2 and Re, the output impedance of the current source It can be increased to dance.

  FIG. 3 shows an embodiment in which the impedance element 104 in FIG. 1 is realized by parallel connection of a resistor and a capacitor. In this manner, by inserting the resistor 303 and the capacitor 304 in parallel between the sources of the transistors 301 and 302, the degeneration impedance of the differential pair 305 is reduced at a sufficiently high frequency, and the transconductance of the differential pair 305 is reduced. To increase. Therefore, even when the gain of the differential offset removal signal path is reduced at high frequency, the transconductance of the differential pair 305 is increased so as to compensate for the reduced gain, and the operating frequency at which the offset removal function works effectively is increased. Things will be possible.

FIG. 4 shows a specific application example of the offset removal circuit of the present invention. As the load current source 402 of the transconductor 401, the current source 402 having the same configuration as described in FIG. 1 is used. Voltage output terminals 405 and 406 by the differential voltage signal input terminals 403 and 404 are supplied to the common mode voltage detection block 407, and the common mode voltage detection block 407 is supplied to the CMFB control terminal 408 of the load current source 402. Is done. With the above configuration, even if the bias current of the transconductor 401 fluctuates, the output potential of the transconductor 401 is stabilized by adjusting the current of the load current source 402.
Furthermore, by inserting phase compensation capacitors 409 and 410 and resistors 411 and 412 between the CMFB control terminal 408 and the output terminals 405 and 406 of the differential amplifier, the common mode output potential of the transconductor 401 can be increased even at high frequencies. Prevents oscillation. At this time, in order to make the phase compensation capacitors 409 and 410 more effective, the source terminals of the CMFB control transistors 414 and 415 are directly connected to the GND, and the CMFB control terminal 408 of the current source 402 is connected to the output terminal. The voltage gain to 405 and 406 is increased. Incidentally, the resistors 411 and 412 for phase compensation are inserted with appropriate values to cancel the deterioration of the phase margin due to the insertion of the capacitors 409 and 410 for phase compensation.

  Here, the CMFB loop stability will be described in detail. The loop is closed from the output terminals 405 and 406 of the transconductor 401 to the output terminal 408 of the common mode voltage detection block 407 (non-inverting amplification) and then to the output terminal of the current source 402 (inverting amplification), that is, the output terminals 405 and 406. ing. In general, since the common mode voltage detection block 407 and the current source 402 also have a constant gain, the two amplifiers form a loop. At that time, in order to secure loop stability, a capacity for phase compensation is required. In order to reduce the capacity size, a mirror effect is generally used. The Miller effect is to equivalently increase the capacitance value by connecting both ends of the capacitance between the input and output terminals of an inverting amplifier having a large voltage gain. That is, the phase compensation capacitor can be inserted in the CMFB loop described above between the input and output terminals of the inverting amplifier (the current source 402). In order to obtain the effect of phase compensation sufficiently, the voltage gain from the CMFB control terminal 408 to the output terminals 405 and 406 must be sufficiently large.

  That is, it is preferable to increase the transconductance of the transistors 414 and 415 as much as possible without inserting a degeneration resistor in the sources of the CMFB transistors 414 and 415. However, by not inserting a degeneration resistor, the relative variation between the transistors 414 and 415 appears as an output current offset of the current source 402, and the output voltage of the transconductor 401 swings differentially when the offset signal is off. May not operate at all, but the influence of the relative variation of the transistors 414 and 415 is reduced by using the structure of the present invention. Specifically, the impedance 413 plays the role.

  The CMFB control block 407 generates a common mode voltage or current using the differential voltage signal input, and reduces the CMFB control voltage when the common mode is lowered by comparison with a reference voltage or current. In the case of raising the common mode, the circuit form is not limited as long as the block has an operation for lowering the CMFB control signal voltage and converging the common mode voltage to a desired voltage value.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, it is possible to obtain a differential amplifier that eliminates the difficulty of design due to a trade-off between the offset removal amount and current consumption.

1 is a circuit diagram of an offset removal circuit according to Embodiment 1. FIG. It is a figure which compares and shows the conventional example and the offset removal circuit concerning Example 1. FIG. 6 is a circuit diagram of an offset removal circuit according to Embodiment 2. FIG. FIG. 6 is a circuit diagram of an offset removal circuit according to a third embodiment. It is a circuit diagram of the conventional differential amplifier.

Explanation of symbols

104, 203, 413 Impedance element 304, 409, 410 Capacitance 220, 303, 411, 412, 517 Resistance 511, 512... PMOS transistor 105-108, 201, 204, 218, 219, 301, 302, 306, 307 414 to 417, 505, 506, 515, 516 NMOS transistors 222, 221, 513, 514 Current source

Claims (10)

An offset removal circuit used in a differential circuit,
A first differential pair configured by two differential first transistors and controlling a current flowing in the differential circuit by controlling a current flowing through the two first transistors;
A pair of current sources provided corresponding to each of the two first transistors to control a common mode of the differential circuit by supplying a desired current to the two first transistors; Offset removal circuit. The pair of current sources is composed of two differential second transistors and an impedance element,
The impedance element is inserted between one drain end and the other drain end of the two second transistors,
2. The offset removal circuit according to claim 1, wherein drain ends of the two second transistors are connected to correspond to source terminals of the two first transistors, respectively.   The offset removing circuit according to claim 1, wherein the impedance element is a circuit including at least a resistor.   The offset removing circuit according to claim 1, wherein the impedance element is a parallel circuit of a resistor and a capacitor.   The current flowing through the two first transistors is controlled by inputting a differential voltage signal to each gate terminal of the two first transistors constituting the first differential pair. Item 5. The offset removal circuit according to any one of Items 1 to 4.   6. The offset removal circuit according to claim 2, wherein a common mode control voltage is input to each gate terminal of the two second transistors constituting the pair of current sources. .   The two second transistors constituting the pair of current sources have their source terminals grounded at a low impedance, a common mode control signal is input to their gate terminals, and their drain terminals are connected to the first transistors. 7. The offset removal circuit according to claim 2, wherein the offset removal circuit is connected to correspond to the source ends of the two first transistors of the differential pair. 8. The offset removal circuit includes a differential transconductor and a first circuit block that detects a differential offset from a differential output terminal of the differential transconductor,
Connecting the differential output terminal of the differential transconductor to the differential output terminal of the first differential pair;
The common mode potential of the differential output terminal of the differential transconductor is stabilized by applying a common mode control signal necessary for stabilizing the common mode from the first circuit block to the pair of current sources. The offset removal circuit according to any one of claims 1 to 7. The offset removal circuit includes a terminal for supplying a common mode control signal to the pair of current sources,
9. The offset removal circuit according to claim 8, wherein a capacitor and a resistor connected in series are inserted between the terminal and each of the two output terminals of the differential transconductor. A differential circuit for signal input;
A first differential pair configured by two differential first transistors, and controlling a current flowing in the two first transistors to control a current offset generated in the differential circuit;
A pair of current sources provided corresponding to each of the two first transistors to control a common mode of the differential circuit by supplying a desired current to the two first transistors; Differential amplifier.

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