JP2000196432A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a floating time of an input terminal. SOLUTION: A series connection between a pull-down resistor 3 and an N-channel MOS transistor(TR) 4 is placed between an input of an inverter 1 and ground, and an N-channel MOS TR 5 controlled by the output of the inverter 1 is placed between the input of the inverter 1 and ground. In a transient state where a switch in a closed state is open, when a voltage at an input terminal 2 drops up to a threshold voltage of the inverter 1, the N-channel MOS TR 5 is conductive by a high level output of the inverter 1 to forcibly connect an input of the inverter 1 to ground. Thus, the floating time can be reduced and a through-current of the inverter 1 can be avoided. Furthermore, a voltage across a pull-down resistor 3 is decreased by a voltage on the basis of an on-resistance of the N-channel MOS TR 4 so as to reduce the current consumption of the pull-down resistor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for fixing an input signal to a high level or a low level and taking it in.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an input portion in a conventional integrated circuit. FIG. 3 shows a pull-down input circuit.

In FIG. 3, an inverter (101) has a threshold voltage Vdd / 2, and an input side is connected to an input terminal (102). The pull-down resistor (103) is connected between the input terminal (102) and the ground Vss.
The input terminal (102) is externally connected to a switch (not shown) for supplying the power supply voltage Vdd.

First, when the switch is open,
The input of the inverter (101) is a pull-down resistor (10
3), the output of the inverter (101) is supplied to the internal circuit of the integrated circuit while being fixed at a high level. Next, when the switch is closed, the input of the inverter (101) is supplied to the power supply Vdd via the switch.
And the output of the inverter (101) is supplied to the internal circuit of the integrated circuit while being fixed at a low level.
Thereafter, in the transition period when the switch is closed, the input voltage of the inverter (101) falls according to a time constant determined by the resistance value of the pull-down resistor (103) and the wiring capacitance, and the output of the inverter (101) has a threshold voltage of the input voltage. When the voltage falls below Vdd / 2, it is fixed to a high level and supplied to the internal circuit of the integrated circuit.

[0005]

However, in the transition period in which the switch is closed, the input voltage of the inverter (101) is increased even though the output of the inverter (101) is fixed at a high level. Continue descending according to. That is, when the switch is changed from the closed state to the open state, there is a problem that the time (pull-down time) until the input of the inverter (101) is completely grounded is long.

If the resistance value of the pull-down resistor (103) is set to a small value, the pull-down time can be shortened, but on the other hand, there is a problem that the current consumption of the resistor (103) becomes large. On the other hand, if the resistance value of the pull-down resistor (103) is set to a large value, the current consumption of the pull-down resistor (103) can be reduced, but there is a problem that the pull-down time becomes longer. However, if the pull-down time is prolonged, the floating time is prolonged, so that a through current flows through the inverter (1), which causes a new problem of increasing the consumption current. Neither case leads to a fundamental solution.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit that can reduce the current consumption of a resistor and shorten the time required for pull-up or pull-down.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an input terminal, an inverter connected to the input terminal, and a connection point between the input terminal and the inverter. And a resistor that is connected to the input terminal and pulls up or pulls down the input side of the inverter when the input terminal is floating, wherein a diode element connected in series with the resistor and an input electrode are connected to the inverter. A transistor element connected to an input side, an output electrode connected to a power supply that pulls up or down the input side of the inverter, and a control electrode connected to an output side of the inverter, wherein the input terminal has a predetermined potential. When released from the state fixed to
The voltage of the input terminal changes in the direction of the power supply in accordance with the value of the resistor on one side of the threshold voltage of the inverter, and changes in the direction of the transistor element on the other side of the threshold voltage of the inverter. It is characterized by a sharp change to the value of the power supply.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a circuit diagram showing an input portion of an integrated circuit according to the present invention. FIG. 1 shows the case of pull-down.

In FIG. 1, an inverter (1) has a threshold voltage Vdd / 2 and an input is an input terminal (2).
Connected to One end of the pull-down resistor (3) is connected to the input of the inverter (1). The N-type MOS transistor (4) is connected between the other end of the pull-down resistor (3) and ground with the gate and the drain short-circuited. Note that N
The type MOS transistor (4) corresponds to the diode element of the first aspect. The gate of the N-type MOS transistor (5) is connected to the output of the inverter (1), the drain is connected to the input of the inverter (1), and the source is grounded.
Incidentally, the N-type MOS transistor (5) corresponds to the transistor element of the first aspect. The input terminal (2) is externally connected to a switch (not shown) for supplying the power supply Vdd.

When the switch is open, the input of the inverter (1) is a pull-down resistor (3) and an N-type MO.
Grounded via the S transistor (4), the output of the inverter (1) is supplied to the internal circuit of the integrated circuit while being fixed at a high level. Next, when the switch is closed, the input of the inverter (1) is connected to the power supply Vdd via the switch, and the output of the inverter (1) is supplied to the internal circuit of the integrated circuit while being fixed at a low level. Is done. Thereafter, in a transition period when the switch is closed, the input voltage of the inverter (1) falls according to a time constant determined by the resistance value of the pull-down resistor (3) and the wiring capacitance, and the output of the inverter (1) has a threshold voltage of the input voltage. Vdd
When the voltage falls below / 2, it is fixed to the high level and supplied to the internal circuit of the integrated circuit. At the same time, the N-type MOS transistor (5) receives the high level output of the inverter (1) and turns on, and the input of the inverter (1) is forcibly grounded via the N-type MOS transistor (5). FIG. 2 is a characteristic diagram showing a transitional state in which the switch is closed.
Note that the solid line represents the characteristic of FIG. 1 and the broken line represents the characteristic of FIG. As described above, when the voltage at the input terminal (2) falls below the threshold voltage Vdd / 2 of the inverter (1), it is forcibly grounded. Therefore, the through current of the inverter (1) can be prevented with the reduction of the floating time, and the current consumption can be reduced.

Since the voltage across the pull-down resistor (3) is subtracted by the voltage based on the ON resistance of the N-type MOS transistor (4), the current consumption of the pull-down resistor (3) can be reduced. The operation and effect are obtained.

[0014]

According to the present invention, the input of the inverter is forcibly connected to the power supply when the voltage of the input terminal changes to the threshold voltage of the inverter. Therefore, the through current of the inverter can be prevented with the reduction of the floating time, and the current consumption can be reduced. Further, since the voltage across the pull-up or pull-down resistor is subtracted by the voltage based on the ON resistance of the diode element, advantages such as reduction in current consumption of the resistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an input portion of an integrated circuit according to the present invention.

FIG. 2 is a characteristic diagram illustrating a transition period when a switch is in an open state.

FIG. 3 is a circuit diagram showing an input portion of a conventional integrated circuit.

[Explanation of symbols]

 (1) Inverter (2) Input terminal (3) Pull-down resistor (4) (5) N-type MOS transistor

Claims (2)

[Claims] 1. An input terminal, an inverter connected to the input terminal, and a connection point between the input terminal and the inverter, wherein an input side of the inverter when the input terminal is floating is pulled up or An integrated circuit having a resistor to pull down, a diode element connected in series with the resistor, an input electrode connected to the input side of the inverter, and an output electrode connected to a power supply to pull up or pull down the input side of the inverter. Wherein the control electrode comprises a transistor element connected to the output side of the inverter, and when the input terminal is released from a state in which the input terminal is fixed at a predetermined potential, the voltage of the input terminal is a threshold voltage of the inverter. On one side, the direction of the power supply changes in accordance with the value of the resistance, An integrated circuit according to claim 1, wherein the other side of the threshold voltage changes sharply to the value of the power supply as the transistor element is turned on. 2. The integrated circuit according to claim 1, wherein said diode element and said transistor element are MOS transistors.