JPH0697802A - Input circuit using mos transistor of integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption and not to prevent the improvement of the degree of integration. CONSTITUTION:An input circuit consists of an NMOS, i.e., an NM.1 where a gate is directly connected to an input point IN together with the source connected directly to the ground GND and the drain connected directly to an output point OUT respectively and a PMOS, i.e., a PM.1 where the source and the drain are directly connected to a voltage power supply Vss and the point OUT respectively. In this input circuit, a reference PMOS, i.e., PM.R and a constant current source CC are provided and the source of a reference PMOS, i.e., a PM.J is directly connected to the Vss together with the gate and the drain connected directly to a reference direct connection point G, the point G connected directly to the gate of the PM.1 and to one of both ends of the CC, and the other end of the CC connected directly to the GND respectively. Furthermore a semiconductor active element SA and a conductive state holding circuit ON are added and put between the source of the NM.1 and the GND and between the SA and the Vss respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit using MOS transistors of an integrated circuit. In recent years, demand for portable products such as laptop computers and cordless phones has been increasing, but on the other hand, sales competition is fierce, and long-term use of portable products is desired.

Therefore, it is essential to reduce the power consumption of the input circuit at the first stage among the integrated circuits that consume the built-in battery.

[0003]

2. Description of the Related Art The prior art will be described below. FIG. 8 shows an example of an input circuit using MOS transistors of an integrated circuit according to the related art.

In the figure, V _SS is a voltage source, GND is a ground, IN is an input point, OUT is an output point, and PM is a P-channel MOS transistor (hereinafter abbreviated as PMOS).
And NM is an N-channel MOS transistor (hereinafter referred to as NM
Abbreviated as OS. ).

As shown in the figure, the PMOS and the NMOS are paired to form a one-stage circuit, but of course, the number of stages may be two or more. Now, from the input point IN to a high logic level (hereinafter abbreviated as "H"),
Alternatively, when a signal of a low logic level (hereinafter abbreviated as “L”) is applied, this signal is inverted, and from the output point OUT,
Signals of "L" or "H" are transmitted respectively. That is, it logically functions as an inverter.

In a two-stage circuit, this is further inverted, so that what is transmitted is an amplified output signal having the same logic level as the input signal. That is, when the number of stages is an odd number, it becomes an amplification inverter, and when it is even, it becomes a simple amplification circuit.

In the input circuit shown in FIG. 8, there is relatively no problem when the amplitude of the input signal changes at the full dynamic range (operating range) and at high speed, but when the change width is small or changes at low speed. A large current flows through this, which is a big problem.

This large current is called a through current and reaches several hundred μA. The reason for this will be described below. Figure 9
It is a 1st time chart which shows the time change of signal amplitude.

In the figure, V _DYN on the amplitude V axis shows the maximum value of the dynamic range, the waveform of the broken line shows the signal whose amplitude changes to the full dynamic range, and the waveform of the solid line shows the change width of the amplitude. Shows a small signal. V _DYN
Is 5 V, and an example of a signal with a small amplitude change width is 0.8 V for a dynamic range of 0 V to 5 V.
It is V-2.5V.

In the actual circuit of FIG. 8, there is an input voltage range in which PM and NM are in a conductive state (hereinafter referred to as ON) at the same time. This is the range between the dotted line V _L and the dotted line V _{H in} FIG. 9, that is, the range of V _L <V <V _H , which is the cause of the through current. Illustrative examples of V _L and V _H are 1.5V and 3.5V, respectively.

On the time t axis, a through-current flows with a broken line signal of Δt _a1 + Δt _a2 for an extremely short time, so that there is almost no problem, but with a solid line signal, it flows for a long time like Δt _a. It becomes a big problem.

Next, FIG. 10 is a second time chart showing a temporal change in signal amplitude. In the figure, V _DYN , V
_{The L} , V _H, etc. are the same as in FIG. 9, and the waveform of the broken line shows a signal with a high change rate, and the waveform of the solid line shows a signal with a low change rate.

The shoot-through current is Δt _b1 + Δt in the signal of the broken line.
There is almost no problem because _b4 flows for an extremely short time, but in the signal of the solid line, Δt _b2 + Δt _b3 (>> Δt _b1 + Δt
Since it flows for a long time like _b4 ), it becomes a big problem in terms of power consumption.

The through current not only increases the power consumption, but also causes a pulsating voltage drop in the power supply wiring and the ground wiring, which causes noise. FIG. 11 shows a conventional input circuit devised to reduce the above-mentioned harmful shoot-through current.

In the figure, both R ₁ and R ₂ are several hundreds kΩ.
Resistance, and other than that is exactly the same as in FIG. By inserting these high resistances R ₁ and R ₂ , the through current can be suppressed for the time being.

[0016]

However, the insertion of the high resistance as described above not only lowers the power efficiency of the entire circuit, but also increases the chip area dimensionally.
There is a difficulty that hinders the improvement of the degree of integration.

Therefore, an object of the present invention is to provide an input circuit using MOS transistors of an integrated circuit which saves power consumption and does not hinder the improvement of the integration degree, except for the above-mentioned drawbacks of the prior art. In point.

[0018]

FIG. 1 is a circuit diagram showing the principle of the present invention. In the figure, V _SS is a voltage source, GND
Is ground, and PM.1, NM.1 and D.1 are the first
These are the PMOS, NMOS and the single stage output points of the first stage, respectively. Also, PM / J-1, NM / J-1
And DJ-1 are the PMOs of the J-1th stage.
PM at the output point of the S, NMOS and J-1 stage
J, NM · J, and D · J, that is, OUT, are the output points of the PMOS, NMOS, and Jth stage, respectively, that is, the output points of the entire circuit.

SA is a semiconductor active element having CS as a carrier receiving electrode, BG as a carrier control electrode, and ED as a carrier supply source electrode, and ON holds the semiconductor active element (SA) in a conductive state. Which is used in claim 2 but is not used in claim 1, and is directly connected between the source of the NM.1 and the ground.

In order to achieve the above-mentioned object, the present invention has the following constitution as shown in FIG. That is, claim 1
Then, the gate is directly connected to the input point IN and the source is the ground GN.
Single-stage output point D.1 directly connected to D. N-channel MOS transistor NM.1 directly connected to OUT, and source directly connected to voltage source V _SS and drain connected to the single-stage output point D.
An input circuit using a MOS transistor of a single-stage integrated circuit formed by a pair of a P-channel MOS transistor PM-1 directly connected to 1 → OUT, or a gate in the first-stage input circuit of the single-stage integrated circuit. -1 stage output point D
The source of the voltage source V _SS is connected to J-1 and the source is directly connected to the ground GND and the drain is directly connected to the output point DJ → OUT of the Jth stage A plurality of JP channels M, which are directly connected to each other and whose drains are directly connected to the output points D and J of the Jth stage of the self stage.
MO of a multi-stage J-stage integrated circuit to which a plurality of J-th integrated circuits, each of which is composed of a pair of OS transistors PM and J, is added
The input circuit using the S transistor includes a reference P-channel MOS transistor PM.R and a constant current source CC, and the reference P-channel MOS transistor PM.J is provided.
Is directly connected to the voltage source V _SS , and its gate and drain are directly connected at a reference direct connection point G, and the reference direct connection point G is connected to the first P-channel MOS transistor P.
The gate of M.1 or all of the gates of the plurality of J P-channel MOS transistors PM.1 to PM.J and one end of the constant current source CC are directly connected at the same time, and the other end of the constant current source CC is connected. Is directly connected to ground GND.

According to a second aspect of the present invention, the MO of the above integrated circuit is provided.
The input circuit using an S transistor includes a semiconductor active element SA and a conduction state holding circuit ON,
The direct connection between the source of the N-channel MOS transistor NM.1 of the first stage and the ground GND is cut, and instead of this, the N-channel MOS transistor NM.1 of the first stage is disconnected.
Between the voltage source V _SS and the semiconductor active element SA by directly connecting the carrier receiving electrode CS of the semiconductor active element SA and the carrier control electrode BG to the source at the same time, and directly connecting the carrier supply source electrode ED to the ground. The conductive state holding circuit ON is connected to and the conductive state of the semiconductor active element SA is held.

[0022]

In FIG. 1, which shows the basic circuit configuration of the present invention,
A reference PMOS or PM.R and a constant current source CC are provided, and the source of the reference PMOS or PM.R is directly connected to the voltage source V _SS , and its gate and drain are directly connected at the reference direct connection point G. A circuit configuration in which the reference direct connection point G is directly connected to the first-stage PMOS, that is, the gate of PM.1 and one end of the constant current source CC at the same time, and the other end of the constant current source CC is directly connected to the ground GND, Clearly reference PMOS
That is, it is the configuration itself of the current mirror circuit in which PM.R and the constant current source CC are used as reference circuits, and the first PMOS, that is, PM.1 is used as the mirror current circuit.

As is known, the first of the mirror current circuits
The PMOS of the stage, that is, the gate of PM.1 and the gate of the reference PMOS, that is, the gate of PM.R and the drain of the reference circuit are directly connected at the reference direct connection point G, and although this connection is simple, it is important for the current mirror circuit. That's the point.

The current mirror circuit is a high-performance constant current circuit, and the first stage PMOS of the mirror current circuit, that is, P
The drain current I _{PM · 1} of M · 1 is exactly equal to the current of the reference circuit, that is, the current I _CC of the constant current circuit, or equal to a constant multiple thereof.

Therefore, if the constant current I _{CC is set} to an extremely small value, 1 μA as an example, a signal with a small amplitude change width or a signal with a low change speed is avoided from the viewpoint of the conventional through current. Even if the incoming signal is applied, as a matter of course, a current of 1 μA or more does not flow, as a matter of course, a through current, which is extremely effective in reducing consumption current and preventing noise.

The above-mentioned effect is that the reference direct connection point (G) has all the gates of a plurality of J PMOSs, that is, PM.1 to PM.J including the first PMOS, that is, PM.1, and the constant current. The same applies when the power source CC is directly connected to one end at the same time and the other end of the constant current source CC is directly connected to the ground (GND).

That is, if the constant current I _CC is selected to be an extremely small value, 1 μA as an example, even if a signal which is conventionally avoided from the viewpoint of the through current is applied as described above, The current of 1 μA or more does not flow as the sum of all drain currents of a plurality of J PMOSs, that is, PM · 1 to PM · J.

Further, in the case of the circuit composed of a plurality of J PMOSs of PM · 1 to PM · J, since an amplifier circuit of a plurality of J stages is formed, the temporal change rate of the signal amplitude is increased every time the stages are followed. A sharp increase, that is, Δt _b in FIG. 10 is sharply decreased, and it is possible to further reduce the consumption current and prevent noise.

Next, in claim 2, the semiconductor active element SA
And a conductive state holding circuit ON, and disconnects the direct connection between the source of the first-stage NMOS, that is, the source of NM.1 and the ground GND, and replaces it with the first-stage NMO.
The semiconductor active element SA is connected to the source of S, that is, NM.
Of the carrier receiving electrode CS and the carrier control electrode BG are directly connected to each other, and the carrier supply source electrode ED is directly connected to the ground to connect the conduction state holding circuit ON between the voltage source V _SS and the semiconductor active element SA. The semiconductor active element SA is connected to hold the conductive state.

In general, a semiconductor active device is provided with at least three kinds of electrodes defined here. The first is a carrier supply source electrode serving as a supply source of carriers (indicating an electrically conductive carrier such as electrons and holes), which corresponds to, for example, an emitter of a transistor or a source of an FET. The second is a carrier receiving / receiving electrode which is a receiving / receiving carrier, and corresponds to, for example, a collector of a transistor or a drain of an FET. The third is a carrier control electrode that controls the amount of carriers transmitted, and corresponds to, for example, the base of a transistor or the gate of an FET.

According to the above-mentioned connection, as long as the semiconductor active element SA is held in the conductive state, V _BG is always provided between the source of the first-stage NMOS, that is, NM · 1, and the ground. _-ED voltage is inserted. An example of V _BG-ED is about 0.7V.

Conventionally, this portion was short-circuited, so V
_BG-ED = 0V, and the first stage NMOS, that is, N
Potential difference V _GS between gate and source when M · 1 is conducting
Was V _GS ≈0.7V, the threshold of NM · 1 was about 0.7V.

However, according to the circuit configuration of the present invention, NM
The threshold of 1 is 0.7V + 0.7V ≒ 1.4V
And double. Therefore, the gate voltage for turning on the NM.1 increases. As a result, the threshold value becomes equal to the threshold value of a general logic level (TTL compatible), and the effect of facilitating the interface with another logic IC is obtained.

[0034]

EXAMPLES Examples of the present invention will be listed below. FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a reference PMO is provided in a single stage input circuit composed of a pair of PM.S and NM.S as shown.
S, that is, PM.R and a constant current source CC are added to form a current mirror circuit.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, as shown, PM.S and N
In the two-stage input circuit consisting of a pair of M · S and a pair of PM · W and NM · W, a reference PMOS, PM ·
A current mirror circuit is formed by adding R and a constant current source CC.

According to this embodiment, since the two-stage amplifier circuit is formed, the temporal change rate of the signal amplitude of the second stage becomes high, and it is effective to reduce the consumption current and prevent the noise. , [Action] as described above.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. In the present embodiment of claim 2, the NMO of the first stage
S, that is, as a conductive state holding circuit of the semiconductor active element SA for increasing the threshold of NM · 1, its gate is connected to the current mirror circuit, and its source is the voltage source V
_{For SS} , a PMOS for maintaining a conductive state, that is, PM.ON, whose drain is connected to the carrier receiving electrode CS of the semiconductor active element SA and the carrier control electrode BG, is used.

A mirror current is always drawn into the drain of PM.ON, and therefore PM.ON is also active in the semiconductor active element S.
Since A is also always conducting, the threshold of NM.1 is raised to a preferred value of about 1.4V as an example.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention. In this embodiment, as shown in the figure, a transistor Q is used as the semiconductor active element SA.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention. In this embodiment, as shown in the figure, another NMOS, that is, NM · SA, is used as the semiconductor active element SA.
Is used.

FIG. 7 is a circuit diagram showing a sixth embodiment of the present invention. This embodiment is the same as the second embodiment shown in FIG.
This is a circuit that is used in combination with the fifth embodiment shown in FIG. That is, by having the two-stage amplifier circuit and the NMOS for increasing the threshold of NM · S, that is, NM · S together, the maximum effect is exerted in the reduction of current consumption and the prevention of noise.

[0043]

As described above, according to the present invention, the power consumption is reduced, the noise due to the through current is also reduced, and the resistance element has a circuit configuration in which only MOS transistor elements are connected. Since the one that requires a large volume when manufactured by the semiconductor manufacturing technology is not used, the MO of the integrated circuit that does not hinder the improvement of the integration degree is used.
An input circuit with S transistors can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 8 is an example of an input circuit using MOS transistors of a conventional integrated circuit.

FIG. 9 is a first time chart showing a temporal change in signal amplitude.

FIG. 10 is a second time chart showing a temporal change in signal amplitude.

FIG. 11 is an example of a conventional input circuit for suppressing a shoot-through current.

[Explanation of symbols]

V _SS Voltage source GND Ground PM · 1 1st stage PMOS NM · 1 1st stage NMOS D · 1 1st stage single stage output point PM · J-1 J−1 stage PMOS NM・ J-1 J-1th stage NMOS D ・ J-1 J-1st stage output point PM ・ J Jth stage PMOS NM ・ J Jth stage PMOS DJ (OUT) Output point of the Jth stage, that is, output point of all circuits SA semiconductor active element ON conductive state holding circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0185

Claims (2)

[Claims] 1. An N-channel MOS transistor (NM.1) having a gate directly connected to an input point (IN), a source directly connected to ground (GND), and a drain directly connected to a single stage output point (D.1.fwdarw.OUT). , A single-stage integrated circuit in which a source is directly connected to a voltage source (V _SS ) and a drain is directly connected to the single-stage output point (D · 1 → OUT) and a P-channel MOS transistor (PM · 1) is paired. Of the input circuit of the MOS transistor of the first stage, or the input circuit of the single stage of the first stage, the output point (DJ-
1), the source is directly connected to the ground (GND), and the drain is directly connected to the output point (DJ → OUT) of its own stage (the Jth stage). J) and a source thereof are directly connected to a voltage source (V _SS ) and a drain thereof is directly connected to the output point (D · J) of the self-stage (the J-th stage), and a plurality of (J-th) P-channel MOS transistors (PM) In an input circuit using MOS transistors of a multi-stage (J-stage) integrated circuit to which a plurality of (J-th) integrated circuits formed by pairing with J) are added, a reference P-channel MOS transistor (PM / R) and , A constant current source (CC), the source of the reference P-channel MOS transistor (PM · R) is directly connected to the voltage source (V _SS ) and its gate and drain are connected at a reference direct connection point (G). Direct connection, see above The node (G) is connected to the gate of the first P-channel MOS transistor (PM.1) or all the gates of the plurality (J) of P-channel MOS transistors (PM.1 to PM.J). The constant current source (CC)
An input circuit using a MOS transistor of an integrated circuit, which is directly connected to one end of the constant current source and the other end of the constant current source (CC) is directly connected to a ground (GND). 2. The input circuit using MOS transistors of the integrated circuit according to claim 1, further comprising a semiconductor active element (SA) and a conduction state holding circuit (ON), wherein the first-stage N-channel MOS is provided. Transistor (NM ・
The direct connection between the source of 1) and the ground (GND) is disconnected, and instead of this, the source of the first-stage N-channel MOS transistor (NM · 1) receives the carrier of the semiconductor active element (SA). The destination electrode (CS) and the carrier control electrode (BG) are directly connected at the same time, the carrier supply source electrode (ED) is directly connected to the ground, and the voltage is supplied between the voltage source (V _SS ) and the semiconductor active element (SA). An input circuit using a MOS transistor of an integrated circuit, characterized in that the conductive state holding circuit (ON) is connected to hold the conductive state of the semiconductor active element (SA).