JP3515941B2 - Differential amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit having a transistor pair in which the potential of a common emitter is held by a constant current source, and more particularly to a voltage fluctuation or surge voltage of an input / output terminal which is a base of each transistor. The present invention relates to a differential amplifier circuit that prevents a latch-up phenomenon caused by the.

[0002]

2. Description of the Related Art A semiconductor device that changes a high-impedance state of a semiconductor circuit to a low-impedance state and a buffer circuit using a differential amplifier circuit in the semiconductor circuit are generally used.

A buffer circuit using a conventional differential amplifier circuit will be described below with reference to the drawings.

FIG. 15 shows a conventional buffer circuit, which is shown in FIG.
Reference numeral 6 shows the voltage characteristic of the buffer circuit with respect to the power supply voltage. As shown in FIG. 15, the buffer circuit comprises a first transistor Q ₅₁ and a second transistor Q ₅₂ having a common emitter Q _51E connected to each other. First
Based Q _51B of the transistor Q ₅₁ is connected to the input terminal V _in, the collector Q _51C is connected to the power supply V _CC via the first load circuit 55. The base Q _52B of the second transistor Q ₅₂ is connected to the output terminal V _out,
The collector Q _52C is connected to the first load circuit 55.

The common emitter Q _51E is connected to a second load circuit 56 that receives the power supply voltage V _CC, and is held at a potential higher than the ground potential by a constant current source 57 connected to the second load circuit 56. Has been done.

As shown in FIG. 16, power is supplied to the buffer circuit.
Voltage V_CCSupply the collector Q _51C Voltage of the power
Voltage V_CCIs between 1.2V and 4V.
Source Q_51B There is a region lower than the voltage value of. This
Voltage difference V1 exceeds the threshold voltage (for example, about 0.7V).
Or a sudden surge voltage is applied
When the value voltage is exceeded, the buffer circuit device of FIG.
As shown in the sectional configuration diagram, the input terminal V_inTo collector Q
_51C Current flows to the pseudo transistor (first pseudo
Similar transistor) Q_A To work as. In addition, the first
Langista Q₅₁A second pseudo transistor Q near_B 
Exists, these first pseudo transistor Q_A When
Second pseudo transistor Q_B A closed circuit is formed between
As a result, a latch-up current flows. This latch
If the up current continues to occur, the buffer will eventually
The circuit device will be destroyed.

This latch-up phenomenon is caused by the second pseudo transistor Q _B when the specific resistance of the semiconductor wafer is large.
Is particularly easy to operate, and thus is likely to occur. To avoid this, the input voltage V _in1 shown in FIG. 16 needs to be higher than the voltage of the collector Q _51C . More specifically, the voltage difference between the base Q _51B and the collector Q _{51C of} the first transistor Q ₅₁ needs to be equal to or less than the above threshold voltage.

Therefore, in a conventional buffer circuit using a differential amplifier circuit, since the power supply of the buffer circuit is common to other circuits connected to the input terminal V _{in of the} buffer circuit, for example, A logic circuit or a delay circuit is added to the terminal V _in to change the voltage of the input signal to the desired input voltage V
_The input signal is delayed by bringing it closer to _in1 .

[0009]

However, since the conventional buffer circuit is provided with the logic circuit for signal delay, the number of components of the semiconductor device including the buffer circuit or the peripheral circuit of the semiconductor device is increased. As a result, it is difficult to reduce the size of the device body, and the cost of the device body increases.

Similarly, since the base Q _51B of the first transistor Q ₅₁ and the base Q _{52B of} the second transistor Q ₅₂ of the differential amplifier circuit generate the same potential signal, the output terminal V _51
The same latch-up phenomenon that occurs when power is supplied also to _out . That is, when a surge voltage higher than the voltage of the collector Q _52C by about 0.7 V is applied to the output terminal V _out , a latch-up phenomenon may occur and the semiconductor device may be destroyed.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional problems described above and to prevent the latch-up phenomenon from occurring in the differential amplifier circuit with a simple structure even when the specific resistance of the wafer is large. .

[0012]

In order to achieve the above object, the present invention provides a differential amplifier circuit having a transistor pair having a common emitter, and a collector voltage and a base voltage of at least one of the transistor pair. A circuit is added to prevent the difference between the threshold voltages from exceeding the threshold voltage.

Specifically, the differential amplifier circuit according to the present invention is
A potential of at least one of a first transistor and a second transistor having a common emitter connected to each other and a collector of the first transistor and a collector of the second transistor is set as a voltage value of an input signal or an output signal. And a collector voltage boosting means for boosting the voltage to substantially the same value.

According to the differential amplifier circuit of the present invention, the potential of at least one of the collector of the first transistor and the collector of the second transistor is set to a voltage value substantially equal to the voltage value of the input signal or the output signal. Since the collector voltage boosting means for boosting the voltage is provided, a closed circuit is not formed between the first pseudo transistor Q _A and the second pseudo transistor Q _B as shown in FIG. Can be prevented. Further, since the collector voltage boosting means is provided in the differential amplifier circuit, the semiconductor device including the differential amplifier circuit can be easily downsized.

In the differential amplifier circuit of the present invention, the collector voltage boosting means has a third transistor whose emitter is connected to the base of the first transistor or the second transistor, and a base which is the base of the third transistor. Preferably the connected emitter has a fourth transistor connected to the collector of the first transistor or the second transistor.

In the differential amplifier circuit of the present invention, the collector voltage boosting means has a diode whose cathode is connected to the base of the first transistor or the second transistor, and whose base is connected to the anode of the diode. It preferably has a third transistor connected to the collector of the first transistor or the second transistor.

Further, in the differential amplifier circuit of the present invention, the collector voltage boosting means includes a third transistor whose emitter is connected to the base of the first transistor or the second transistor, and a base whose third transistor is connected. A fourth transistor having a base connected to the emitter of the first transistor and a fourth transistor having an emitter connected to the collector of the first transistor, and a fifth transistor having a base connected to the base of the third transistor and an emitter connected to the collector of the second transistor. It is preferable to have

In the differential amplifier circuit of the present invention, the collector voltage boosting means has a diode whose cathode is connected to the base of the first transistor or the second transistor, and whose base is connected to the anode of the diode. It is preferable to have a third transistor connected to the collector of the first transistor, and a fourth transistor whose base is connected to the anode of the diode and whose miter is connected to the collector of the second transistor. .

Further, in the differential amplifier circuit of the present invention, the collector voltage boosting means has a third transistor, a fourth transistor having an emitter connected to a common emitter and a base and a collector connected in common, and a base having a fourth transistor. It is preferable that the third transistor has a fifth transistor connected to the base and the emitter connected to the collector of the first transistor or the second transistor.

In the differential amplifier circuit according to the present invention, the collector voltage boosting means has a diode whose cathode is connected to the common emitter, and whose base is connected to the anode of the diode and whose emitter is the first transistor or the second transistor. Preferably has a third transistor connected to the collector of.

In the differential amplifier circuit of the present invention, the collector voltage boosting means includes a third transistor, a fourth transistor having an emitter connected to a common emitter and a base and a collector connected in common, and a base having a fourth base. A fifth transistor having a base connected to the base of the third transistor and an emitter connected to the collector of the first transistor; and a fifth transistor having a base connected to the base of the third transistor and an emitter connected to the collector of the second transistor. 6 transistors.

In the differential amplifier circuit of the present invention, the collector voltage boosting means has a diode whose cathode is connected to the common emitter, whose base is connected to the anode of the diode, and whose emitter is connected to the collector of the first transistor. And a fourth transistor whose base is connected to the anode of the diode and whose emitter is connected to the collector of the second transistor.

[0023]

(First Embodiment) First Embodiment of the Present Invention
Embodiments will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the first embodiment of the present invention, and FIG.
Shows the voltage characteristics with respect to the power supply voltage of the buffer circuit according to the present embodiment.

As shown in FIG. 1, the bag according to this embodiment is
The common circuit Q has a common emitter Q which is commonly connected to each other._11E 
A first transistor Q having₁₁And the second Transis
Q ₁₂Is equipped with. In addition, the transaction in this specification
Dista means a bipolar transistor.

The base of the first transistor Q ₁₁ is connected to the input terminal V _in, and the collector Q _11C is connected to the power supply terminal (power supply voltage) via the first load circuit 11 which is a p-type FET.
It is connected to V _CC . The base of the second transistor Q ₁₂ is connected to the output terminal V _out, and the collector Q _12C is connected to the first load circuit 11.

The common emitter Q _11E is connected to the second load circuit 12 composed of an n-type FET and a transistor. The voltage output from the third load circuit 14 including a p-type FET connected to the terminal of the constant current source 13 opposite to the ground terminal is applied to the second load circuit 12.
Thus, the common emitter Q _11E is predetermined voltage higher than the ground potential, i.e., 0 from the voltage V _in of the input terminals.
It is maintained at a voltage as low as about 7V.

A feature of this embodiment is that a collector voltage boosting circuit 20A is provided between the first load circuit 11 and the third load circuit 14.

The collector voltage boosting circuit 20A, the gate receives the output voltage of the third load circuit 14, connected to the p-type FETs Q ₄₀ having a source receiving the supply voltage V _CC, a collector and base and drain of the p-type FETs Q ₄₀ A third transistor Q ₁₃ whose emitter is connected to the base of the first transistor Q ₁₁ , and whose collector receives the power supply voltage V _CC , and whose base is commonly connected to the base of the third transistor Q ₁₃ .
The emitter is constituted by the fourth transistor Q ₁₄ connected to the collector Q _11C of the first transistor Q ₁₁ .

The operation of the buffer circuit configured as described above will be described below.

As shown in FIG. 2, the power supply voltage V_CCSupply
Then, the input terminal V_inVoltage applied to (= input voltage
V_in) Depending on the third transistor Q₁₃Emitter voltage
Rises. As a result, the third transistor Q₁₃The
Source voltage is the base-emitter voltage V _BE(Here, about 0.
7V), so that the third transistor Q₁₃
Fourth transistor Q sharing the base with₁₄The emitter of
The voltage is the base-emitter voltage V_BEThe voltage can be reduced by
Will be Here, the fourth transistor Q₁₄The emitter of
Is the first transistor Q₁₁Collector Q_11C Connected with
Therefore, the first transistor Q₁₁Collector Q_11C 
Voltage of the third transistor Q₁₃Base emitter
Pressure V_BETherefore, the input voltage is increased.
V_inAnd collector Q_11C Voltage difference V2 with the voltage of
Becomes

As described above, according to this embodiment, since the collector voltage boosting means is provided inside the buffer circuit,
Collector Q without hindering miniaturization of semiconductor device
It is possible to eliminate the power supply voltage region in which the voltage of _11C becomes lower than the input voltage V _in (base voltage of the first transistor Q ₁₁ ) and prevent the first transistor Q ₁₁ from causing the latch-up phenomenon. In addition, as shown in FIG.
In the region where the power supply voltage V _CC exceeds 4V, the same voltage characteristic as that of the conventional buffer circuit is exhibited.

In the present embodiment, the value of the base-emitter voltage V _BE of the third transistor Q ₁₃ and the fourth transistor Q ₁₄ is set to 0.7 V, but this is only an example, and the value of the collector Q _11C is equal to that of the collector Q _11C . The base-emitter voltage V _BE value may be such that the voltage difference V2 from the input voltage V _in does not exceed a predetermined threshold voltage.

Although the emitter of the third transistor Q ₁₃ is connected to the input terminal V _in , it may be connected to the output terminal V _out (base of the second transistor Q ₁₂ ).

(Modification of First Embodiment) A modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment.
In FIG. 3, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 20 according to this modification
B is characterized in that the emitter of the fourth transistor Q ₁₄ is connected not to the collector Q _{11C of} the first transistor Q ₁₁ but to the collector Q _{12C of} the second transistor Q ₁₂ . Even in this case, the voltage characteristic shows the same characteristic as in FIG.

According to this modification, since the output terminal V _out is often connected to another circuit as an output terminal of the semiconductor device, an unexpected voltage such as a surge voltage is applied to the output terminal V _out . Even in such a case, collector Q
_Since the voltage difference V2 between the voltage of _{12C and} the voltage output to the output terminal _Vout (= output voltage _Vout ) does not become larger than the predetermined threshold voltage, the latch-up phenomenon can be prevented.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the second embodiment of the present invention. In FIG. 4, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 2 according to the present embodiment
1A includes a p-type FET Q ₄₁ whose gate receives the output voltage of the third load circuit 14 and whose source receives the power supply voltage V _CC ,
An anode is connected to the drain of the p-type FET Q ₄₁ , a cathode is connected to the base of the first transistor Q ₁₁ , a diode D ₁₃ is connected, and a collector is connected to the power supply voltage V _CC , and a base is connected to the anode of the diode D _13. , And the third transistor Q ₁₅ whose emitter is connected to the collector Q _{11C of} the first transistor Q ₁₁ .

As described above, the diode D ₁₃ is connected in series in the forward direction between the input terminal V _in which is the base of the first transistor Q ₁₁ and the p-type FET Q _41, and the voltage of the anode of the diode D ₁₃ is changed. by increasing the order of 0.7V than the input voltage V _in, it is possible to obtain the voltage characteristic similar to that of the first embodiment.

(Modification of Second Embodiment) A modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment.
In FIG. 5, the same components as those shown in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 21 according to this modification
B is characterized in that the emitter of the third transistor Q ₁₅ is connected not to the collector Q _{11C of} the first transistor Q ₁₁ but to the collector Q _{12C of} the second transistor Q ₁₂ . Even in this case, the voltage characteristic shows the same characteristic as in FIG.

According to this modification, a modification of the first embodiment is provided.
Similar to the model, output terminal V_out Against surge voltage, etc.
Even if an unexpected voltage is applied,
Q _12C Voltage and output terminal V_out Output voltage applied to
V_out And the voltage difference V2 between is larger than a predetermined threshold voltage.
Since it does not get worse, it can prevent the occurrence of latch-up phenomenon.
It

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the third embodiment of the present invention. 6, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 2 according to the present embodiment
2A includes a p-type FET Q ₄₀ whose gate receives the output voltage of the third load circuit 14 and whose source receives the power supply voltage V _CC ;
A third transistor Q ₁₆ whose collector and base are connected to the drain of the p-type FET Q _40, whose emitter is connected to the base of the first transistor Q ₁₁ , and whose collector receives the power supply voltage V _{CC and} whose base is the third The emitter of the first transistor Q ₁₁ is commonly connected to the base of the transistor Q _16.
A fourth transistor Q ₁₇ connected to the collector Q _{11C of the}
And a fifth transistor Q ₁₈ whose collector receives the power supply voltage V _CC , whose base is commonly connected to the base of the third transistor Q ₁₆ , and whose emitter is connected to the collector Q _{12C of} the second transistor Q _12. It is configured.

Thus, the emitter is the first transistor
Q₁₁Collector Q_11C 4th Transis connected with
Q₁₇And the emitter is the second transistor Q₁₂Collect
Q _12C A fifth transistor Q connected to₁₈Is that
The base of each is the third transistor Q₁₆Together with the base of
Since it is connected through, collector Q_11C And collector Q
_12C Are both the third transistor Q₁₆Base emitter
Voltage V_BEThe minute voltage rises. Therefore, the first transition
Star Q₁₁Collector Q in_11C Is the input terminal V_in
Latch-up phenomenon occurs compared to the voltage applied to
It will not drop as much. Similarly, the second transition
Star Q₁₂Collector Q in_12C Voltage of output terminal V
_out Latch-up phenomenon occurs compared to the voltage applied to
It does not fall to the point where it twists.

(Modification of Third Embodiment) A modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment.
In FIG. 7, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 22 according to this modification
In B, the gate receives the output voltage of the third load circuit 14,
Source is power supply voltage V_CCP-type FET Q receiving₄₁And Ano
P-type FET Q₄₁Connected to the drain of the cathode
Is the first transistor Q₁₁Dio connected with the base of
Mode D₁₃And the collector is the power supply voltage V_CCReceived the base
Diode D₁₃Connected to the anode of the
Transistor Q₁₁Collector Q_11C Third connected with
Transistor Q₁₉And the collector is the power supply voltage V _CCReceived
K, the base is the third transistor Q₁₉Base and common connection
And the emitter is the second transistor Q.₁₂Collector of
Q_12C A fourth transistor Q connected with ₂₀Depending on
Is made.

As described above, the diode D ₁₃ is connected in series in the forward direction between the input terminal V _in which is the base of the first transistor Q ₁₁ and the p-type FET Q _41, and the voltage of the anode of the diode D ₁₃ is changed. Increase to about 0.7V. This allows
A voltage difference V2 between the collector Q _11C voltage and the input voltage V _in ,
Also, the voltage difference V2 between the voltage of the collector Q _12C and the output voltage V _out is such that the latch-up phenomenon does not occur.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the fourth embodiment of the present invention. In FIG. 8, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 2 according to the present embodiment
3A includes a p-type FET Q ₄₀ whose gate receives the output voltage of the third load circuit 14 and whose source receives the power supply voltage V _CC ,
A third transistor Q ₂₁ whose collector and base are connected to the drain of the p-type FET Q ₄₀ , and a fourth transistor whose collector and base are connected to the emitter of the third transistor Q _{21 and} whose emitter is connected to the common emitter Q _11E . Transistor Q ₂₂ and the collector thereof receive the power supply voltage V _CC , the base thereof is commonly connected to the base of the third transistor Q ₂₁ , and the emitter thereof is connected to the collector Q _{11C of} the first transistor Q _11. Q ₂₃ and.

The operation of the buffer circuit configured as described above will be described below.

Power supply voltage V_CCSupply the common emitter
Q_11E Is the input voltage V_inDepending on the first transition
Star Q₁₁Base-emitter voltage V_BEIt only drops by a minute. Reverse
And the fourth transistor Q_{twenty two}The base voltage of the
Langista Q_{twenty two}Base-emitter voltage V_BERise by minutes
Therefore, the third transistor Q_{twenty one}The emitter voltage of
1 transistor Q₁₁Base voltage of input voltage
V_inIs almost equal to. As a result, the third transistor
Q_{twenty one}Fifth transistor Q sharing the base with _{twenty three}Emi
The output voltage of the third transistor Q_{twenty one}The emitter of
Since it is almost equal to the pressure, the voltage characteristic curve shown in Fig. 2
Sea urchin fifth transistor Q_{twenty three}The emitter voltage of the first
Transistor Q₁₁Collector Q_11C Is the input voltage
Pressure V_inIs almost equal to.

For example, in the first embodiment, the first
The input voltage of the third transistor Q ₁₃ and the fourth transistor Q ₁₄ sharing the base with each other is substantially equal to each other with reference to the base voltage (input voltage V _in ) of the transistor Q ₁₁ of FIG. V _in and the collector Q _11C
The voltage difference V2 from the voltage is suppressed below the threshold voltage.

On the other hand, in this embodiment, since the voltage of the common emitter Q _11E is used as a reference, the base is shared with each other by interposing the fourth transistor Q ₂₂ . Third transistor Q ₂₁
And using the respective emitter voltages of the fifth transistor Q ₂₃ , the voltage difference V _in between the input voltage Vin and the voltage of the collector Q _11C.
2 is made smaller than the threshold voltage.

As described above, also in the present embodiment, the power supply voltage region _in which the difference V2 between the voltage of the collector Q _11C and the input voltage V _in becomes larger than the threshold voltage without hindering the miniaturization of the semiconductor device is set. Since it can be eliminated, the first transistor Q ₁₁ can be prevented from causing the latch-up phenomenon.

(Modification of Fourth Embodiment) A modification of the fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 9 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment.
Here, in FIG. 9, the same components as those shown in FIG. 8 are designated by the same reference numerals, and a description thereof will be omitted.

Collector voltage boosting circuit 23 according to this modification
B is characterized in that the emitter of the fifth transistor Q ₂₃ is connected not to the collector Q _{11C of} the first transistor Q ₁₁ but to the collector Q _{12C of} the second transistor Q ₁₂ . Even in this case, the voltage characteristic shows the same characteristic as in FIG.

According to this modification, the output terminal V _out is often connected to another circuit as an output terminal of the semiconductor device. Therefore, when a surge voltage or the like is applied to the output terminal V _out . However, since the voltage difference V2 between the voltage of the collector Q _12C and the output voltage V _out does not become larger than the threshold voltage, the latch-up phenomenon hardly occurs.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 10 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the fifth embodiment of the present invention. In FIG. 10, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 2 according to the present embodiment
4A includes a p-type FET Q ₄₁ whose gate receives the output voltage of the third load circuit 14 and whose source receives the power supply voltage V _CC ,
A first diode D ₁₃ and a second diode D ₁₄ connected in series in the forward direction between the drain of the p-type FET Q ₄₁ and the common emitter Q _11E , a collector receives the power supply voltage V _CC , and a base receives 1 is connected to the anode of the diode D ₁₃ , and the emitter is the collector Q of the first transistor Q ₁₁ .
It is composed of a third transistor Q ₂₄ connected to _11C .

Thus, the common emitter Q _11E and the p-type F
By connecting the first diode D ₁₃ and the second diode D ₁₄ in series in the forward direction between the ETQ ₄₁ and the ETQ _41, and increasing the anode voltage of the first diode D ₁₃ by about 1.4V, It is possible to obtain the same voltage characteristic as that of the embodiment.

In this embodiment, the two diodes are connected in series, but the first transistor Q is used.
_{As long as} the voltage of the collector Q _11C of ₁₁ is almost equal to the input voltage V _in , in other words, the number of diodes that can boost the base voltage of the third transistor Q _{24 to} a voltage at which the latch-up phenomenon does not occur, Not limited.

(Modification of Fifth Embodiment) A modification of the fifth embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment. In FIG. 11, the same components as those shown in FIG. 10 are designated by the same reference numerals and the description thereof will be omitted.

A collector voltage booster circuit 24 according to this modification.
B is characterized in that the emitter of the third transistor Q ₂₄ is connected not to the collector Q _{11C of} the first transistor Q ₁₁ but to the collector Q _{12C of} the second transistor Q ₁₂ . Even in this case, the voltage characteristic shows the same characteristic as in FIG.

(Sixth Embodiment) A sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 12 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to the sixth embodiment of the present invention. In FIG. 12, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 2 according to the present embodiment
5A, the gate receives the output voltage of the third load circuit 14.
The source is the power supply voltage V_CCP-type FET Q receiving₄₀When,
Collector and base are p-type FETQ₄₀Connected to the drain of
Third transistor Q_{twenty five}And collector and base
Is the third transistor Q_{twenty five}Connected with the emitter of
Common emitter Q_11E 4th transition connected with
Star Q₂₆And the collector is the power supply voltage V_CCReceived the base
Third transistor Q_{twenty five}Emi is commonly connected to the base of
Is the first transistor Q₁₁Collector Q_11C Connect with
Fifth transistor Q₂₇And the collector is the supply voltage
V_CCAnd the base is the third transistor Q_{twenty five}Base of
Is commonly connected with the emitter of the second transistor Q₁₂of
Collector Q _12C A sixth transistor Q connected to₂₈When
It is composed by.

As a result, the input terminal V _in or the output terminal V in
_{Even if} a voltage fluctuation such as a surge voltage occurs with respect to _out , the latch-up phenomenon hardly occurs.

(Modification of Sixth Embodiment) A modification of the sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 13 shows a circuit configuration of a buffer circuit using a differential amplifier circuit according to a modification of this embodiment. In FIG. 13, the same components as those shown in FIG. 12 are designated by the same reference numerals and the description thereof will be omitted.

Collector voltage boosting circuit 25 according to this modification
In B, the gate receives the output voltage of the third load circuit 14,
A p-type FET Q ₄₁ whose source receives the power supply voltage V _CC ,
The first diode D ₁₃ and the second diode connected in series in the forward direction between the drain of the FET Q ₄₁ and the common emitter Q _11E .
The diode D ₁₄ and the collector receive the power supply voltage V _CC ,
The base is connected to the anode of the first diode D ₁₃ ,
A third transistor Q ₂₉ whose emitter is connected to the collector Q _11C of the first transistor Q ₁₁ and a collector which receives the power supply voltage V _CC , whose base is commonly connected to the base of the third transistor Q ₂₉ , and whose emitter is Second transistor Q
Fourth transistor Q connected to ₁₂ collector Q _12C
It is composed of ₃₀ and.

As described above, the common emitter Q _11E and the p-type F
The first diode D ₁₃ and the second diode D ₁₄ are connected in series in the forward direction between the ETQ ₄₁ and the ETQ _41, and the voltage of the anode of the first diode D ₁₃ is increased by about 1.4 V, thereby It is possible to obtain the same voltage characteristic as that of the embodiment.

In this modification, the two diodes are connected in series, but the first transistor Q ₁₁ is used.
Of the collector Q _11C of the second transistor Q ₁₂ is approximately equal to the input voltage V _in , and the collector Q _12C of the second transistor Q ₁₂ is approximately equal to the output voltage V _out , in other words, the third transistor. Any number of diodes can be used as long as they can boost the base voltage of Q _{29 to} a voltage at which latch-up does not occur.

In each embodiment and its modification, the first transistor Q ₁₁ and the second transistor Q _{11 are used} .
The effect of the present invention can be obtained even if a protective base resistor R is provided for ₁₂ . As shown in FIG. 14, taking the buffer circuit according to the first embodiment as an example, between the emitter of the third transistor Q _{13 and} the base of the first transistor Q ₁₁ and between the second transistor Q ₁₂ and the second transistor Q ₁₂ . A base resistor R may be inserted between the base and the output terminal V _out .

A differential amplifier circuit is used instead of the buffer circuit.
When used as, for example, the first embodiment,
Connect the first input terminal and the second input terminal to the firsttransistor.
Q ₁₁And the second transistor Q₁₂Each base and then
1 output terminal of the first transistor Q₁₁Collector Q
_11C And the second output terminal is the output terminal V shown in FIG._out
And it is sufficient.

[0086]

According to the differential amplifier circuit of the present invention, the potential of at least one of the collector of the first transistor and the collector of the second transistor in the first transistor and the second transistor having a common emitter. Is provided with a collector voltage boosting means for boosting the voltage to a voltage value almost equal to the voltage value of the input signal or the output signal, so that the latch-up phenomenon can be prevented without hindering downsizing of the circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing voltage characteristics with respect to a power supply voltage of a buffer circuit using the differential amplifier circuit according to the present invention.

FIG. 3 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a fifth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a sixth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a buffer circuit using a differential amplifier circuit according to a modification of the sixth embodiment of the present invention.

FIG. 14 is a circuit diagram when a base resistor is provided in the differential amplifier circuit according to the first embodiment of the present invention.

FIG. 15 is a circuit diagram showing a buffer circuit using a conventional differential amplifier circuit.

FIG. 16 is a graph showing voltage characteristics with respect to a power supply voltage of a buffer circuit using a conventional differential amplifier circuit.

FIG. 17 is a schematic configuration cross-sectional view of a semiconductor device for explaining a latch-up phenomenon of a buffer circuit using a conventional differential amplifier circuit.

[Explanation of symbols]

11 First Load Circuit 12 Second Load Circuit 13 Constant Current Source 14 Third Load Circuit 20A Collector Voltage Boosting Circuit (Collector Voltage Boosting Means) 20B Collector Voltage Boosting Circuit 21A Collector Voltage Boosting Circuit 21B Collector Voltage Boosting Circuit 22A Collector Voltage booster circuit 22B Collector voltage booster circuit 23A Collector voltage booster circuit 23B Collector voltage booster circuit 24A Collector voltage booster circuit 24B Collector voltage booster circuit 25A Collector voltage booster circuit 25B Collector voltage booster circuit V _in input terminal (input voltage) V _out output terminal (Output voltage) V _CC Power supply terminal (Power supply voltage) Q ₁₁ First transistor Q ₁₂ Second transistor Q _11E Common emitter Q _11C (First transistor) collector Q _12C (Second transistor) collector Q ₄₀ p-type FET Q ₁₃ 3rd transistor Q ₁₄ 4 transistor Q ₄₁ p-type FET D ₁₃ diode (first diode) Q ₁₅ third transistor Q ₁₆ third transistor Q ₁₇ fourth transistor Q ₁₈ fifth transistor Q ₁₉ third transistor Q ₂₀ 4th transistor Q ₂₁ 3rd transistor Q ₂₂ 4th transistor Q ₂₃ 5th transistor D ₁₄ 2nd diode Q ₂₄ 3rd transistor Q ₂₅ 3rd transistor Q ₂₆ 4th transistor Q ₂₇ 5th transistor Transistor Q ₂₈ 6th transistor Q ₂₉ 3rd transistor Q ₃₀ 4th transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03F 3/45

Claims (8)

(57) [Claims] 1. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting the voltage of the collector voltage boosting means, the collector voltage boosting means comprising: a third transistor having an emitter connected to the base of the first transistor or the second transistor; and a base having the third transistor. Connected to the base of
An emitter of the first transistor and the fourth transistor and the differential amplifier circuit characterized by having a connected to the collector of the second transistor. 2. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting with, the collector voltage boosting means, wherein the cathode is connected to the diode of the first transistor or the base of the second transistor, and the base is connected to the anode of the diode, an emitter of the first transistor and the third differential amplifier circuit characterized by having a transistor connected to the collector of the second transistor. 3. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting the voltage of the collector voltage boosting means, the collector voltage boosting means comprising: a third transistor having an emitter connected to the base of the first transistor or the second transistor; and a base having the third transistor. Connected to the base of
A fourth transistor having an emitter connected to the collector of the first transistor, a base connected to the base of the third transistor,
An emitter has a fifth transistor connected to the collector of the second transistor,
Differential amplifier circuit that. 4. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting with, the collector voltage boosting means, wherein the cathode is connected to the diode of the first transistor or the base of the second transistor, and the base is connected to the anode of the diode, A third transistor whose emitter is connected to the collector of the first transistor, and a fourth transistor whose base is connected to the anode of the diode and whose emitter is connected to the collector of the second transistor. differential amplifier circuit you characterized by that. 5. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting the voltage by means of a third transistor, a fourth transistor having an emitter connected to the common emitter, a base and a collector connected in common, and a base having the base described above. Connected to the base of the third transistor,
Differential amplifier circuit you characterized by having a fifth transistor having an emitter connected to the collector of said first transistor or said second transistor. 6. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting the voltage by means of the collector voltage boosting means, wherein the collector voltage boosting means comprises a diode having a cathode connected to the common emitter, a base connected to the anode of the diode, and an emitter connected to the first transistor or the first transistor. differential amplifier circuit you characterized in that a third transistor connected to the collector of the second transistor. 7. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting the voltage by means of a third transistor, a fourth transistor having an emitter connected to the common emitter, a base and a collector connected in common, and a base having the base described above. Connected to the base of the third transistor,
A fifth transistor having an emitter connected to the collector of the first transistor, a base connected to the base of the third transistor,
An emitter having a sixth transistor connected to the collector of said second transistor
Differential amplifier circuit that. 8. Having common emitters connected to each other
A first transistor and a second transistor, a collector of the first transistor and the second transistor,
The potential of at least one of the collectors of the
Make sure that the voltage value is almost the same as the voltage value of the input signal or output signal.
Collector voltage boosting means for boosting with a diode, the cathode of which is connected to the common emitter, the base of which is connected to the anode of the diode, and the emitter of which is the collector of the first transistor. a third transistor connected, the base is connected to the anode of the diode, the difference emitter you characterized by having a fourth transistor connected to the collector of the second transistor dynamic Amplifier circuit.