CN213937839U

CN213937839U - Cascode structure, output structure, amplifier and drive circuit

Info

Publication number: CN213937839U
Application number: CN202022945285.XU
Authority: CN
Inventors: 朱磊
Original assignee: Changxin Storage Technology Shanghai Co ltd
Current assignee: Changxin Storage Technology Shanghai Co ltd
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2021-08-10
Anticipated expiration: 2030-12-07

Abstract

The disclosure provides a cascode structure, an output structure, an amplifier and a driving circuit. The bias voltage of the common-gate structure in the cascode structure is provided by the common-gate structure, the bias voltage of the transistor in the output structure is provided by the common-gate structure, and the cascode structure is provided with a first node, a second node, a third node, a fourth node and a fifth node. The amplifier comprises the cascode structure and/or the output structure, and the driving circuit comprises the amplifier. The amplifying circuit provided by the embodiment of the disclosure can realize voltage amplification without arranging a biasing circuit.

Description

Cascode structure, output structure, amplifier and drive circuit

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a cascode structure, an output structure, an amplifier, and a driving circuit in which a bias voltage is provided by the cascode structure.

Background

An amplifier is generally used in the drive circuit. A common structure of an amplifier includes a differential input stage, an intermediate amplification stage, an output stage, and a bias circuit that provides bias voltages to the differential input stage, the intermediate amplification stage, and the output stage. The bias circuit is an indispensable part in the prior amplifier technology, but the arrangement of the bias circuit can increase the power consumption of the circuit.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure is directed to a cascode structure, an output structure, an amplifier and a driving circuit, which are used to overcome, at least to some extent, the problem of large power consumption of the circuit due to the adoption of a bias circuit.

According to a first aspect of the present disclosure, a cascode structure is provided, a bias voltage of a cascode structure of the cascode structure being provided by itself, the cascode structure having a first node, a second node, a third node, a fourth node, a fifth node.

In an exemplary embodiment of the present disclosure, the common-gate structure of the cascode structure includes: the grid electrode and the drain electrode of the first transistor and the grid electrode of the second transistor are connected with the first node, and the drain electrode of the second transistor is connected with the second node.

In an exemplary embodiment of the present disclosure, the common source structure of the cascode structure includes: the drain of the third transistor is connected with the source of the first transistor, the drain of the fourth transistor is connected with the source of the second transistor, the source of the third transistor and the source of the fourth transistor are both connected with the third node, the gate of the third transistor is connected with the fourth node, and the gate of the fourth transistor is connected with the fifth node.

In one exemplary embodiment of the present disclosure, the first transistor, the second transistor, the third transistor, and the fourth transistor are the same type.

According to a second aspect of the present disclosure, there is provided an amplifier comprising: in the cascode structure, the fourth node and the fifth node in the cascode structure are respectively used as a first input port and a second input port of the amplifier; a current source comprising two ports, a first port of the current source being connected to the third node; and the load structure comprises four ports, a first port of the load structure is connected with the first node, a second port of the load structure is connected with the second node, and the second port of the load structure is used as an output port of the amplifier.

In an exemplary embodiment of the present disclosure, a transistor type of the current source is the same as a transistor type of the cascode structure.

In an exemplary embodiment of the present disclosure, the load structure includes: the grid electrode and the drain electrode of the fifth transistor are both connected with the grid electrode of the sixth transistor, the drain electrode of the fifth transistor serves as a first port of the load structure, the drain electrode of the sixth transistor serves as a second port of the load structure, the source electrode of the fifth transistor serves as a third port of the load structure, and the source electrode of the sixth transistor serves as a fourth port of the load structure.

In an exemplary embodiment of the disclosure, the transistor type in the cascode structure is different from the transistor type of the cascode structure.

In an exemplary embodiment of the disclosure, the second port of the current source is grounded, and the third port and the fourth port of the load structure are both connected to a power supply.

In an exemplary embodiment of the disclosure, the second port of the current source is connected to a power supply, and the third port and the fourth port of the load structure are both connected to ground.

According to a third aspect of the present disclosure, there is provided an output structure, the bias voltages of the transistors in the output structure each being provided by the output structure itself, the output structure comprising a first node, a second node, a sixth node, a seventh node, an eighth node, a ninth node.

In an exemplary embodiment of the present disclosure, the output structure includes: the gate of the first transistor, the gate of the second transistor, the drain of the first transistor, and the drain of the fifth transistor are all connected to the first node, the drain of the second transistor and the drain of the sixth transistor are all connected to the second node, the source of the first transistor is connected to the sixth node, the source of the second transistor is connected to the seventh node, the source of the fifth transistor is connected to the eighth node, the source of the sixth transistor is connected to the ninth node, and the second node is used as an output port of the output structure.

In an exemplary embodiment of the present disclosure, the first transistor and the second transistor are N-type transistors, and the fifth transistor and the sixth transistor are P-type transistors.

According to a fourth aspect of the present disclosure, there is provided an amplifier comprising: an output structure as claimed in any preceding claim, an output port of the output structure acting as an output port of the amplifier; the first input port and the second input port of the input structure are respectively used as a first input port and a second input port of the amplifier; a current source comprising two ports, a first port of the current source being connected to a fifth port of the input structure.

In an exemplary embodiment of the disclosure, the second port of the current source is grounded, the first output port of the input structure is connected to the sixth node, the second output port of the input structure is connected to the seventh node, and the eighth node and the ninth node are both connected to a power supply.

In an exemplary embodiment of the disclosure, the second port of the current source is connected to a power supply, the first output port of the input structure is connected to the eighth node, the second output port of the input structure is connected to the ninth node, and the sixth node and the seventh node are both grounded.

According to a fifth aspect of the present disclosure, there is provided a driving circuit comprising: the first amplifier is the amplifier as described in any one of the above, the first input end is connected with the first reference voltage, and the second input end is connected with the tenth node; a second amplifier, which is an amplifier as described in any one of the above, wherein the first input terminal is connected to a second reference voltage, and the second input terminal is connected to the tenth node; the grid electrode of the first driving transistor is connected with the output end of the first amplifier, the source electrode of the first driving transistor is connected with a power supply, and the drain electrode of the first driving transistor is connected with the tenth node; and the grid electrode of the second driving transistor is connected with the output end of the second amplifier, the source electrode of the second driving transistor is grounded, the drain electrode of the second driving transistor is connected with the tenth node, and the tenth node is used as the output end of the driving circuit.

In an exemplary embodiment of the present disclosure, the first driving transistor is a P-type transistor, and the second driving transistor is an N-type transistor.

In an exemplary embodiment of the present disclosure, the first driving transistor and the second driving transistor are both N-type transistors or both P-type transistors.

In an exemplary embodiment of the present disclosure, the first reference voltage and the second reference voltage are not equal.

In an exemplary embodiment of the present disclosure, the driving circuit further includes: and the reference voltage generating circuit is used for generating the first reference voltage and the second reference voltage, and both the first reference voltage and the second reference voltage can be adjusted.

In an exemplary embodiment of the present disclosure, the first amplifier, the second amplifier, the first driving transistor, and the second driving transistor are all powered by a first power source, and the reference voltage generating circuit is powered by a second power source.

In an exemplary embodiment of the present disclosure, a voltage value of the first power supply is greater than a voltage value of the second power supply.

The embodiment of the disclosure sets the bias voltage of the transistor in the amplifier to be provided by the transistor, and realizes the voltage amplification function without adding an external bias circuit, namely reduces the power consumption of the amplifier.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1A and 1B are schematic structural diagrams of a cascode structure in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an amplifier composed of the cascode structure shown in fig. 1A or 1B.

FIG. 3 is a schematic diagram of a load configuration in one embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a load configuration in another embodiment of the present disclosure.

Fig. 5 is a schematic diagram of an output structure provided by an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of an amplifier to which the output structure shown in fig. 5 is applied.

Fig. 7 is a schematic diagram of one embodiment of the amplifier shown in fig. 6.

Fig. 8 is a schematic diagram of another embodiment of the amplifier shown in fig. 6.

Fig. 9 is a schematic diagram of a driving circuit provided in an embodiment of the present disclosure.

Fig. 10 is a circuit diagram of a first driving transistor and a second driving transistor in an embodiment of the disclosure.

FIG. 11 is a schematic diagram of a driver circuit in one embodiment of the present disclosure.

Fig. 12 is a schematic diagram of a driving circuit in yet another embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Referring to fig. 1A and 1B, the bias voltage of the common-gate structure 11 in the structure 100 is provided by itself, and has a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

In the embodiment shown in fig. 1A and 1B, the structure 100 includes a common-gate structure 11 and a common-source structure 12, wherein the common-gate structure 11 includes a first transistor M1 and a second transistor M2, a gate and a drain of the first transistor M1 and a gate of the second transistor M2 are connected to a first node N1, and a drain of the second transistor M2 is connected to a second node N2. The common-source structure 12 includes a third transistor M3 and a fourth transistor M4, a drain of the third transistor M3 is connected to a source of the first transistor M1, a drain of the fourth transistor M4 is connected to a source of the second transistor M2, a source of the third transistor M3 and a source of the fourth transistor M4 are both connected to a third node N3, a gate of the third transistor M3 is connected to the fourth node N4, and a gate of the fourth transistor M4 is connected to the fifth node N5.

The first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are of the same type, and are all N-type transistors (as shown in fig. 1A) or all P-type transistors (as shown in fig. 1B).

Referring to fig. 2, the amplifier 200 may include:

the cascode structure 100, and a fourth node N4 and a fifth node N5 in the cascode structure 100 are respectively used as a first input port and a second input port of the amplifier 200;

a current source 21 comprising two ports, a first port of the current source 21 being connected to the third node N3;

the load structure 22 includes four ports, a first port of the load structure 22 is connected to the first node N1, a second port of the load structure is connected to the second node N2, and the second port of the load structure 22 serves as an output port of the amplifier 200.

In an exemplary embodiment of the present disclosure, the transistor type of the current source 21 is the same as that of the common source common gate structure 100.

Referring to fig. 3, in an exemplary embodiment of the present disclosure, the load structure 22 may include:

a fifth transistor M5 and a sixth transistor M6, wherein the gate and the drain of the fifth transistor M5 are both connected to the gate of the sixth transistor M6, the drain of the fifth transistor M5 is used as the first port of the load structure 22, the drain of the sixth transistor M6 is used as the second port of the load structure 22, the source of the fifth transistor M5 is used as the third port of the load structure 22, and the source of the sixth transistor M6 is used as the fourth port of the load structure 22.

In the disclosed embodiment, the transistor type of the load structure 22 is different from the transistor type of the common source common gate structure 100.

In the embodiment shown in fig. 3, the second port of the current source 21 is grounded, and the third port and the fourth port of the load structure 22 are both connected to the power source VCC. At this time, the fifth transistor M5 and the sixth transistor M6 in the load structure 22 are both P-type transistors, and the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the cascode structure 100 are all N-type transistors.

In the embodiment 400 shown in fig. 4, the second port of the current source 21 is connected to the power source VCC, and the third port and the fourth port of the load structure 22 are both grounded. At this time, the fifth transistor M5 and the sixth transistor M6 in the load structure 22 are both N-type transistors, and the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 in the cascode structure 100 are all P-type transistors.

In the embodiments shown in fig. 3 and 4, the fourth node N4 and the fifth node N5 of the cascode structure 100 serve as two input ports of the amplifier, and may be connected to the first input voltage Vin1 and the second input voltage Vin2, and the first input voltage Vin1 and the second input voltage Vin2 may be differential mode inputs or common mode inputs. The second node N2 as the amplifier output terminal Vout is the drain of the second transistor M2 connected in common gate, which can achieve a higher voltage gain.

Because the bias voltages of the transistors in the

amplifiers

200, 300 and 400 are all provided by the amplifying circuits, the

amplifiers

200, 300 and 400 can amplify the voltages without arranging the biasing circuits, and have lower power consumption.

Embodiments of the present disclosure also provide an output structure in which the bias voltages of the transistors are all provided by the output structure itself.

Referring to fig. 5, the output structure 500 includes a first node N1, a second node N2, a sixth node N6, a seventh node N7, an eighth node N8, and a ninth node N9.

The output structure 500 includes:

the first transistor M1, the second transistor M2, the fifth transistor M5 and the sixth transistor M6, the gate of the first transistor M1, the gate of the second transistor M2, the drain of the first transistor M1 and the drain of the fifth transistor M5 are all connected to the first node N1, the drain of the second transistor M2 and the drain of the sixth transistor M6 are all connected to the second node N2, the source of the first transistor M1 is connected to the sixth node N6, the source of the second transistor M2 is connected to the seventh node N7, the source of the fifth transistor M5 is connected to the eighth node N8, the source of the sixth transistor M6 is connected to the ninth node N9, and the second node N2 serves as an output port Vout of the output structure.

The first transistor M1 and the second transistor M2 are N-type transistors, and the fifth transistor M5 and the sixth transistor M6 are P-type transistors.

Referring to fig. 6, an amplifier 600 may include:

an output structure 500, an output port Vout of the output structure 500 being an output port of the amplifier 600;

an input structure 61 comprising five ports, a first output port and a second output port of the input structure 61 being connected to the output structure 500, a first input port (fourth node N4) and a second input port (fifth node N5) of the input structure 61 being a first input port and a second input port of the amplifier 600, respectively;

a current source 62 comprising two ports, a first port of the current source 62 being connected to the fifth port (third node N3) of the input structure 61.

Fig. 7 is an embodiment of the amplifier shown in fig. 6.

Referring to fig. 7, in an exemplary embodiment of the present disclosure, the second port of the current source 62 is grounded, the first output port of the input structure 61 is connected to the sixth node N6, the second output port is connected to the seventh node N7, and the eighth node N8 and the ninth node N9 of the output structure 500 are both connected to the power source VCC. A first input port (fourth node N4) and a second input port (fifth node N5) of the input structure 61 are connected to the first input voltage Vin1 and the second input voltage Vin2 as a first input port and a second input port, respectively, of the amplifier 600, and a first port of the current source 62 is connected to a fifth port (third node N3) of the input structure 61.

Fig. 8 is another embodiment of the amplifier shown in fig. 6.

Referring to fig. 8, in another embodiment, the second port of the current source 62 is connected to the power source VCC, the first output port of the input structure 61 is connected to the eighth node N8, the second output port is connected to the ninth node N9, and the sixth node N6 and the seventh node N7 of the output structure 500 are both grounded. A first input port (fourth node N4) and a second input port (fifth node N5) of the input structure 61 are connected to the first input voltage Vin1 and the second input voltage Vin2 as a first input port and a second input port, respectively, of the amplifier 600, and a first port of the current source 62 is connected to a fifth port (third node N3) of the input structure 61.

Referring to fig. 9, the driving circuit 900 may include:

the first amplifier 91 is the amplifier (200, 300, 400, 600, 700, 800) as described above, and has a first input terminal connected to the first reference voltage Vref1 and a second input terminal connected to the tenth node N10;

a second amplifier 92, which is an amplifier (200, 300, 400, 600, 700, 800) as described above, having a first input terminal connected to a second reference voltage Vref2, and a second input terminal connected to a tenth node N10;

a first driving transistor Mdrv1 having a gate connected to the output terminal of the first amplifier 91, a source connected to a power source VCC, and a drain connected to a tenth node N10;

the second drive transistor Mdrv2 has a gate connected to the output terminal of the second amplifier 92, a source connected to ground, a drain connected to the tenth node N10, and a tenth node N10 as the output terminal of the drive circuit 900.

In the embodiment of the present disclosure, the first amplifier 91 and the second amplifier 92 may be the same or different, and the amplifiers configured by applying the above embodiments are all within the protection scope of the present disclosure.

In the embodiment shown in fig. 9, the first drive transistor Mdrv1 is a P-type transistor and the second drive transistor Mdrv2 is an N-type transistor. Thus, the first input terminal of the first amplifier 91 is an inverting input terminal, and the second input terminal is a non-inverting input terminal; the first input of the second amplifier 92 is an inverting input and the second input is a non-inverting input.

In one embodiment of the present disclosure, the first reference voltage Vref1 is not equal to the second reference voltage Vref2, when there is the first reference voltage Vref1 > the output voltage Vout > the second reference voltage Vref 2. In order to make the P-type first driving transistor Mdrv1 pull up the tenth node N10, the inverting input terminal of the first amplifier 91 is connected to the first reference voltage Vref1, and the non-inverting input terminal is connected to the tenth node N10; in order to pull down the tenth node N10 by the N-type second drive transistor Mdrv2, the inverting input terminal of the first amplifier 91 is connected to the second reference voltage Vref2, and the non-inverting input terminal thereof is connected to the tenth node N10.

In another embodiment, the first reference voltage Vref1 is equal to the second reference voltage Vref2, where Vref1 is Vout, Vref 2.

In an exemplary embodiment of the present disclosure, the first driving transistor Mdrv1 and the second driving transistor Mdrv2 are both N-type transistors or both P-type transistors. At this time, the first and second input terminals of the first amplifier 91 or the second amplifier 92 may be defined according to the type of transistors connected thereto.

Referring to fig. 10, when the first driving transistor Mdrv1 and the second driving transistor Mdrv2 are both N-type transistors, the non-inverting input terminal of the first amplifier 91 is connected to the tenth node N10, and the inverting input terminal is connected to the first reference voltage Vref 1. At this time, the first input terminal of the first amplifier 91 is a non-inverting input terminal, and the second input terminal is an inverting input terminal; the first input of the second amplifier 92 is an inverting input and the second input is a non-inverting input.

Referring to fig. 11, in an exemplary embodiment of the present disclosure, the driving circuit further includes:

the reference voltage generating circuit 93 is used for generating a first reference voltage Vref1 and a second reference voltage Vref2, and the first reference voltage Vref1 and the second reference voltage Vref2 are adjustable.

The reference voltage generation circuit 93 may be formed by a voltage division circuit composed of a plurality of resistors, and the reference voltages are drawn from different nodes of the voltage division circuit, that is, the values of the first reference voltage Vref1 and the second reference voltage Vref2 may be flexibly adjusted. Of course, the reference voltage generating circuit 93 may have various schemes, and the disclosure is not limited thereto.

Referring to fig. 12 in one embodiment, the first amplifier 91, the second amplifier 92, the first drive transistor Mdrv1, and the second drive transistor Mdrv2 are all powered by a first power supply V1, and the reference voltage generation circuit 92 is powered by a second power supply V2. The voltage value of the first power source V1 may be greater than the voltage value of the second power source V2. At this time, the first transistor Mdrv1 is connected to the second power supply V2.

By using a lower voltage to power the reference voltage generation circuit 92 to generate the reference voltage, the power consumption of the driver circuit can be further reduced.

The driving circuits shown in fig. 9 to 12 have lower power consumption than the related art due to the self-supplied amplifier using the bias voltage provided by the embodiment of the present disclosure.

In summary, in the circuit provided by the embodiment of the present disclosure, the bias voltage of the transistor in the circuit is set to be provided by the transistor itself, so that the amplification function can be still achieved after the bias circuit set for providing the bias voltage in the related art is deleted, and the power consumption of the circuit is effectively reduced.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A cascode structure, wherein a bias voltage for a cascode structure in the cascode structure is provided by itself, the cascode structure having a first node, a second node, a third node, a fourth node, and a fifth node.

2. The cascode structure of claim 1, wherein a common-gate structure of said cascode structure comprises:

the grid electrode and the drain electrode of the first transistor and the grid electrode of the second transistor are connected with the first node, and the drain electrode of the second transistor is connected with the second node.

3. The cascode structure of claim 2, wherein a common source structure of said cascode structure comprises:

the drain of the third transistor is connected with the source of the first transistor, the drain of the fourth transistor is connected with the source of the second transistor, the source of the third transistor and the source of the fourth transistor are both connected with the third node, the gate of the third transistor is connected with the fourth node, and the gate of the fourth transistor is connected with the fifth node.

4. The cascode structure of claim 3, wherein said first transistor, said second transistor, said third transistor and said fourth transistor are of the same type.

5. An amplifier, comprising:

the cascode structure according to any one of claims 1 to 4, the fourth and fifth nodes in the cascode structure being a first and second input port of the amplifier, respectively;

a current source comprising two ports, a first port of the current source being connected to the third node;

and the load structure comprises four ports, a first port of the load structure is connected with the first node, a second port of the load structure is connected with the second node, and the second port of the load structure is used as an output port of the amplifier.

6. The amplifier of claim 5, wherein a transistor type of the current source is the same as a transistor type of the cascode structure.

7. The amplifier of claim 5, wherein the load structure comprises:

the grid electrode and the drain electrode of the fifth transistor are both connected with the grid electrode of the sixth transistor, the drain electrode of the fifth transistor serves as a first port of the load structure, the drain electrode of the sixth transistor serves as a second port of the load structure, the source electrode of the fifth transistor serves as a third port of the load structure, and the source electrode of the sixth transistor serves as a fourth port of the load structure.

8. The amplifier of claim 5, wherein a transistor type in the load structure is different from a transistor type of the cascode structure.

9. The amplifier of claim 7, wherein a second port of the current source is connected to ground, and wherein the third port and the fourth port of the load structure are both connected to a power supply.

10. The amplifier of claim 7, wherein a second port of the current source is connected to a power supply, and the third port and the fourth port of the load structure are both connected to ground.

11. An output structure, wherein bias voltages for transistors in the output structure are each provided by the output structure itself, the output structure comprising a first node, a second node, a sixth node, a seventh node, an eighth node, and a ninth node.

12. The output structure of claim 11, wherein the output structure comprises:

the gate of the first transistor, the gate of the second transistor, the drain of the first transistor, and the drain of the fifth transistor are all connected to the first node, the drain of the second transistor and the drain of the sixth transistor are all connected to the second node, the source of the first transistor is connected to the sixth node, the source of the second transistor is connected to the seventh node, the source of the fifth transistor is connected to the eighth node, the source of the sixth transistor is connected to the ninth node, and the second node is used as an output port of the output structure.

13. The output structure of claim 12, wherein the first transistor and the second transistor are N-type transistors, and the fifth transistor and the sixth transistor are P-type transistors.

14. An amplifier, comprising:

an output structure as claimed in any one of claims 11 to 13, an output port of the output structure serving as an output port of the amplifier;

the first input port and the second input port of the input structure are respectively used as a first input port and a second input port of the amplifier;

a current source comprising two ports, a first port of the current source being connected to a fifth port of the input structure.

15. The amplifier of claim 14, wherein a second port of the current source is connected to ground, a first output port of the input structure is connected to the sixth node, a second output port of the input structure is connected to the seventh node, and the eighth node and the ninth node of the output structure are both connected to a power supply.

16. The amplifier of claim 14, wherein a second port of the current source is connected to a power supply, a first output port of the input structure is connected to the eighth node, a second output port of the input structure is connected to the ninth node, and the sixth node and the seventh node of the output structure are both connected to ground.

17. A driver circuit, comprising:

a first amplifier as claimed in any one of claims 5 to 10 or 14 to 16, the first input terminal being connected to a first reference voltage, the second input terminal being connected to a tenth node;

a second amplifier as claimed in any one of claims 5 to 10 or 14 to 16, having a first input connected to a second reference voltage and a second input connected to said tenth node;

the grid electrode of the first driving transistor is connected with the output end of the first amplifier, the source electrode of the first driving transistor is connected with a power supply, and the drain electrode of the first driving transistor is connected with the tenth node;

and the grid electrode of the second driving transistor is connected with the output end of the second amplifier, the source electrode of the second driving transistor is grounded, the drain electrode of the second driving transistor is connected with the tenth node, and the tenth node is used as the output end of the driving circuit.

18. The driving circuit of claim 17, wherein the first driving transistor is a P-type transistor and the second driving transistor is an N-type transistor.

19. The driving circuit according to claim 17, wherein the first driving transistor and the second driving transistor are both N-type transistors or both P-type transistors.

20. The driving circuit of claim 17, wherein the first reference voltage and the second reference voltage are not equal.

21. The drive circuit of claim 17, further comprising:

and the reference voltage generating circuit is used for generating the first reference voltage and the second reference voltage, and both the first reference voltage and the second reference voltage can be adjusted.

22. The driver circuit of claim 21, wherein the first amplifier, the second amplifier, the first driver transistor, and the second driver transistor are all powered by a first power supply, and wherein the reference voltage generation circuit is powered by a second power supply.

23. The drive circuit according to claim 22, wherein a voltage value of the first power source is larger than a voltage value of the second power source.