JP4836483B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4836483B2
JP4836483B2 JP2005118223A JP2005118223A JP4836483B2 JP 4836483 B2 JP4836483 B2 JP 4836483B2 JP 2005118223 A JP2005118223 A JP 2005118223A JP 2005118223 A JP2005118223 A JP 2005118223A JP 4836483 B2 JP4836483 B2 JP 4836483B2
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Japan
Prior art keywords
concavo
semiconductor device
lead frame
convex structure
semiconductor
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Expired - Fee Related
Application number
JP2005118223A
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English (en)
Japanese (ja)
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JP2006302940A5 (enExample
JP2006302940A (ja
Inventor
智光 理崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP2005118223A priority Critical patent/JP4836483B2/ja
Priority to US11/404,934 priority patent/US7768102B2/en
Publication of JP2006302940A publication Critical patent/JP2006302940A/ja
Publication of JP2006302940A5 publication Critical patent/JP2006302940A5/ja
Application granted granted Critical
Publication of JP4836483B2 publication Critical patent/JP4836483B2/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/256Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01ELECTRIC ELEMENTS
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • H10D62/405Orientations of crystalline planes

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)
JP2005118223A 2005-04-15 2005-04-15 半導体装置 Expired - Fee Related JP4836483B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005118223A JP4836483B2 (ja) 2005-04-15 2005-04-15 半導体装置
US11/404,934 US7768102B2 (en) 2005-04-15 2006-04-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005118223A JP4836483B2 (ja) 2005-04-15 2005-04-15 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011119228A Division JP2011171766A (ja) 2011-05-27 2011-05-27 半導体装置

Publications (3)

Publication Number Publication Date
JP2006302940A JP2006302940A (ja) 2006-11-02
JP2006302940A5 JP2006302940A5 (enExample) 2008-03-27
JP4836483B2 true JP4836483B2 (ja) 2011-12-14

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Application Number Title Priority Date Filing Date
JP2005118223A Expired - Fee Related JP4836483B2 (ja) 2005-04-15 2005-04-15 半導体装置

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US (1) US7768102B2 (enExample)
JP (1) JP4836483B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8552543B2 (en) * 2006-11-13 2013-10-08 International Rectifier Corporation Semiconductor package
JP5830958B2 (ja) * 2011-06-23 2015-12-09 日産自動車株式会社 半導体モジュール
US9171804B2 (en) 2012-11-19 2015-10-27 Infineon Technologies Ag Method for fabricating an electronic component
DE102014115770B4 (de) 2014-10-30 2018-03-29 Infineon Technologies Ag Verfahren zur verbindung eines substrats
US9496193B1 (en) * 2015-09-18 2016-11-15 Infineon Technologies Ag Semiconductor chip with structured sidewalls
US11251152B2 (en) 2020-03-12 2022-02-15 Diodes Incorporated Thinned semiconductor chip with edge support
US11133246B1 (en) * 2020-03-24 2021-09-28 Vanguard International Semiconductor Corporation Semiconductor structure employing conductive paste on lead frame

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04293268A (ja) * 1991-03-22 1992-10-16 Sharp Corp 半導体装置とその製造方法
US5171703A (en) * 1991-08-23 1992-12-15 Intel Corporation Device and substrate orientation for defect reduction and transistor length and width increase
JPH0620984A (ja) * 1992-06-29 1994-01-28 Toyota Motor Corp 半導体装置の裏面電極形成方法
US6104062A (en) * 1998-06-30 2000-08-15 Intersil Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
US6335546B1 (en) * 1998-07-31 2002-01-01 Sharp Kabushiki Kaisha Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device
US6406636B1 (en) * 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
JP3215686B2 (ja) * 1999-08-25 2001-10-09 株式会社日立製作所 半導体装置及びその製造方法
JP2002029057A (ja) * 2000-07-18 2002-01-29 Casio Comput Co Ltd インクジェットプリントヘッド
ATE463462T1 (de) * 2000-10-09 2010-04-15 Imec Verfahren zur herstellung von mikrobearbeiteten anordnungen
JP3531613B2 (ja) * 2001-02-06 2004-05-31 株式会社デンソー トレンチゲート型半導体装置及びその製造方法

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US20060231934A1 (en) 2006-10-19
US7768102B2 (en) 2010-08-03
JP2006302940A (ja) 2006-11-02

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