JP4826195B2 - rfid tag - Google Patents

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JP4826195B2
JP4826195B2 JP2005288544A JP2005288544A JP4826195B2 JP 4826195 B2 JP4826195 B2 JP 4826195B2 JP 2005288544 A JP2005288544 A JP 2005288544A JP 2005288544 A JP2005288544 A JP 2005288544A JP 4826195 B2 JP4826195 B2 JP 4826195B2
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antenna
rfid tag
antenna pattern
spiral
ic chip
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JP2007102348A (en
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荒木  登
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大日本印刷株式会社
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Description

  The present invention relates to an RFID tag (also referred to as a wireless IC tag, an IC card, a non-contact data carrier, etc.) that communicates by an electromagnetic induction method, and particularly relates to an RFID tag that contributes to miniaturization.

  RFID tags that communicate using the electromagnetic induction method are mainly used in society mainly in the card type. In recent years, RFID tags having a size much smaller than the card type have been developed, and further miniaturization is expected.

  On the other hand, an RFID tag that communicates using an electromagnetic induction method requires an antenna coil that forms a resonance circuit that resonates at a predetermined frequency (for example, 13.56 MHz or 135 KHz). In general, it is formed in a single layer structure on one surface. In general, the card-type RFID tag is formed in a substantially rectangular shape (rectangular shape) along the outer periphery of the card. In the case of a card type of 13.56 MHz, since the card is sufficiently large, even with a single layer structure, the number of turns of the antenna coil for securing a predetermined inductance value is sufficient to be about 3 to 4 times. .

  However, if the antenna coil having such a conventional single-layer structure is miniaturized, a sufficient number of turns cannot be secured while securing the inner peripheral area of the antenna coil, and a predetermined inductance value is set. There is a problem that it cannot be secured.

  Therefore, an antenna coil having a multi-layer structure has been proposed. For example, in Patent Document 1, a plurality of resin sheets having conductive patterns formed in a spiral shape are stacked and electrically connected so that the spirals of the antenna patterns are in the same direction and electrically connected. An antenna coil of structure is disclosed.

The spiral shape of the antenna coil disclosed in Patent Document 1 is a rectangular shape that is substantially along the outer periphery of a rectangular substrate as in the prior art, except that the mounting area of the IC chip is left outside the spiral. Both ends of the antenna coil to be connected are arranged outside the spiral that is rectangular.
JP 2004-240529 A

  In this way, when an IC chip is arranged outside the antenna pattern while keeping the antenna pattern in a general rectangular shape with a card-type antenna coil, an extra board area is required for the IC chip arrangement, There is a problem that it is difficult to reduce the size of the RFID tag. Further, even when the IC chip is arranged inside the spiral, if the spiral remains rectangular, an extra board area is required to form a through hole to be placed outside the spiral, and the RFID tag There is a problem that it is difficult to reduce the size.

  Also, if the spiral of the antenna pattern is made circular in order to improve the efficiency of receiving magnetic flux, the area of the antenna cannot be secured for the size of the RFID tag substrate, and the RFID tag can be reduced in size without reducing the inductance value. There is a problem that it is difficult to make it.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide an RFID tag including a multi-layered antenna coil capable of downsizing the RFID tag while ensuring a necessary inductance value. And

In order to achieve the above object, an RFID tag according to the present invention forms a spiral antenna pattern leaving four corners on at least one surface of a rectangular insulating substrate, and forms a spiral antenna pattern within the antenna pattern spiral and the four corners of the insulating substrate. One of them is a unit antenna substrate formed by forming a connection terminal connected to the inner end or the outer end of the antenna pattern, and a plurality of layers are laminated via an insulating layer. The antenna patterns are connected in series to form an antenna coil having both terminals on the uppermost unit antenna substrate, and an IC is placed in the spiral of the uppermost antenna pattern of the stacked unit antenna substrate. equipped with a chip, the ends of the antenna coil Ri name connected electrically to the IC chip, and the antenna pattern spiral The main coil portions when viewed from one side, is characterized in face to Rukoto each other via the insulating layer.

  The planar shape of the insulating substrate may be a rectangular shape in terms of facilitating the processing of a large number of pieces, but is preferably a substantially square shape in the present invention. By making the substrate plane substantially square, the area of the substrate can be increased while shortening the length of each side, and the inductance value can be increased.

  As the interlayer connection conductor, it is preferable to use a through-hole penetrating all layers. By doing so, it can be simply manufactured.

  According to the present invention, it is possible to provide an RFID tag including a multi-layered antenna coil that can reduce the size of the RFID tag while ensuring a necessary inductance value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, in principle, the same components are denoted by the same reference numerals, and description thereof is omitted.

[First Embodiment]
FIG. 1 is a plan view of the RFID tag 100 according to the first embodiment of the present invention as seen from the front (front) surface (IC chip mounting surface) side, and FIG. 2 shows the RFID tag from the back surface side. FIG.

  As shown in FIGS. 1 and 2, the planar shape of the substrate of the RFID tag 100 is substantially square. The size of the substrate is much smaller than 54 mm × 85.6 mm, which is a standard size for a card-type RFID tag (IC card), for example, about 5 mm × 5 mm. . The mounted IC chip is, for example, a rectangle having a planar shape of about 0.5 mm to 1 mm and a thickness of about 150 μm. Therefore, the RFID tag 100 of the present embodiment is not so large with respect to the size of the IC chip to be mounted.

  The planar shape of the substrate does not necessarily have to be a square, but is rectangular in order to facilitate the production of a large number of pieces. By making the substrate plane substantially square as shown in FIG. 1, it is easy to secure the inner area of the antenna coil while reducing the size, and it is easy to improve the inductance value of the coil.

  As shown in FIG. 1, a spiral antenna pattern 12 made of a conductor such as copper is formed on the front surface side of the RFID tag 100, one main surface 11 of the insulating substrate, leaving four corners. Has been. The spiral antenna pattern 12 is formed as close as possible to the outer edge so as to make full use of the area of the substrate. However, since the four corners remain, the shape is substantially octagonal. A substantially octagonal spiral antenna pattern having such a shape obtained by cutting off four corners from a substantially square has an advantage that it is more efficient to receive magnetic flux because it is closer to a circle than a square one.

  As shown in FIG. 1, an outer terminal 14 directly connected to the outer end 12 b of the antenna pattern 12 is formed at one of the four corners of the main surface 11. The outer terminal 14 is formed with a through hole 6b for connecting to an outer end of an antenna pattern of another layer. A through hole 6a is formed in another one of the four corners of the main surface 11, but the through hole 6a is not connected to the antenna pattern 12 of this layer. In the remaining two corners of the main surface 11, there are shown substantially right-angled triangular conductor patterns 19a and 19b formed integrally with the antenna pattern 12, but these are the components of the antenna. This is a so-called dummy pattern.

  In FIG. 1, a region indicated by reference numeral 7 in the substantially central portion is a portion covered with a sealing resin. The inner end 12a of the spiral and the IC chip 1 are hidden under the sealing resin 7 and cannot be seen. Further, although it is difficult to understand in FIG. 1, the antenna pattern 12 and the wiring pattern outside thereof are protected by a solder resist 8 for Au plating.

  FIG. 3 is a plan view showing a state of the front surface of the RFID tag before the IC chip is resin-sealed. In FIG. 3, the inside of the rectangle A indicated by the bold line is a region sealed with the sealing resin 7. A solder resist 8 is applied to the outside of the rectangle A indicated by the bold line so as to be slightly higher (for example, about 5 μm) than the inside so that the sealing resin 7 does not flow out.

  As shown in FIG. 3, chip mounting pads 15, chip connection terminals 16a and 16b, and through holes 5a and 5b are formed inside the spiral of the antenna pattern 12. The IC chip 1 includes two electrode terminals 3a and 3b. The IC chip 1 is mounted on the chip mounting pad 15 with its electrode terminals facing 3a and 3b. The electrode terminal 3a of the IC chip 1 is connected to the chip connection terminal 16a by a low-profile wire 4a. The electrode terminal 3b of the IC chip 1 is connected to the chip connection terminal 16b by a low-profile wire 4b. The chip connection terminal 16 a is also the inner connection terminal 13 connected to the inner end 12 a of the spiral antenna pattern 12. The chip connection terminal 16b is connected to the through hole 5b through the wiring 12c. A part of the through holes 5a and 5b is hidden under the IC chip 1 and also serves as a chip mounting pad. Even in this case, the through holes 5a and 5b are not electrically connected to the bottom surface of the IC chip 1. By arranging a part or all of the through holes 5a and 5b under the IC chip 1 so as not to be electrically connected, and also serving as a chip mounting pad, an area dedicated to the through hole is provided inside the spiral. Since it is not necessary to ensure, the area of the antenna coil can be increased. That is, the number of turns of the antenna coil is increased by not taking a special area for the inner through hole even if other conditions such as the board size, wiring width, gap width, and number of antenna patterns remain the same. Therefore, the inductance value of the antenna coil can be increased.

  The wiring pattern of each wiring layer is formed by etching copper. The chip mounting pad 15 and the chip connection terminals 16a and 16b are further plated with Au in order to ensure electrical connection with the electrode terminals of the IC chip 1. The low-profile wires 4a and 4b are also Au plated. A solder resist for Au plating is applied to the parts that do not require Au plating, such as the antenna pattern 12 and the connection terminals 13 and 14. As described above, this solder resist is formed so that the outside of the rectangle A indicated by the thick line is slightly higher than the inside.

  On the back side of the RFID tag 100 of the present embodiment, as shown in FIG. 2, as in the front side, the antenna pattern 42 is a substantially octagonal spiral pattern leaving the four corners of the main surface 41 of the substantially square insulating substrate. Is formed. Inside the spiral of the antenna pattern 42, an inner connection terminal 43 that is directly connected to the inner end 42a of the spiral is provided. The inner connection terminal 43 is provided with a through hole 5b. At one of the four corners of the main surface 41, a substantially right-angled triangular outer terminal 44 that is directly connected to the spiral outer end 42b of the antenna pattern 42 is formed. The outer terminal 44 is formed with a through hole 6a for connecting to the outer end of the antenna pattern of another layer. A through hole 6b is formed in another one of the four corners of the main surface 41, but the through hole 6b is not connected to the antenna pattern 42 of this layer. In the remaining two corners of the main surface 41, there are shown substantially right-angled triangular conductor patterns 49a and 49b formed integrally with the antenna pattern 42. These are the antenna components. This is a so-called dummy pattern. On the entire rear surface side, a solder resist 8 for Au plating is applied and protected.

As shown in FIGS. 1 to 3, the through holes 5 a and 5 b positioned inside the spiral and the through holes 6 a and 6 b positioned outside the spiral respectively penetrate the entire substrate of the RFID tag 100. It is a through hole. The through-hole has an advantage that it can be easily manufactured and does not require an extra space, rather than forming a separate through-hole for each pair of layers to be connected.
These through-through holes 5a, 5b, 6a, 6b have inner walls plated with copper, for example, and the insides of the holes are filled with a conductor such as conductive resin or copper plating and filled. Since the conductor is filled inside the hole of the through hole, the liquid for chip mounting or resin sealing does not enter the hole. Further, corrosion due to the plating solution remaining on the inner wall of the through hole can be prevented. Note that, when the through hole is filled with a conductive resin, conduction between layers is possible, so that the inner wall of the through hole may not be plated. The inner diameters of these through holes 5a, 5b, 6a, 6b are, for example, about 10 to 100 μm. The through hole can be made relatively easily by, for example, known laser processing or drilling.

  Next, the configuration of the antenna of the RFID tag will be described with reference to FIGS.

  FIG. 4 is an exploded perspective view schematically showing the configuration of the RFID tag in a simplified manner. 5 to 8 are horizontal sectional views showing wiring patterns of respective layers constituting the antenna of the RFID tag, FIG. 5 is a first wiring layer (also referred to as an uppermost layer) on which an IC chip is mounted, and FIG. FIG. 7 shows a third wiring layer, and FIG. 8 shows a fourth wiring layer.

  In FIG. 4, in order to explain the connection relationship between the respective wiring layers, the number of turns is reduced to be simplified than the actual number. The actual number of spirals of the antenna pattern is, for example, about nine as shown in FIGS. 5 to 8 depending on the required inductance value and design.

  As shown in FIG. 4, the RFID tag 100 according to the first embodiment includes four unit antenna substrates 10 each having a wiring layer including a spiral antenna pattern formed on one main surface of a substantially square insulating substrate. , 20, 30, and 40 are laminated and integrated through an insulating layer to form a four-layer wiring board. The configurations of the unit antenna substrate 10 positioned at the uppermost layer of the four unit antenna substrates stacked and the unit antenna substrate 40 positioned at the lowermost layer are the same as those described with reference to FIGS.

  As shown in FIGS. 4 to 8, each wiring layer includes spiral antenna patterns 12, 22, 32, and 42 in order from the first wiring layer. Each antenna pattern 12, 22, 32, 42 includes one inner end 12a, 22a, 32a, 42a and one outer end 12b, 22b, 32b, 42b. One inner connection terminal 13, 23, 33, 43 is connected to each of the inner ends 12a, 22a, 32a, 42a. One outer connection terminal 14, 24, 34, 44 is connected to each of the outer ends 12b, 22b, 32b, 42b. The inner connection terminals 13, 23, 33, and 43 are provided inside the spiral of the antenna pattern, and the inner terminals of the wiring layers that are connected to each other are overlapped at the same position. Only one of the plurality of through-holes 5a and 5b is electrically connected to each inner connection terminal 13, 23, 33, and 43. The outer connection terminals 14, 24, 34, 44 are provided at one of the four corners of the antenna substrate so that the outer terminals of the wiring layers connected to each other are in the same position. Each outer connection terminal 14, 24, 34, 44 is made to conduct only one of the plurality of through-through holes 6 a, 6 b.

  As shown in FIGS. 4 to 8, wiring regions 19a, 19b, 29a, 29b, 39a, 39b, and 49a having substantially right-angled isosceles triangles that are not provided with through holes are provided at two corners of each wiring layer. , 49b are formed. These are integrated with the spiral antenna pattern, but are dummy patterns that may or may not be a component of the antenna.

  As shown in FIG. 4, the antenna pattern 12 of the first wiring layer and the antenna pattern 22 of the second wiring layer are connected via the through holes 6b that are electrically connected to the outer connection terminals 14 and 24 at the outer end of the spiral. Has been. The antenna pattern 22 of the second wiring layer and the antenna pattern 32 of the third wiring layer are connected to each other at the inner end of the spiral via the through holes 5a that are electrically connected to the inner connection terminals 23 and 33. The antenna pattern 32 of the third wiring layer and the antenna pattern 42 of the fourth wiring layer are connected to each other at the outer end of the spiral via through holes 6a that are electrically connected to the outer connection terminals 34 and 44. The antenna pattern 42 of the fourth wiring layer and the antenna pattern 12 of the first wiring layer are connected to each other at the inner end of the spiral via the through holes 5b that are electrically connected to the inner connection terminals 43 and 13.

  The antenna patterns 12, 22, 32, and 42 are electrically connected in series as shown in FIG. 4 through these connection terminals and interlayer connection conductors, and both terminals are connected to the first wiring layer (uppermost layer). One antenna coil 2 having the above is configured. One end of the antenna coil 2 configured in this way is the inner connection terminal 13 (also used as the chip connection terminal 16a) of the first wiring layer, and the other end is connected to the inner through-through hole 5b of the first wiring layer. Chip connection terminal 16b (may be referred to as wiring 12c).

  In this example, the unit antenna substrates are stacked and connected in this order. However, in the example of FIG. 4, the unit antenna substrate 20 on which the second wiring layer is formed and the third wiring layer are formed. The unit antenna substrate 30 may be stacked in a different order. Even in such a case, it is possible to configure one antenna coil in which each antenna pattern is connected in series and both ends are exposed in the uppermost layer.

  As shown in FIGS. 4 to 8, these spiral antenna patterns 12, 22, 32, and 42 are formed so that wirings of main coil portions overlap each other when seen through from one surface. Since they are formed so as to overlap each other, a parasitic capacitance is generated between the antenna patterns of the wiring layers facing each other through the insulating layer. In the present embodiment, the parasitic capacitance is actively used. Accordingly, in order to increase the parasitic capacitance, it is preferable that the insulating layer interposed between the wiring layers has a high dielectric constant.

  As shown in FIGS. 4 to 8, when these spiral antenna patterns 12, 22, 32, and 42 are traced from one end of the antenna coil 2 along the connection relationship of each antenna pattern, the swirling direction of the spiral is It is formed so as to be in the same direction (for example, clockwise for clockwise and counterclockwise for counterclockwise). That is, each antenna pattern is formed in a direction that does not cancel out the current generated when a magnetic field in a certain direction is received.

  FIG. 9 is a diagram showing an equivalent circuit of the RFID tag 100 of the present embodiment. As shown in FIG. 9, the RFID tag 100 basically comprises an LC resonance circuit with a capacitor C1 mounted inside the IC chip 1 and an antenna coil 2 having a four-layer structure. Furthermore, the parasitic capacitance C2 generated by the overlapping of the antenna patterns described above is connected in parallel to the capacitor C1 in the IC chip 1.

  Here, the IC chip 1 is mainly composed of a read-only memory (ROM), a random access memory (RAM), a logic circuit, and an arithmetic unit (CPU) (not shown). The CPU executes various types of arithmetic processing such as communication control with a reader / writer and response processing using programs and data stored in the ROM and RAM. The ROM stores a tag identification code, which is identification information uniquely assigned to each RFID tag when the RFID tag 100 is manufactured, and the tag identification code cannot be rewritten. The IC chip 1 includes a capacitor C1 and the like in addition to a rewritable non-volatile memory and an RF circuit for wireless communication that do not require power backup (see FIG. 9). As the IC chip 1, a chip that is commercially available as a chip for a 13.56 MHz band RFID tag, such as Philips I-CODE SLI chip, Infineon Technologies my-d chip, etc., is appropriately selected according to the application. Can be used.

  The antenna pattern formed on each unit antenna substrate has, for example, a line width of about 80 μm, a line-to-line (gap) of about 70 μm, and a line thickness of about 18 μm. Although the antenna pattern 12 can be formed by a known method, it is preferably formed by etching a conductive metal such as copper because it is such a fine wiring pattern.

  As described above and as shown in FIGS. 1 to 8, the RFID tag 100 according to the present embodiment has a four-layer spiral antenna pattern in which the number of turns of each layer is about 9, and is connected in series. One antenna coil having both terminals in the first wiring layer, which is the uppermost layer, is constructed, an IC chip is mounted inside the spiral of the antenna pattern of the first wiring layer, and both the electrode terminals of the IC chip and the antenna coil Both terminals are electrically connected. By adopting such a configuration, even if the substrate is significantly reduced in size compared to an IC card, such as a substantially square of 5 mm square, a sufficient number of turns and area of the antenna coil can be secured. A predetermined inductance value could be secured.

  In the present embodiment, the RFID tag 100 may be thicker than a card-type one, and the thickness thereof is, for example, about 0.3 mm to 0.5 mm in a portion that is not resin-sealed, and 0 in total thickness. .6 mm to 1.2 mm.

(Production method)
Next, a method for manufacturing the RFID tag 100 according to this embodiment will be described.

  Hereinafter, for convenience, the description will be made as a method for manufacturing one RFID tag. However, as shown in FIG. 10, in actuality, for example, 7 × 7 Plural pieces such as 49 pieces are manufactured together and separated into pieces by dicing to form individual RFID tags 100.

  As schematically shown in FIG. 4, the RFID tag of the present invention forms antenna patterns and connection terminals of a predetermined shape on one side of four insulating substrates to form four unit antenna substrates, and these four unit antennas. It can be manufactured by laminating a substrate via an adhesive insulating layer and making each connection terminal conductive. As the material and manufacturing method therefor, a known multilayer printed wiring board material and manufacturing method can be used.

However, if four layers of a single-sided printed wiring board are laminated via an adhesive insulating layer, the whole becomes thick. In addition, since the insulating layer between the wiring layers becomes thick, it cannot be expected that parasitic capacitance is generated between the wiring layers stacked via the insulating layer.
Therefore, in actuality, in order to make the interlayer insulating layer thin to easily generate parasitic capacitance, and to make the whole thin, as described below, the double-sided wiring board is manufactured by a multilayer method as an inner layer board. It is preferable (see FIGS. 11 to 12).

  First, as an inner layer board, a double-sided copper-clad board in which 18 μm-thick copper foil is stretched on both sides of an insulating board having a thickness of 0.1 mm is prepared, and the second wiring layer shown in FIG. A third wiring layer pattern shown in FIG. 7 was formed on the other copper foil surface by known photolithography and etching. As the insulating substrate, for example, a glass epoxy prepreg cured was used. It is not necessary to prepare a copper foil having the same thickness as the finished one, and it may be thicker. This is because the thickness of the wiring layer can be adjusted by etching the copper foil. As the copper etchant, a commonly used one, for example, an aqueous solution containing iron chloride as a component was used.

  On the other hand, two sets of single-sided copper-clad substrates in which a copper foil having a thickness of 18 μm was stretched on one side of an insulating substrate having a thickness of 0.1 mm were prepared as outer layer plates.

  Then, as shown in FIG. 11 (a), the double-sided board 102 having the wiring layer formed thereon is used as an inner layer board, and the single-sided copper-clad substrate before the wiring layer is formed on both sides via insulating adhesive layers 104 and 105, respectively. 101 and 103 were laminated together with the copper layer on the outside. As the insulating adhesive layers 104 and 105, for example, uncured glass epoxy prepreg was used.

  Then, as shown in FIG.11 (b), the laminated body laminated | stacked is heat-pressed and integrated, a through-hole is drilled by the laser processing, drilling, etc. in the predetermined place shown in FIGS. Was plated with copper, and the inside of the hole was filled with a conductive paste to fill the hole, thereby forming through-holes 5a, 5b, 6a, 6b. Then, the copper foils on both sides of the outer layer were patterned by known photolithography and etching. That is, the first wiring layer pattern shown in FIG. 5 was formed on the copper layer of the single-sided copper-clad substrate 101, and the fourth wiring layer pattern shown in FIG.

  Subsequently, as shown in FIG. 11C, after masking the portion of the first wiring layer to which Au plating is to be performed, that is, the chip mounting pad 15 and the chip connection terminals 16a and 16b, A solder resist for protecting from Au plating and oxidation was applied to the bottom surface. As a result, the portion where Au plating is not desired, that is, the antenna pattern 12 of the first wiring layer, the outer connection terminals 14, the surfaces of the through holes 6a and 6b, the entire surface of the fourth wiring layer, and the exposed insulating substrate A solder resist layer 8 for anti-Au plating was formed on the part. Then, the mask was removed and bonding plating was performed. As a result, the surfaces of the chip mounting pad 15 and the chip connection terminals 16a and 16b were Au plated. In this way, by effecting Au plating after forming a solder resist layer by opening a window only at the chip mounting portion, effects of reducing the amount of Au plating and stabilizing antenna characteristics can be obtained.

  Subsequently, as shown in FIG. 12D, a mask is applied to a portion of the first wiring layer where the resin sealing is desired (that is, the inside of the region indicated by the thick line A in FIG. 3), and the first wiring layer side again. A solder resist was applied to the surface of the film. The solder resist layer additionally formed at this time serves as a bank to prevent the sealing resin from flowing out as described with reference to FIG. The thickness (height) of the levee, that is, the level difference between the solder resist layers is appropriately determined depending on the amount and viscosity of the sealing resin, and is set to 10 μm, for example.

  Subsequently, as shown in FIG. 12 (e), the mask is removed, and the IC chip 1 is fixed on the chip mounting pad 15 and the inner through-holes 5a and 5b using an adhesive, and by wire bonding, The electrode terminals 3a and 3b of the IC chip 1 were connected to the chip connection terminals 16a and 16b, respectively. Then, as shown in FIG. 12 (f), the recessed portion at the center of the first wiring layer was sealed with a sealing resin 7. As a result, the state shown in FIGS.

  As already described, a plurality of RFID tags are manufactured together on one mounting unit sheet as shown in FIG. That is, after that, it is separated into individual RFID tags by dicing to form individual RFID tags 100.

  The RFID tag 100 of this embodiment is manufactured as described above.

  Then, if necessary, the RFID tag is formed in a form suitable for the use scene by being covered with a transparent resin.

  Although the above description has been given for the case where the antenna wiring layer has four layers, even in the case of a multilayer structure, the antenna wiring layer can be manufactured similarly by increasing the number of double-sided inner layer plates.

[Other Embodiments]
In the above description, the IC chip mounting portion is resin-sealed (partially sealed) at the necessary minimum. However, as shown in FIG. 13B, not only the IC chip mounting portion but also the IC chip mounting surface (uppermost layer). ) The entire surface may be sealed with the sealing resin 7. The manufacturing process in that case is the same as that in the case of partial sealing up to FIGS. After the step of FIG. 11 (c), an IC chip may be mounted and wire-bonded as shown in FIG. 13 (a) without forming an additional solder resist layer and providing a step for bank. Then, as shown in FIG. 13B, the entire uppermost layer is sealed with a sealing resin 7 so that the upper surface of the RFID tag 200 becomes flat.

  Since matters other than resin sealing are the same as those in the first embodiment, description thereof is omitted.

  When the entire surface is sealed in this way, as shown in FIG. 13B, the top surface on the chip mounting surface side can be flattened, so that it is easy to print the brand name, model number, and the like. There are advantages. In addition, there is an advantage that it can be stably arranged regardless of which side is facing down. On the other hand, when the partial sealing is performed as in the first embodiment, the top surface on the chip mounting surface side is not flat as shown in FIG. Therefore, the direction in which stable placement can be performed is limited, and printing is difficult.

  In the above description, the IC chip 1 is connected by wire bonding, but may be flip-chip connected.

  FIG. 14 is a diagram showing an example of the arrangement of connection terminals for flip chip connection. In the figure, only the vicinity of the IC chip mounting area B is shown, and the other areas are omitted. As shown in FIG. 14, in the IC chip mounting area B, the inner connection terminal 13 connected to the inner end 12a of the spiral antenna pattern 12, the chip connection terminal 16a connected to the electrode terminal 3a of the IC chip 1, A chip connection terminal 16b connected to the electrode terminal 3b of the IC chip 1 and through-through holes 5a and 5b are provided. The inner connection terminal 13 and the chip connection terminal 16a are shared and are the same. The through-through hole 5a serves as an interlayer connection conductor for connecting the inner terminals of the antenna patterns of the other layers, and is not connected to the antenna pattern 12 of the first wiring layer. The through-hole 5b serves as an interlayer connection conductor for connection to the inner terminal 43 of the antenna pattern of the fourth wiring layer shown in FIG. 8, as in the case of FIG. As shown in FIG. 14, the through through hole 5b and the chip connection terminal 16b are connected via a wiring 12c. In this way, the electrode terminals 3a and 3b of the IC chip 1 are electrically connected to both ends of the antenna coil 2 having a multilayer structure in which the antenna pattern and the connection terminal of each layer are connected via the through-hole. The

  FIG. 15 is a diagram showing another example of the arrangement of connection terminals for flip-chip connection. In the figure, only the vicinity of the IC chip mounting area B is shown, and the other areas are omitted. The example of FIG. 15 is basically the same as the example of FIG. 14, but the through-holes 5a and 5b protrude outside the IC chip mounting area B, and the antenna pattern is the electrode terminal of the IC chip. The difference is that two small chip mounting pads 15 that are not connected to each other are provided. Since the two small chip mounting pads 15 are bases for mounting the chip, it is not necessary to divide into two in such a shape, and the two may be formed into an elongated quadrangle. Alternatively, one of the small chip mounting pads 15 may be deleted and the through hole 5a may be disposed inside the region B.

  FIG. 16 schematically shows an RFID 300 in which an IC chip is mounted by flip chip connection as shown in FIG. 14, and the IC chip and its vicinity are partially resin-sealed, as in the example shown in FIG. FIG. In FIG. 16, the electrode terminal 3a of the IC chip 1 is connected to the chip connection terminal 16a of the first wiring layer, the electrode terminal 3b of the IC chip 1 and the first wiring layer 16b via the chip connection bumps 9, respectively. Has been. The chip connection bump 9 may be a general conductor for flip chip connection. For example, it can be made of gold (Au), but it may be made of copper and the surface may be plated with Au. In addition, in FIG. 16, although it seems that the chip connection terminal 16a and the through hole 5a are connected, as shown in FIG. 14, the chip connection terminal 16a and the through hole 5a are not connected. Thus, the IC chip may be mounted not only by wire bonding but also by flip chip connection. Of course, even in the case of flip chip connection, as in the example shown in FIG. 13B, the entire surface may be sealed with the sealing resin 7 to flatten the upper surface. In this case, the upper surface can be flattened, which contributes to printing and stable placement, as well as the effect of reducing the overall thickness.

  In addition, this invention is not limited only to the said embodiment. Various modifications can be made without departing from the spirit of the present invention.

  For example, in the above description, the example of the through-hole is used as the interlayer connection conductor. However, instead of the through-hole, a substantially conical conductor bump may be made conductive by penetrating the interlayer insulating layer and plastically deforming. By aligning the conductor bumps in each layer so as to be laminated with each other, even in the case of conductor bumps, interlayer connection can be made without taking up an extra area. Of course, it is not necessary to penetrate all the wiring layers, and only necessary wiring layers may be connected by through holes or conductor bumps.

  In the above description, the antenna wiring layer has been described as having four layers, but it is not necessary to have four layers, and three or five or more layers may be used. In the case of a multilayer of five or more layers, the wiring region (the rest of the four corners) described above as the dummy pattern can be used to form connection terminals and through-holes with the increased number of antenna patterns. Further, only one through hole penetrating the outside of the spiral cannot be formed at one corner, and two or more through holes may be provided at the same corner. Even in such a case, if the conductor patterns around the through hole are not electrically connected to each other, the multi-layer antenna pattern is electrically connected in series without short-circuiting in the middle, and one antenna having both ends exposed to the uppermost layer. A coil can be constructed. Even when the wiring layer on which the antenna pattern is formed is an odd number, the wiring layer needs to be an even number in order to connect both ends of the antenna coil to both electrode terminals of the IC chip. In that case, one of the wiring layers is simply a wiring pattern for connecting a jumper without an antenna pattern.

  Further, the numerical values such as the specific size and thickness described above are examples in the optimal embodiment of the present invention, and the scope of the present invention is not limited to these numerical values.

  According to the present invention, an RFID tag that communicates by an electromagnetic induction method such as the 13.56 MHz band can be made much smaller than an IC card while ensuring a necessary inductance value. For example, a 5 mm square RFID tag can be provided in the 13.56 MHz band. Thereby, since the RFID tag can be attached to various things, it can be expected that the use of the RFID tag is further expanded and used in various industries.

The figure which looked at the RFID tag which concerns on the 1st Embodiment of this invention from the surface (IC chip mounting surface) side. The top view which looked at the RFID tag of FIG. 1 from the back side. The top view which looked at the state before resin sealing of the RFID tag of FIG. 1 from the surface side. FIG. 2 is an exploded perspective view schematically showing the configuration of the RFID tag in FIG. 1. FIG. 2 is a horizontal sectional view showing a first wiring layer of the RFID tag in FIG. 1. The horizontal sectional view showing the 2nd wiring layer of the RFID tag of FIG. The horizontal sectional view showing the 3rd wiring layer of the RFID tag of FIG. The horizontal sectional view showing the 4th wiring layer of the RFID tag of FIG. The equivalent circuit schematic of the RFID tag of FIG. The figure which shows notionally that many RFID tags were formed in one mounting board | substrate. The figure which shows the outline of the manufacturing process of the RFID tag which concerns on the 1st Embodiment of this invention. The figure which shows the continuation of the manufacturing process shown in FIG. The vertical sectional view showing the outline of the manufacturing process of the RFID tag concerning other embodiments of the present invention. The figure which looked at the IC chip mounting area vicinity of the RFID tag when flip-chip connecting an IC chip from the surface side. The figure which shows the modification of FIG. FIG. 15 is a vertical sectional view showing the RFID tag of FIG. 14.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... IC chip, 2 ... Antenna coil, 3a, 3b ... Chip electrode terminal, 4 ... Low profile wire, 5a, 5b ... Inner through-hole, 6a, 6b ... Outer through-hole, 7 ... Sealing resin, 8 ... Solder resist, 9 ... Chip connection bumps, 10, 20, 30, 40 ... Unit antenna substrate, 11, 21, 31, 41 ... One main surface of insulating substrate, 12, 22, 32, 42 ... Antenna pattern, 12a, 22a, 32a, 42a ... inner end of spiral of antenna pattern, 12b, 22b, 32b, 42b ... outer end of spiral of antenna pattern, 13, 23, 33, 43 ... inner connection terminal, 14, 24, 34, 44 ... Outer connection terminals, 15... Chip mounting pads, 16 a and 16 b... Chip connection terminals, 100.

Claims (9)

  1. A spiral antenna pattern is formed, leaving four corners on at least one surface of a rectangular insulating substrate, and inside the antenna pattern spiral and one of the four corners of the insulating substrate, respectively, on the inner end or outer end of the antenna pattern, respectively. A unit antenna substrate formed by forming connected connection terminals,
    A plurality of layers are laminated via an insulating layer, and each connection terminal is connected via an interlayer connection conductor.
    Each antenna pattern is connected in series to form an antenna coil having both terminals on the uppermost unit antenna substrate surface,
    An IC chip is mounted in the spiral of the antenna pattern on the uppermost layer of the laminated unit antenna substrate,
    Ri Na by connecting both ends of the antenna coil electrically the IC chip, and spiral in primary coil portions when viewed from one surface of the antenna pattern, the mutually opposing to isosamples through said insulating layer A featured RFID tag.
  2.   The RFID tag according to claim 1, wherein the planar shape of the insulating substrate is substantially square.
  3.   The RFID tag according to claim 1 or 2, wherein each antenna pattern has an octagonal shape.
  4.   4. The RFID tag according to claim 1, wherein the spiral of each antenna pattern is formed such that main coil portions overlap each other when seen through from one surface. 5.
  5.   The RFID tag according to any one of claims 1 to 4, wherein the interlayer connection conductor is a through-hole penetrating all layers.
  6.   The RFID tag according to claim 5, wherein the through-hole is filled with a conductive material.
  7.   7. The RFID tag according to claim 1, wherein the IC chip, the interlayer connection conductor, and the IC chip connected to both ends of the antenna coil are sealed with a sealing resin. .
  8.   The interlayer connection conductor disposed in the spiral of the antenna pattern on the uppermost layer of the stacked unit antenna substrates is disposed at a position where a part or all of the interlayer connection conductor is hidden under the IC chip. The RFID tag according to any one of claims 1 to 7.
  9.   9. The RFID according to claim 1, wherein the uppermost layer of the stacked unit antenna substrates is entirely sealed with a sealing resin, and an upper surface thereof is flattened. tag.
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