JP4819150B2 - セラミック基板の電極パターン形成方法 - Google Patents
セラミック基板の電極パターン形成方法 Download PDFInfo
- Publication number
- JP4819150B2 JP4819150B2 JP2009180968A JP2009180968A JP4819150B2 JP 4819150 B2 JP4819150 B2 JP 4819150B2 JP 2009180968 A JP2009180968 A JP 2009180968A JP 2009180968 A JP2009180968 A JP 2009180968A JP 4819150 B2 JP4819150 B2 JP 4819150B2
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- JP
- Japan
- Prior art keywords
- ceramic substrate
- pattern
- electrode pattern
- conductive adhesive
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06755—Material aspects
- G01R1/06761—Material aspects related to layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/143—Masks therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
200 マスク
110 導電性接着パターン
120 メッキシード層
130 感光膜
130a 感光膜パターン
140 メッキ層
300 電極パターン
Claims (8)
- セラミック基板上に互いに離間された複数の導電性接着パターンを設けるステップと、
前記セラミック基板上に前記導電性接着パターンを覆うメッキシード層を設けるステップと、
前記メッキシード層上に前記導電性接着パターンと対応する部分を露出させる感光膜パターンを設けるステップと、
前記感光膜パターンにより露出された前記メッキシード層上にメッキ層を設けるステップと、
前記感光膜パターンを除去するステップと、
前記感光膜パターンが除去されて露出された前記メッキシード層の部分をエッチングするステップと、
を含むセラミック基板の電極パターン形成方法。 - 前記セラミック基板が、LTCC基板である請求項1に記載のセラミック基板の電極パターン形成方法。
- 前記セラミック基板上に互いに離間された複数の導電性接着パターンを設けるステップが、
前記セラミック基板上に、前記導電性接着パターンが設けられた領域と対応する部分が穿孔されているマスクを設けるステップと、
前記マスクにより露出された前記セラミック基板上に導電性接着パターンを蒸着するステップと、
前記マスクを除去するステップと、
を備える請求項1に記載のセラミック基板の電極パターン形成方法。 - 前記マスクが、金属、ガラス、アクリル及びフォトレジストのうちのいずれか一つの材質からなる請求項3に記載のセラミック基板の電極パターン形成方法。
- 前記導電性接着パターンが、Tiの蒸着によって設けられる請求項3に記載のセラミック基板の電極パターン形成方法。
- 前記メッキシード層が、Cuによって構成される請求項1に記載のセラミック基板の電極パターン形成方法。
- 前記メッキ層が、Cu、Ni及びAuのうちの少なくともいずれか一つを含む請求項1に記載のセラミック基板の電極パターン形成方法。
- 前記感光膜パターンが除去されて露出された前記メッキシード層の部分をエッチングするステップで、
pHが6〜7のエッチング液を用いて前記メッキシード層をエッチングする請求項1に記載のセラミック基板の電極パターン形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2009-0048593 | 2009-06-02 | ||
KR1020090048593A KR101003615B1 (ko) | 2009-06-02 | 2009-06-02 | 세라믹 기판의 전극패턴 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010283318A JP2010283318A (ja) | 2010-12-16 |
JP4819150B2 true JP4819150B2 (ja) | 2011-11-24 |
Family
ID=43219068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009180968A Expired - Fee Related JP4819150B2 (ja) | 2009-06-02 | 2009-08-03 | セラミック基板の電極パターン形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8198198B2 (ja) |
JP (1) | JP4819150B2 (ja) |
KR (1) | KR101003615B1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9128123B2 (en) | 2011-06-03 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer test structures and methods |
KR101214734B1 (ko) * | 2011-08-05 | 2012-12-21 | 삼성전기주식회사 | 박막 전극 세라믹 기판 및 이의 제조방법 |
KR101865799B1 (ko) * | 2011-11-07 | 2018-06-08 | 삼성전기주식회사 | 인쇄회로기판 및 그의 제조방법 |
US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
KR101567580B1 (ko) | 2015-07-24 | 2015-11-12 | 한국기계연구원 | 유연 접속 구조물 및 그 제조 방법 |
KR101719145B1 (ko) * | 2015-11-12 | 2017-03-23 | 백종호 | 플라즈마 광원 시스템용 무전극 플라즈마 광원 소켓 베이스 성형방법 |
KR101959381B1 (ko) * | 2016-08-18 | 2019-03-18 | 한국생산기술연구원 | C4f8 가스 중합을 이용한 실리카 파이버 어레이용 그루브의 제조방법 |
US20180337391A1 (en) * | 2017-05-18 | 2018-11-22 | GM Global Technology Operations LLC | Pressing process of creating a patterned surface on battery electrodes |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000323845A (ja) | 1999-05-14 | 2000-11-24 | Sony Corp | 電子回路実装用基板の製造方法 |
JP4467171B2 (ja) | 2000-11-30 | 2010-05-26 | 京セラ株式会社 | セラミック配線基板の製造方法 |
WO2002096166A1 (en) * | 2001-05-18 | 2002-11-28 | Corporation For National Research Initiatives | Radio frequency microelectromechanical systems (mems) devices on low-temperature co-fired ceramic (ltcc) substrates |
JP2007250929A (ja) * | 2006-03-17 | 2007-09-27 | Koa Corp | Ltcc基板上の配線形成方法 |
KR100771783B1 (ko) | 2006-09-28 | 2007-10-30 | 삼성전기주식회사 | 무수축 세라믹 기판의 제조방법 |
US7943510B2 (en) * | 2007-09-10 | 2011-05-17 | Enpirion, Inc. | Methods of processing a substrate and forming a micromagnetic device |
US20090107851A1 (en) * | 2007-10-10 | 2009-04-30 | Akira Kodera | Electrolytic polishing method of substrate |
-
2009
- 2009-06-02 KR KR1020090048593A patent/KR101003615B1/ko active IP Right Grant
- 2009-07-23 US US12/458,834 patent/US8198198B2/en not_active Expired - Fee Related
- 2009-08-03 JP JP2009180968A patent/JP4819150B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8198198B2 (en) | 2012-06-12 |
US20100301009A1 (en) | 2010-12-02 |
KR20100129968A (ko) | 2010-12-10 |
JP2010283318A (ja) | 2010-12-16 |
KR101003615B1 (ko) | 2010-12-23 |
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