JP4802338B2 - 多層基板の製造方法及び多層基板 - Google Patents
多層基板の製造方法及び多層基板 Download PDFInfo
- Publication number
- JP4802338B2 JP4802338B2 JP2008232073A JP2008232073A JP4802338B2 JP 4802338 B2 JP4802338 B2 JP 4802338B2 JP 2008232073 A JP2008232073 A JP 2008232073A JP 2008232073 A JP2008232073 A JP 2008232073A JP 4802338 B2 JP4802338 B2 JP 4802338B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder resist
- multilayer substrate
- resist layer
- metal foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明の一実施例による多層基板の製造方法を示すフローチャートであり、図2乃至図12は、本発明の一実施例による多層基板の製造方法の各工程を示す断面図である。
220 分離層
230 第1ソルダレジスト層
240 金属箔
250 メッキレジスト
261 回路パターン
280 ビアホール
290 第2ソルダレジスト層
270 絶縁部
300 回路積層ユニット
Claims (6)
- 支持体から離型可能な分離層を形成する段階と、
前記分離層上に第1ソルダレジスト層を形成する段階と、
前記第1ソルダレジスト層上に金属箔を積層する段階と、
前記金属箔上に回路パターンを形成する段階と、
前記第1ソルダレジスト層上に前記回路パターンを覆うように絶縁部を形成する段階と、
前記絶縁部上に第2ソルダレジスト層を形成する段階と、
前記分離層と前記支持体とを離隔することにより、前記第1ソルダレジスト層、前記金属箔、前記回路パターン、前記絶縁部、及び前記第2ソルダレジスト層を含む回路積層ユニットであって前記第1ソルダレジスト層及び前記第2ソルダレジスト層が最外層として形成されている回路積層ユニットを前記支持体から分離する段階と、
を含む多層基板の製造方法。 - 前記金属箔上に前記回路パターンを形成する段階が、
前記金属箔上に前記回路パターンに対応するメッキレジストを形成する段階と、
前記メッキレジストが形成された前記金属箔上にメッキ層を形成する段階と、
前記メッキレジストを除去する段階と、
フラッシュエッチング(flash etching)して前記金属箔を除去する段階と、
を含む請求項1に記載の多層基板の製造方法。 - 前記支持体が、銅張積層板(CCL、copper clad laminate)であることを特徴とする請求項1または2に記載の多層基板の製造方法。
- 前記第1ソルダレジスト層の一面には粗さ(roughness)が形成され、
前記金属箔は前記一面に対向して積層される請求項1から3のいずれか一項に記載の多層基板の製造方法。 - 前記支持体上に前記分離層を形成する段階は、
前記分離層が、前記支持体の一面及び他面の両方ともに対称的に形成されることを特徴とする請求項1から4のいずれか一項に記載の多層基板の製造方法。 - 前記絶縁部が、複数の単位絶縁層を含むことを特徴とする請求項1から5のいずれか一項に記載の多層基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080027073A KR100957787B1 (ko) | 2008-03-24 | 2008-03-24 | 다층 기판 제조 방법 및 다층 기판 |
KR10-2008-0027073 | 2008-03-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009231792A JP2009231792A (ja) | 2009-10-08 |
JP4802338B2 true JP4802338B2 (ja) | 2011-10-26 |
Family
ID=41087760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008232073A Expired - Fee Related JP4802338B2 (ja) | 2008-03-24 | 2008-09-10 | 多層基板の製造方法及び多層基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8051559B2 (ja) |
JP (1) | JP4802338B2 (ja) |
KR (1) | KR100957787B1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101067152B1 (ko) * | 2009-11-12 | 2011-09-22 | 삼성전기주식회사 | 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법 |
KR101106927B1 (ko) * | 2009-11-30 | 2012-01-25 | 주식회사 심텍 | 초박형 코어리스 플립칩 칩 스케일 패키지의 제조 방법 |
KR101055570B1 (ko) * | 2009-12-02 | 2011-08-08 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
US20110195223A1 (en) * | 2010-02-11 | 2011-08-11 | Qualcomm Incorporated | Asymmetric Front/Back Solder Mask |
KR101109216B1 (ko) * | 2010-03-03 | 2012-01-30 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
DE102010031945A1 (de) * | 2010-07-22 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
KR101983191B1 (ko) * | 2017-07-25 | 2019-05-28 | 삼성전기주식회사 | 인덕터 및 그 제조방법 |
KR102257926B1 (ko) | 2018-09-20 | 2021-05-28 | 주식회사 엘지화학 | 다층인쇄회로기판, 이의 제조방법 및 이를 이용한 반도체 장치 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61236192A (ja) * | 1985-04-12 | 1986-10-21 | 株式会社日立製作所 | セラミツク基板の電極形成方法 |
JPH06318783A (ja) * | 1993-05-10 | 1994-11-15 | Meikoo:Kk | 多層回路基板の製造方法 |
US5699613A (en) * | 1995-09-25 | 1997-12-23 | International Business Machines Corporation | Fine dimension stacked vias for a multiple layer circuit board structure |
JP2000101245A (ja) * | 1998-09-24 | 2000-04-07 | Ngk Spark Plug Co Ltd | 積層樹脂配線基板及びその製造方法 |
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
KR100366411B1 (ko) * | 2000-04-11 | 2002-12-31 | 엘지전자 주식회사 | 다층 인쇄회로기판 및 그 제조방법 |
KR100743231B1 (ko) * | 2001-05-10 | 2007-07-27 | 엘지전자 주식회사 | 인쇄회로기판의 제조방법 |
JP3925378B2 (ja) * | 2002-09-30 | 2007-06-06 | ソニー株式会社 | 高周波モジュール装置の製造方法。 |
US6670009B1 (en) * | 2002-12-13 | 2003-12-30 | Industrial Label Corporation | Multi-layer extended text resealable label |
KR100674319B1 (ko) * | 2004-12-02 | 2007-01-24 | 삼성전기주식회사 | 얇은 코어층을 갖는 인쇄회로기판 제조방법 |
-
2008
- 2008-03-24 KR KR1020080027073A patent/KR100957787B1/ko active IP Right Grant
- 2008-09-10 JP JP2008232073A patent/JP4802338B2/ja not_active Expired - Fee Related
- 2008-09-24 US US12/232,820 patent/US8051559B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8051559B2 (en) | 2011-11-08 |
US20090236125A1 (en) | 2009-09-24 |
JP2009231792A (ja) | 2009-10-08 |
KR100957787B1 (ko) | 2010-05-12 |
KR20090101746A (ko) | 2009-09-29 |
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