JP4711670B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). In the special game, based on the detection of the game ball passing through the start winning opening (the variable display start condition is satisfied), the display symbol update display (for example, scroll display) is performed, and the display symbol update display is performed. In this game, the “hit” is defined as a case where the stop symbol form when completely stopped is a predetermined display form. Whether or not the special game is “big hit” is determined before the display result is displayed depending on whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. . When a “big hit” is reached, a special electric combination called a big winning opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time.

  In such a gaming machine, as a method for generating a random number (big hit determination random number) used for determining whether or not to make a “big hit”, a method in which a CPU executes a predetermined application program is known. ing. However, such a random number generation method has a problem that the processing load of the CPU at the time of generation increases.

To solve this problem, a random number circuit is used to generate a big hit determination random number, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. A gaming machine that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, Patent Document 1).
JP 7-124296 A (page 3-4, FIG. 1)

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). There has also been proposed a gaming machine or the like that can generate a random number by hardware by storing it as a random value (for example, Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2)

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  In the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gradual, the rising edge of the inverted clock pulse also becomes gradual. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse is output. There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  In addition, in these conventional techniques, it is difficult to recognize that a failure has occurred in the configuration for outputting random values, and there is a possibility that the player may suffer a significant disadvantage.

  The present invention has been made in view of the above-described situation, and a game that can reliably and stably acquire a random value and can estimate the occurrence of a failure in the configuration for outputting the random value. The purpose is to provide a machine.

In order to achieve the above object, the gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Reference clock signal output means (for example, reference clock signal output circuit 171) and clock signal generation means (for example, clock signal generation circuit 175) for generating a plurality of signals having the same period and different phases based on the reference clock signal. The clock signal generation means receives the reference clock signal from the reference clock signal output means. A clock terminal (for example, an input terminal CK of the clock signal generation circuit 175), an input terminal to which the first signal is input (for example, an input terminal D of the clock signal generation circuit 175), and a change state of the first signal. A signal synchronized with a timing (for example, timing T10, T11,..., When the reference clock signal S1 rises from a low level to a high level) that changes every predetermined cycle of the reference clock signal input from the clock terminal. A first output terminal that outputs (for example, a positive phase output terminal Q of the clock signal generation circuit 175) and a second output that outputs a signal having the same period and a different phase from the signal output from the first output terminal. Terminal (for example, a reverse phase output terminal Q (bar) of the clock signal generation circuit 175), and the clock signal generation means includes the second output terminal. And the input terminal, the first clock signal output from the first output terminal (e.g., the counting clock signal S2) and the second output terminal output the first clock signal. A second clock signal (for example, a latching clock signal S3) having the same period and a different phase from the clock signal, and the random number generating means generates the first clock signal generated by the clock signal generating means. Numerical data update for updating numerical data (for example, count value C) at a first timing that changes in a predetermined manner (for example, timings T10, T12,... When count clock signal S2 rises from a low level to a high level) Means (for example, counter 174) and the second clock signal generated by the clock signal generating means At a second timing that changes in a manner (for example, timings T11, T13,... When the latch clock signal S3 rises from a low level to a high level, etc.), the start signal input from the start signal output means is a latch signal (for example, In response to the latch signal output means (for example, latch signal output circuit 173) that outputs as the latch signal SL) and the latch signal input from the latch signal output means, the numerical data updated by the numerical data update means is disturbed. Random number storage means (for example, random value storage circuit 179) for storing as a numerical value (for example, random value R1), the game control means, based on the start signal input from the start signal output means, The random number value is read from the random value storage means, and the read random number value is set to predetermined determination value data (for example, “ Display result determining means (for example, the CPU 103 determines whether or not the display result in the variable display is set as the specific display result by determining whether or not it matches “001 to 2184” or “2001 to 3104”). The portion for executing the start winning process in step S15 and the jackpot determination process in step S111) and numerical data updated in synchronization with the numerical data updated by the numerical data updating means (for example, the reach determination random value R2). Whether or not the numerical data acquisition means to be acquired (for example, the part where the CPU 103 executes the process of step S244) and the numerical data acquired by the numerical data acquisition means match predetermined performance determination value data (for example, “8”). Is determined to determine whether or not to execute a predetermined effect (for example, CPU 1). 03 is a part for executing the processing of step S245), and before the display result determination means reads out the random value from the random value storage means, an output control signal (for example, output control signal SC) is output to the random value storage means. The random value storage means is controlled to be readable, and after the display result determining means reads the random value from the random value storage means, the output of the output control signal to the random value storage means is stopped. and read control means for controlling the reading disabled state of the random numeric storage unit (e.g., the portion CPU103 is executing the processing of step S204, S207), only contains the random number storage means, output control from the reading control means Read priority means (for example, AND circuit 201) that prohibits updating of the stored random number value even when a latch signal is output from the latch signal output means when a signal is input Including.

In order to achieve the above object, the gaming machine according to claim 2 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Reference clock signal output means (for example, reference clock signal output circuit 171) and a plurality of timings (for example, reference clock signal for which the reference clock signal output from the reference clock signal output means changes in a predetermined manner every predetermined period. The first of the timings T20, T30,..., When S1 rises from the low level to the high level Numerical timing updating means (for example, a counter 174) for updating numerical data (for example, a count value C) at a timing (for example, timings T20, T21,...) And a first timing different from the first timing among the plurality of timings. Latch signal output means (for example, latch signal output circuit 173) that outputs a start signal input from the start signal output means as a latch signal (for example, latch signal SL) at a timing of 2 (for example, timing T30, T31,...). And, in response to a latch signal input from the latch signal output means, random number storage means (for example, a random value storage circuit) that stores numerical data updated by the numerical value update means as a random number value (for example, random value R1) 179), and the game control means receives a start signal from the start signal output means. Is read from the random value storage means, and the read random number value matches predetermined determination value data (for example, “2001 to 2184”, “2001 to 3104”, etc.). Display result determining means for determining whether or not the display result in the variable display is a specific display result (for example, the CPU 103 executes the start winning process in step S15 and the big hit determination process in step S111). And numerical data acquisition means (for example, the CPU 103 performs the process of step S244) for acquiring numerical data (for example, the reach determination random value R2) updated in synchronization with the numerical data updated by the numerical data update means. And the numerical data acquired by the numerical data acquisition means are predetermined performance determination value data. (E.g., "8") by determining whether they meet the, the effect determination unit for determining whether to perform a predetermined effect (e.g. a portion CPU103 executes the process of step S245), the display Before the result determining means reads the random value from the random value storage means, an output control signal (for example, an output control signal SC) is output to the random value storage means to control the random value storage means to be readable. Read control means for controlling output of the random value storage means to an unreadable state by stopping output of an output control signal to the random value storage means after the display result determining means reads the random value from the random value storage means (e.g. part CPU103 is executing the processing of step S204, S207), seen including, said random number storage means, when the output control signal from said read control means is inputted, said La Including a read priority means for inhibiting updating of the random numbers latch signal from the switch signal output means is stored be output (for example, AND circuit 201).

In order to achieve the above-mentioned object, the gaming machine according to claim 3 of the present application has a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Delayed clock signal by delaying a reference clock signal output means (for example, reference clock signal output circuit 171) and a reference clock signal input from the reference clock signal output means by a period different from an integer multiple of the predetermined period. Clock signal delay means for generating (for example, delayed clock signal S7) and outputting the generated delayed clock signal For example, a delay circuit 178) and a first timing at which the reference clock signal input from the reference clock signal output means changes in a predetermined manner every predetermined cycle (for example, the reference clock signal S1 changes from low level to high level). And the second timing at which the delayed clock signal input from the clock signal delay means changes in a predetermined manner every predetermined cycle (for example, the delayed clock signal S7 is changed from the low level). Numerical value updating means (for example, counter 174) for updating numerical data (for example, count value C) and the first timing at any one of timings T50, T51,. And the second timing, the numerical data is updated by the numerical value updating means. Latch signal output means (for example, latch signal output circuit 173) for outputting a start signal input from the start signal output means as a latch signal (for example, latch signal SL) at a timing different from the updated timing; and the latch signal Random value storage means (for example, a random value storage circuit 179) that stores numerical data updated by the numerical value updating means as a random value (for example, random number value R1) in response to a latch signal input from the output means. The game control means reads a random number value from the random value storage means based on the input of the start signal from the start signal output means, and the read random number value is a predetermined judgment value data (for example, “ 2001 ”to“ 2184 ”,“ 2001 to 3104 ”, etc.) Display result determining means for determining whether or not the display result is a specific display result (for example, a portion where the CPU 103 executes the start winning process in step S15 and the jackpot determination process in step S111) and the numerical data updating means Numerical data acquisition means (for example, a portion where the CPU 103 executes the processing of step S244) for acquiring numerical data (for example, reach determination random number R2) that is updated in synchronization with the numerical data to be processed, and the numerical data acquisition means An effect determining means (for example, the CPU 103 determines, for example, whether or not to execute the predetermined effect by determining whether or not the acquired numerical data matches predetermined effect determination value data (for example, “8”)) in step S245. processing and the portions for performing), random number values the display result determining means from the random number storage means Before reading out, the output control signal (eg, output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the display result determination means is read from the random value storage means. After reading the random number value, the output control signal is stopped from being output to the random value storage means, and the random number value storage means is controlled to be in a non-readable state (for example, the CPU 103 executes the processing of steps S204 and S207. a portion) that, only contains the random number storage means when said output control signal from the read control means is input, the random number value latch signal from the latch signal output means is stored be output Read priority means (for example, AND circuit 201 etc.) for prohibiting the update of.

  In the gaming machine according to claim 4, the effect continuous number measuring means for measuring the number of times that the start condition of the variable display for which the predetermined effect is determined by the effect determining means is continuously established ( For example, the reach counter 124 and the portion where the CPU 103 executes the processes of steps S250 and S248) and the variable display start condition in which the predetermined effect is determined not to be executed by the effect determining means are continuously established. The production avoidance frequency measurement means (for example, the part where the normal losing frequency counter 125 and the CPU 103 execute the processes of steps S247 and S251) and the production continuous frequency measurement means count the predetermined production continuous. When the upper limit number is exceeded (for example, when it is determined Yes in step S253), the production continuous upper limit The effect continuous notification control means for performing control to notify that the number has been exceeded (for example, the CPU 103 executes the process of step S254 after executing the process of step S254, so that the process of step S266 is executed. The part in which the production control CPU 105 executes the process of step S142) and the number of times measured by the production avoidance frequency measuring means exceeds a predetermined production avoidance upper limit number (for example, when it is determined Yes in step S255). In addition, an effect avoidance notification control unit that performs control to notify that the effect avoidance upper limit number has been exceeded (for example, the process of step S266 is executed when the CPU 103 determines No in step S261 after executing the process of step S256. In response to this, the production control CPU 105 executes step S142. Comprising a part) and.

  6. The gaming machine according to claim 5, wherein the effect continuous notification control means executes the specific effect (for example, displays an image as shown in FIG. 26 (A)), thereby setting the effect continuous upper limit count. The effect avoidance notifying control unit performs control to notify that the effect has been exceeded, and the effect avoidance upper limit number of times by causing the specific effect to be executed (for example, displaying an image as shown in FIG. 26B). Control is performed to notify the user that the number exceeds.

In order to achieve the above object, the gaming machine according to claim 6 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Reference clock signal output means (for example, reference clock signal output circuit 171) and clock signal generation means (for example, clock signal generation circuit 175) for generating a plurality of signals having the same period and different phases based on the reference clock signal. The clock signal generation means receives the reference clock signal from the reference clock signal output means. A clock terminal (for example, an input terminal CK of the clock signal generation circuit 175), an input terminal to which the first signal is input (for example, an input terminal D of the clock signal generation circuit 175), and a change state of the first signal. A signal synchronized with a timing (for example, timing T10, T11,..., When the reference clock signal S1 rises from a low level to a high level) that changes every predetermined cycle of the reference clock signal input from the clock terminal. A first output terminal that outputs (for example, a positive phase output terminal Q of the clock signal generation circuit 175) and a second output that outputs a signal having the same period and a different phase from the signal output from the first output terminal. Terminal (for example, a reverse phase output terminal Q (bar) of the clock signal generation circuit 175), and the clock signal generation means includes the second output terminal. And the input terminal, the first clock signal output from the first output terminal (e.g., the counting clock signal S2) and the second output terminal output the first clock signal. A second clock signal (for example, a latching clock signal S3) having the same period and a different phase from the clock signal, and the random number generating means generates the first clock signal generated by the clock signal generating means. Numerical data update for updating numerical data (for example, count value C) at a first timing that changes in a predetermined manner (for example, timings T10, T12,... When count clock signal S2 rises from a low level to a high level) Means (for example, counter 174) and the second clock signal generated by the clock signal generating means The start signal input from the start signal output means is output as a latch signal at the second timing (for example, the timing T11, T13,... When the latch clock signal S3 rises from the low level to the high level). In response to a latch signal output means (for example, latch signal output circuit 173) and a latch signal input from the latch signal output means, the numerical data updated by the numerical data update means is converted into a random value (for example, random value R1). ) Stored as random number value storage means (for example, random value storage circuit 179), and the game control means receives random start signal from the start signal output means, A numerical value is read, and the read random number value is set to predetermined determination value data (for example, “2001 to 2184” or “ Display result determining means for determining whether or not the display result in the variable display is set as the specific display result (for example, the CPU 103 starts the winning prize process in step S15). And a portion for executing the jackpot determination process in step S111), a random value holding means (for example, a jackpot determination random value holding area 130) for holding the random value read from the random value storage means, and the random value storage. Means for determining whether or not the random number value read from the means matches the random value held in the random value holding means (for example, the part where the CPU 103 executes the process of step S301); When it is determined that the random number value matching means does not match, a random number value to be held in the random value holding means is newly added to the random value value. The stored random number value updating means (for example, the part where the CPU 103 executes the process of step S303) for updating to the random value read from the numerical value storage means and the random number value coincidence determining means are continuously determined to match. A continuous number counting unit (for example, the coincidence number counter 126), and a continuous number determining unit (for example, determining whether the continuous number counted by the continuous number counting unit exceeds a predetermined continuous upper limit value). The CPU 103 detects that a failure has occurred in the reference clock signal output means when it is determined by the continuous count determination means that the continuous upper limit value has been exceeded. Failure detection means (for example, when CPU 103 determines Yes in step S305) A portion, and so on) that perform the processing of step S306, the display before the result determination unit reads a random number from the random number value storing means, and outputs an output control signal (e.g., the output control signal SC) to the random numeric storage unit The random value storage means is controlled to be readable, and after the display result determination means reads the random value from the random value storage means, the output of the output control signal to the random value storage means is stopped to and read control means for controlling the random number storage means unreadable state (e.g. part CPU103 is executing the processing of step S204, S207), only contains the random number storage means, an output control signal from said read control means Read priority means (for example, AND circuit 201) that prohibits updating of the stored random number value even when a latch signal is output from the latch signal output means. No. Note that the game control means replaces the continuous count counting means and the continuous count determination means with a time measurement means for measuring the elapsed time since the random number value held in the random value holding means is updated by the holding random number update means (for example, (Elapsed time timer) and elapsed time determination means for determining whether or not the elapsed time measured by the time measurement means has reached a predetermined time when the match is determined by the random number value match determination means. In addition, the failure detection means may detect that a failure has occurred in the reference clock signal output means when it is determined by the elapsed time determination means that the predetermined period has been reached.

In order to achieve the above object, the gaming machine according to claim 7 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Reference clock signal output means (for example, reference clock signal output circuit 171) and a plurality of timings (for example, reference clock signal for which the reference clock signal output from the reference clock signal output means changes in a predetermined manner every predetermined period. The first of the timings T20, T30,..., When S1 rises from the low level to the high level A numerical value updating means (for example, a counter 174) for updating numerical data (for example, a count value C) at a timing (for example, timing T20, T21,. Latch signal output means (for example, latch signal output circuit 173) that outputs a start signal input from the start signal output means as a latch signal (for example, latch signal SL) at a timing of 2 (for example, timing T30, T31,...). And, in response to a latch signal input from the latch signal output means, random number storage means (for example, a random value storage circuit) that stores numerical data updated by the numerical value update means as a random number value (for example, random value R1) 179), and the game control means receives a start signal from the start signal output means. Is read from the random value storage means, and the read random number value matches predetermined determination value data (for example, “2001 to 2184”, “2001 to 3104”, etc.). Display result determining means for determining whether or not the display result in the variable display is a specific display result (for example, the CPU 103 executes the start winning process in step S15 and the big hit determination process in step S111). Portion), a random value holding means (for example, a jackpot determination random value holding area 130) for holding a random value read from the random value storage means, and a random value read from the random value storage means. Random value match determination means for determining whether or not the random number value held in the random value holding means matches (for example, the CPU 103 executes step S30). The random number value to be held in the random value holding means is newly read out from the random value storage means when it is determined that the random number value match determining means does not match A continuous random number count that counts the number of times that the random number value matching means (for example, the part where the CPU 103 executes the process of step S303) and the random number value match judgment means continuously make a match is determined. Means (for example, coincidence number counter 126) and continuous number determination means (for example, CPU 103 executes the process of step S305) for determining whether or not the continuous number counted by the continuous number counter exceeds a predetermined continuous upper limit value. And a determination that the continuous upper limit value is exceeded by the continuous number determination means. Te, a failure detection means for detecting that a failure occurs in the reference clock signal output means (e.g. CPU103 and portions for performing the process of step S306 by it is determined Yes at step S305), determines the display result Before the means reads out the random value from the random value storage means, an output control signal (for example, output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the display After the result determining means reads out the random value from the random value storage means, a read control means for stopping the output of the output control signal to the random value storage means and controlling the random value storage means to the unreadable state (for example, CPU103 is a part) to perform the processing of step S204, S207, only contains the random number storage means, an output control signal from said read control means is input Read priority means (for example, an AND circuit 201) that prohibits updating of the stored random number value even when a latch signal is output from the latch signal output means. Note that the game control means replaces the continuous count counting means and the continuous count determination means with a time measurement means for measuring the elapsed time since the random number value held in the random value holding means is updated by the holding random number update means (for example, (Elapsed time timer) and elapsed time determination means for determining whether or not the elapsed time measured by the time measurement means has reached a predetermined time when the match is determined by the random number value match determination means. In addition, the failure detection means may detect that a failure has occurred in the reference clock signal output means when it is determined by the elapsed time determination means that the predetermined period has been reached.

In order to achieve the above object, the gaming machine according to claim 8 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Based on the establishment of the previous variable display and end of jackpot gaming state in the device 4, a variable display device (for example, special display) that variably displays each of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified. A specific game that has a symbol display 4 and an image display device 5) and is advantageous to the player when the display result of variable display becomes a predetermined specific display result (for example, a decisive symbol of a big hit symbol or a big hit combination) A gaming machine (for example, a pachinko gaming machine 1) that is controlled to a state (for example, a big hit gaming state), and a game control means for controlling the progress of the game (for example, for game control mounted on the main board 11) The computer 100), random number generating means for generating random numbers (for example, the random number generating circuit 17), and the start signal (for example, start winning signal SS) is sent to the game control means based on the fact that the execution condition is satisfied. And a start signal output means (for example, a start winning prize switch 70) for outputting to the random number generation means, and the random number generation means generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period. Delayed clock signal by delaying a reference clock signal output means (for example, reference clock signal output circuit 171) and a reference clock signal input from the reference clock signal output means by a period different from an integer multiple of the predetermined period. Clock signal delay means for generating (for example, delayed clock signal S7) and outputting the generated delayed clock signal For example, a delay circuit 178) and a first timing at which the reference clock signal input from the reference clock signal output means changes in a predetermined manner every predetermined cycle (for example, the reference clock signal S1 changes from low level to high level). And the second timing at which the delayed clock signal input from the clock signal delay means changes in a predetermined manner every predetermined cycle (for example, the delayed clock signal S7 is changed from the low level). Numerical value updating means (for example, counter 174) for updating numerical data (for example, count value C) and the first timing at any one of timings T50, T51,. And the second timing, the numerical data is updated by the numerical value updating means. Latch signal output means (for example, latch signal output circuit 173) for outputting a start signal input from the start signal output means as a latch signal (for example, latch signal SL) at a timing different from the updated timing; and the latch signal Random value storage means (for example, a random value storage circuit 179) that stores numerical data updated by the numerical value updating means as a random value (for example, random number value R1) in response to a latch signal input from the output means. The game control means reads a random number value from the random value storage means based on the input of the start signal from the start signal output means, and the read random number value is a predetermined judgment value data (for example, “ 2001 ”to“ 2184 ”,“ 2001 to 3104 ”, etc.) Display result determination means for determining whether or not the display result is a specific display result (for example, the part where the CPU 103 executes the start winning process in step S15 and the jackpot determination process in step S111) and the random value storage means Random value holding means (for example, a jackpot determination random value holding area 130) that holds the random number value that is output, and a random value that is read from the random value storage means and held in the random value holding means The random number value match determination means (for example, the part where the CPU 103 executes the process of step S301) and the random value match determination means determine that they do not match. Holding random number value updating means (for example, CPU) for updating a random value to be held in the holding means to a new random value read out from the random value storage means 03 is a part for executing the process of step S303), a continuous number counting means (for example, the coincidence number counter 126) for counting the number of times that the determination that the random number value coincidence coincides is continuously performed, and the continuous The continuous number determination means for determining whether or not the continuous number counted by the number count means exceeds a predetermined continuous upper limit value (for example, the part where the CPU 103 executes the process of step S305), and the continuous number determination means When it is determined that the continuous upper limit value has been exceeded, failure detection means for detecting that a failure has occurred in the reference clock signal output means (for example, when the CPU 103 determines Yes in step S305, step S306 And the display result determination means is the random number value. Before reading the random value from the storage means, an output control signal (for example, output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the display result determination means After reading the random value from the random value storage means, the output control signal to the random value storage means is stopped and the random number value storage means is controlled to be in a non-readable state (for example, the CPU 103 executes step S204, a portion) that performs the process of S207, only contains the random number storage means when said output control signal from the read control means is input, the latch signal output unit memory even latch signal is output from the Read priority means (for example, an AND circuit 201) that prohibits updating of the random number value being performed. Note that the game control means replaces the continuous count counting means and the continuous count determination means with a time measurement means for measuring the elapsed time since the random number value held in the random value holding means is updated by the holding random number update means (for example, (Elapsed time timer) and elapsed time determination means for determining whether or not the elapsed time measured by the time measurement means has reached a predetermined time when the match is determined by the random number value match determination means. In addition, the failure detection means may detect that a failure has occurred in the reference clock signal output means when it is determined by the elapsed time determination means that the predetermined period has been reached.

  In the gaming machine according to claim 9, when it is detected by the failure detection means that a failure has occurred in the reference clock signal output means (for example, the CPU 103 determines that the failure detection flag is on in step S261). Failure occurrence notification control means (for example, the CPU 103 executes the processing of step S266), and the effect control CPU 105 performs step S266 in response to the failure occurrence notification control means for performing control for notifying that a failure has occurred in the reference clock signal output means. By executing the process of S142, for example, an image as shown in FIG. 31A or a character image 60 as shown in FIG. 31B is displayed on the image display device 5.

  11. The gaming machine according to claim 10, wherein the random number generation means measures a time during which a start signal is input from the start signal output means, and when the measured time reaches a predetermined time (for example, 3 ms). And timer means (for example, timer circuit 172) for outputting the start signal to the latch signal output means.

  12. The gaming machine according to claim 11, wherein the game control means executes timer interrupt processing execution means for executing timer interrupt processing in response to an interrupt request signal input periodically (for example, every 2 ms). For example, the CPU 103 includes a part where the game control interrupt process is executed), and the display result determination unit is executing the timer interrupt process a predetermined number of times (for example, twice) by the timer interrupt process executing unit ( For example, for a period of 4 ms), based on the fact that the start signal is continuously input from the start signal output means, the random number value is read from the random value storage means, and the timer means is predetermined by the timer interrupt processing execution means. Setting means for setting, as the predetermined time, a time shorter than the time at which the timer interrupt processing is executed (for example, 4 m which is the execution time of the timer interrupt processing by the timer circuit 172 twice) Shorter than includes a portion or the like) for setting a 3 ms, when the time measured reaches a time set as the predetermined time by the setting unit, and outputs the start signal to the latch signal output means.

13. The gaming machine according to claim 12 , wherein when the latch signal is input from the latch signal output means, the random value storage means is in a state incapable of receiving the output control signal output from the read control means. Output control signal reception control means for controlling (for example, an AND circuit 203) is included.

  The present invention has the following effects.

According to the configuration of the first aspect, it is determined whether or not to execute a predetermined effect based on numerical data updated in synchronization with the random value read from the random value storage means. Therefore, when a predetermined effect is not executed over a long period of time, or when a predetermined effect is executed over a long period of time, it can be estimated that a failure has occurred in the random number generation means, and a failure has occurred in the random number generation means It is possible to prevent the player from suffering a significant disadvantage. Here, by setting the probability that the predetermined effect is executed higher than the probability that the variable display result of the identification information becomes the specific display result, the random number generating means malfunctions when the specific display result is not obtained over a long period of time. It is possible to estimate the occurrence of a failure within a shorter period than when it is estimated that the error has occurred.
Further, since a special configuration for monitoring the random number value read from the random value storage means is not necessary, an increase in manufacturing cost can be suppressed.
Further, the random number generation means generates the first clock signal and the second clock signal having the same period and different phases without inverting the reference clock signal output from the reference clock signal output means, The numerical data is updated at the first timing when the clock signal changes in a predetermined manner, and the latch signal is output at the second timing when the second clock signal changes in the predetermined manner. In this way, the random number generation means can reliably change the update timing of the numerical data and the latch timing of the numerical data, so that the game control means can reliably and stably acquire the random value. Can do.
In addition, the signal output from the first output terminal is synchronized with the timing at which the change state of the first signal input to the input terminal changes every predetermined period of the reference clock signal input from the clock terminal. It is a signal. The signal output from the second output terminal is a signal having the same period and a different phase from the signal output from the first output terminal.
Thereby, the rising edge and the falling edge in the first clock signal that determines the timing at which the numerical data updating means updates the numerical data and the second clock signal that determines the timing at which the latch signal output means outputs the latch signal are: Even if the rising edge or falling edge of the reference clock signal is gradual, it can be made steep so that the update timing of numerical data and the output timing of the latch signal can be stabilized to obtain random values. Can be reliably and stably performed. In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

According to the configuration described in claim 2, it is determined whether or not to execute a predetermined effect based on numerical data updated in synchronization with the random value read from the random value storage means. Therefore, when a predetermined effect is not executed over a long period of time, or when a predetermined effect is executed over a long period of time, it can be estimated that a failure has occurred in the random number generation means, and a failure has occurred in the random number generation means It is possible to prevent the player from suffering a significant disadvantage. Here, by setting the probability that the predetermined effect is executed higher than the probability that the variable display result of the identification information becomes the specific display result, the random number generating means malfunctions when the specific display result is not obtained over a long period of time. It is possible to estimate the occurrence of a failure within a shorter period than when it is estimated that the error has occurred.
Further, since a special configuration for monitoring the random number value read from the random value storage means is not necessary, an increase in manufacturing cost can be suppressed.
Further, the random number generation means does not invert the reference clock signal output from the reference clock signal output means, and the first timing among the plurality of timings at which the reference clock signal changes in a predetermined manner every predetermined cycle. The numerical data is updated by the numerical value updating means, and the start signal input from the start signal output means is output as a latch signal at a second timing different from the first timing among a plurality of timings. it can. For this reason, acquisition of a random value can be performed reliably and stably. In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

According to the configuration described in claim 3, it is determined whether or not to execute a predetermined effect based on numerical data updated in synchronization with the random value read from the random value storage means. Therefore, when a predetermined effect is not executed over a long period of time, or when a predetermined effect is executed over a long period of time, it can be estimated that a failure has occurred in the random number generation means, and a failure has occurred in the random number generation means It is possible to prevent the player from suffering a significant disadvantage. Here, by setting the probability that the predetermined effect is executed higher than the probability that the variable display result of the identification information becomes the specific display result, the random number generating means malfunctions when the specific display result is not obtained over a long period of time. It is possible to estimate the occurrence of a failure within a shorter period than when it is estimated that the error has occurred.
Further, since a special configuration for monitoring the random number value read from the random value storage means is not necessary, an increase in manufacturing cost can be suppressed.
Further, the random number generation means includes a first timing at which the reference clock signal changes in a predetermined manner every predetermined cycle and the clock signal delay means without inverting the reference clock signal output from the reference clock signal output means. Numerical data is updated by the numerical value updating means at any one of the second timing at which the input delayed clock signal changes in a predetermined manner every predetermined cycle, and the first timing and the second timing are updated. The start signal input from the start signal output means is output as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means. Thereby, the update timing of the numerical data by the numerical value updating means and the output timing of the latch signal can be reliably made different, so that the random value can be acquired reliably and stably. In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

  In the configuration according to claim 4, when the number of times of the production continuous number of times exceeds the production continuous upper limit number of times, the production continuous notification control unit performs control to notify that effect, and the production avoidance frequency measurement unit. When the number of times measured by exceeds the effect avoidance upper limit count, control to notify that effect is performed by the effect avoidance notification control means. By this notification, the player can easily recognize that a failure has occurred in the random number generation means, and can be prevented from suffering a disadvantage.

  In the configuration according to claim 5, it is informed that the predetermined effect means has executed a specific effect and the effect continuous upper limit has been exceeded, and by executing an effect whose effect mode is different from the specific effect. It is notified that the maximum number of production avoidances has been exceeded. By this notification, the player can easily recognize that a failure has occurred in the random number generation means, and can be prevented from suffering a disadvantage.

According to the configuration of the sixth aspect, the determination that the random number value read from the random value storage unit matches the random value stored in the random number storage unit is continuously performed by the random value match determination unit. The number of times made is counted by the continuous number counting means. Then, when the continuous number determining means determines that the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit value, the failure detecting means detects that a failure has occurred in the reference clock signal output means. To do. Thereby, when a failure occurs in the reference clock signal output means included in the random number generation means, it is possible to prevent the player from receiving a significant disadvantage.
Further, the random number generation means generates the first clock signal and the second clock signal having the same period and different phases without inverting the reference clock signal output from the reference clock signal output means, The numerical data is updated at the first timing when the clock signal changes in a predetermined manner, and the latch signal is output at the second timing when the second clock signal changes in the predetermined manner. In this way, the random number generation means can reliably change the update timing of the numerical data and the latch timing of the numerical data, so that the game control means can reliably and stably acquire the random value. Can do.
In addition, the signal output from the first output terminal is synchronized with the timing at which the change state of the first signal input to the input terminal changes every predetermined period of the reference clock signal input from the clock terminal. It is a signal. The signal output from the second output terminal is a signal having the same period and a different phase from the signal output from the first output terminal.
Thereby, the rising edge and the falling edge in the first clock signal that determines the timing at which the numerical data updating means updates the numerical data and the second clock signal that determines the timing at which the latch signal output means outputs the latch signal are: Even if the rising edge or falling edge of the reference clock signal is gradual, it can be made steep so that the update timing of numerical data and the output timing of the latch signal can be stabilized to obtain random values. Can be reliably and stably performed.
In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

According to the configuration of the seventh aspect, the determination that the random number value read from the random value storage unit matches the random value stored in the random number storage unit is continuously performed by the random value match determination unit. The number of times made is counted by the continuous number counting means. Then, when the continuous number determining means determines that the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit value, the failure detecting means detects that a failure has occurred in the reference clock signal output means. To do. Thereby, when a failure occurs in the reference clock signal output means included in the random number generation means, it is possible to prevent the player from receiving a significant disadvantage.
Further, the random number generation means does not invert the reference clock signal output from the reference clock signal output means, and the first timing among the plurality of timings at which the reference clock signal changes in a predetermined manner every predetermined cycle. The numerical data is updated by the numerical value updating means, and the start signal input from the start signal output means is output as a latch signal at a second timing different from the first timing among a plurality of timings. it can. For this reason, acquisition of a random value can be performed reliably and stably. In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

According to the configuration of the eighth aspect, the determination that the random number value read from the random value storage unit matches the random value stored in the random number storage unit is continuously performed by the random value match determination unit. The number of times made is counted by the continuous number counting means. Then, when the continuous number determining means determines that the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit value, the failure detecting means detects that a failure has occurred in the reference clock signal output means. To do. Thereby, when a failure occurs in the reference clock signal output means included in the random number generation means, it is possible to prevent the player from receiving a significant disadvantage.
Further, the random number generation means includes a first timing at which the reference clock signal changes in a predetermined manner every predetermined cycle and the clock signal delay means without inverting the reference clock signal output from the reference clock signal output means. Numerical data is updated by the numerical value updating means at any one of the second timing at which the input delayed clock signal changes in a predetermined manner every predetermined cycle, and the first timing and the second timing are updated. The start signal input from the start signal output means is output as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means. Thereby, the update timing of the numerical data by the numerical value updating means and the output timing of the latch signal can be reliably made different, so that the random value can be acquired reliably and stably. In addition, according to this configuration, the game control means reads out the random number value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing.
Furthermore, since the random value storage means can be made readable only when the display result determining means reads the random value, the random value can be acquired reliably and stably.
The random number generation means prevents the random number value stored in the random value storage means from being updated when the display result determination means reads the random value from the random value storage means. Acquisition can be performed reliably and stably.

  According to the ninth aspect of the present invention, when the failure detecting means detects that a failure has occurred in the reference clock signal output means, the failure occurrence notifying control means notifies that a failure has occurred. By this notification, the player can easily recognize that a failure has occurred in the random number generation means, and can be prevented from suffering a disadvantage.

  In the configuration of the tenth aspect, instead of directly inputting the start signal output from the start signal output means to the latch signal output means, the input time of the start signal is measured by the timer means, and the measurement time is When the preset time is reached, a start signal is input to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting the latch signal to the random value storage means due to the influence of noise or the like.

  In the configuration according to claim 11, since the timer means is set as a predetermined time that is shorter than the execution time of a predetermined number of timer interrupt processes by the timer interrupt process executing means, the display result determining means Can prevent the random value read from the random value storage means from being the same as the previously read random value.

In the configuration according to claim 12 , when the random number value stored in the random value storage means is updated, the random number value is prevented from being read from the random value storage means by the display result determining means, The random number value can be updated reliably and stably.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The gaming machine in the present embodiment is a gaming machine that performs a special game using a display device composed of, for example, a 7-segment or dot matrix LED (light emitting diode), and a card reader (CR: Card) that lends a ball using a prepaid card. Reader) type pachinko machines, etc. may be used.

  FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails. Above the center position of the game area, a special symbol display 4 is provided for variably displaying special symbols as identification information that can be identified. Below the special symbol display 4 is provided an image display device 5 that can perform variable display of decorative symbols different from the special symbols, image display that is a predetermined effect display, and the like. Below the image display device 5, an ordinary variable winning ball device (start winning port) 6 is arranged. Below the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus 7 and an ordinary symbol display 40 are provided.

  The special symbol display 4 is composed of, for example, 7-segment or dot matrix LEDs. The special symbol display 4 displays, for example, “0” to “9” in a special game as a variable display game performed based on the fact that the start condition is established by winning a game ball in the normal variable winning ball device 6. The special symbol which consists of the number etc. which show and functions as several types of identification information which can identify each is variably displayed. In the special symbol game performed by the special symbol display device 4, after the special symbol variation display is started, when the predetermined time has elapsed, the fixed symbol that is the special symbol variation display result is stopped and displayed (derived display).

  The image display device 5 is composed of, for example, an LCD or the like, and may be any device that performs screen display by a dot matrix method using a large number of pixels (pixels). On the display screen of the image display device 5, for example, a variable display unit serving as a display area divided into three variably displays a plurality of types of decorative symbols that can each be identified. As a specific example, variable display portions “left”, “middle”, and “right” are arranged on the image display device 5, and decorative symbols are variably displayed on the variable display portions. When the special symbol display on the special symbol display 4 is started, the variable display of the “left”, “middle”, and “right” on the image display device 5 starts the variable display of the decorative symbols. After that, when the fixed symbol is stopped and displayed as a special symbol variation display result on the special symbol display 4, the variable display portions “left”, “middle”, and “right” in the image display device 5 are fixed. By stopping and displaying the decorative pattern that becomes the symbol, a combination of decorative symbols that is a variable display result is derived and displayed.

  For example, in each of the “left”, “middle”, and “right” variable display portions, nine types of symbols “1” to “9” are displayed as decorative symbols in a variable manner. In the “left”, “middle”, and “right” variable display sections, when the decorative symbol variation display is started, the display is switched or scrolled from the smallest number shown in the symbol to the larger one. If the decorative symbol “9” is displayed, then the decorative symbol “1” is displayed. As a display result in the variable display of the decorative pattern by the image display device 5, for example, when the same decorative pattern is stopped and displayed in the “left”, “middle”, and “right” variable display units, a specific result is displayed. When the display result is derived and displayed, the pachinko gaming machine 1 is in the big hit gaming state. In each of the “left”, “middle”, and “right” variable display portions, a plurality of types of symbols representing alphabets may be displayed as decorative designs, and a plurality of types of character designs related to a predetermined motif may be displayed. May be variably displayed as a decorative pattern.

  In addition, the image display device 5 may be provided with a special symbol start memory display area for displaying the number of effective winning balls entered into the normal variable winning ball device 6, that is, the starting winning memory number (holding memory number). In the special symbol start memory display area, a winning display is performed corresponding to the effective start winning when the start winning memory number is less than a predetermined upper limit value (for example, “4”). As a specific example, the display that is normally blue is changed to a red display. In this case, by providing the decorative symbol display area (variable display portion) and the special symbol start memory display area separately, the number of starting winning balls can be displayed even during variable display of the decorative symbol. . The special symbol start memory display area may be provided in a part of the decorative symbol display area. In this case, the display of the start winning memory number may be interrupted during the variable display of the decorative symbols. Further, a display (special symbol start storage display) for displaying the start winning memory number may be provided separately from the image display device 5.

  In this embodiment, an ornamental symbol with an even symbol number is a normal jackpot symbol, and an ornamental symbol with an odd symbol number is an odd jackpot symbol. That is, after starting the variable display of the decorative pattern on the image display device 5, when the same decorative pattern is derived and displayed as a display result on the “left”, “middle”, and “right” variable display sections, The pachinko gaming machine 1 is in a big hit gaming state. Further, after the variable display of the decorative symbols on the image display device 5 is started, when the same probability variation big winning symbol is derived and displayed as a display result on the “left”, “middle”, and “right” variable display portions and confirmed. The pachinko gaming machine 1 is in a special gaming state (probability increasing state) following the end of the jackpot gaming state, and thereafter, there is a probability that the display result in the special display game or variable display of decorative symbols will be a big hit until the predetermined condition is satisfied. improves. Further, in the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 includes a light emitting diode (LED) or the like, and lights up, flashes, colors, etc. in a normal diagram game where a game ball passes through a pass gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 2). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding storage unit 121 (FIG. 6) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 2). The opening / closing plate is in a closed state at a normal time, for example, before the big hit gaming state is generated after the pachinko gaming machine 1 is turned on. On the other hand, when the game state is a big hit based on the variation display result in the special symbol game by the special symbol display 4 or the variable display result of the decoration symbol in the image display device 5, the solenoid 22 sets the winning area for a predetermined period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated, and then closed. When a game ball is won in the winning area when the opening / closing plate is opened by the special variable winning ball device 7, the predetermined ball game is detected based on the fact that the game ball is detected by a large winning port switch (not shown). A number of prize balls will be paid out.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  In addition to the main board 11 and the effect control board 12, main boards such as a power supply board, a payout control board, and an information terminal board are arranged at appropriate positions on the back surface of the pachinko gaming machine 1, respectively.

  FIG. 2 is a block diagram showing a system configuration example centering on the main board 11 and the effect control board 12. Note that FIG. 2 also shows a random number generation circuit 17, a start winning a prize opening switch 70, and the like.

  The start winning opening switch 70 generates a start winning signal (high level signal) SS with the main board 11 and a random number based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. Output to the circuit 17.

  The main board 11 includes a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The main board 11 is also connected with wiring to the effect control board 12 and wiring from the start winning port switch 70. Further, on the main board 11, wiring to the solenoids 21 and 22 for performing the movable control of the movable blade piece in the normal variable winning ball apparatus 6 and the opening and closing control in the special variable winning ball apparatus 7 and a special symbol display are provided. Wiring to the device 4 and the normal symbol display 40 is also connected.

  The game control microcomputer 100 is, for example, a one-chip microcomputer, and is controlled according to a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a program. A CPU (Central Processing Unit) 103 and an I / O (Input / Output) port 104 are included. This game control microcomputer 100 has a function of generating random numbers used in a special game, a function of outputting and transmitting a control command as an example of command information for the effect control board 12, and a display control of the special symbol display 4. A function to perform, a function to perform the on / off control of the normal symbol display 40, and the like.

  The control command transmitted from the main board 11 to the effect control board 12 is an effect control command transmitted as an electrical signal using, for example, signal lines of the effect control signals CD0 to CD7. FIG. 3 is an explanatory diagram showing an example of the contents of the effect control command used in this embodiment. The effect control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit (bit 7) of the MODE data is always “1”, and the first bit of the EXT data is “0”. The command form shown in FIG. 3 is an example, and other command forms may be used. In this example, the control command is composed of two control signals. However, the number of control signals constituting the control command may be one or a plurality of three or more.

  In the example shown in FIG. 3, the command 80XX (h) is a variable display start command transmitted when the special symbol display by the special symbol display 4 is started in the special symbol game. XX (h) indicates an unspecified hexadecimal number and may be a value arbitrarily set according to the instruction content by the effect control command. The variable display start command is a special symbol variable display time that is the time from when the special symbol variable display is started until the fixed symbol is stopped and displayed, or whether the variable display result in the special symbol game is a big hit EXT data indicating whether or not the decorative symbol being variably displayed is to be reached is included.

  Here, “reach” is a variable display for symbols that have not yet been derived and displayed (referred to as reach variation symbols) when the symbols that have been derived and displayed (reach symbols) constitute a part of the jackpot combination. It is a display mode or a display mode in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, on the combination effective line that has not been stopped yet when the symbols constituting the predetermined jackpot combination are stopped and displayed on some of the variable display portions on the predetermined combination effective line. Display mode in which variable display is performed in the variable display section (for example, “left”, “right” variable display sections among the “left”, “middle”, “right” variable display sections provided in the display area Is a display mode in which part of the big hit symbol (for example, “7”) is stopped and displayed, and the “medium” variable display section is still displaying variable display), or variable on the effective line A display mode in which all or some of the symbols on the display unit are variably displayed synchronously while constituting all or part of the jackpot symbol (for example, “left”, “middle”, “right” provided in the display area) ”Variable display is performed on all of the variable display sections, which state is Be shown the same display mode variable display is being performed in a manner special symbol are aligned). On the side of the effect control board 12, for example, in response to receiving a variable display start command, variable display of decorative symbols in the image display device 5 is started.

  The command 9000 (h) is a variable display end command transmitted when the special symbol display on the special symbol game by the special symbol display 4 is ended. The command A000 (h) is transmitted when the big hit gaming state is started because the display result is a big hit in the special symbol game by the special symbol display 4 and the variable display of the decorative symbol in the image display device 5. A jackpot start command. The command A001 (h) is a jackpot end command transmitted when the jackpot gaming state ends. The command B000 (h) is generated when the decision to reach the variable display mode of the decorative design in the image display device 5 is made continuously over a predetermined number of times (for example, 10 times) of variable display. This is a failure detection command that is transmitted as a failure is detected. The command B001 (h) continuously determines over the variable display for a predetermined number of times (for example, 50 times) that the variable display result of the decorative pattern on the image display device 5 is a normal loss that is lost without reaching, for example. This is a failure detection command that is transmitted when a failure is detected in the random number generation circuit 17 when it is performed.

  In addition to the game control program, the ROM 101 of the game control microcomputer 100 mounted on the main board 11 stores various data tables used for controlling the progress of the game. For example, the ROM 101 stores a plurality of determination tables and determination tables prepared for the CPU 103 to perform various determinations and determinations. This determination table includes a jackpot determination table that is referred to in order to determine whether or not the confirmed symbol is a jackpot symbol in the special symbol game by the special symbol display 4. As an example of such a big hit determination table, in this embodiment, a normal big hit determination table 111 shown in FIG. 4 (A) and a probable change big hit determination table 112 shown in FIG. 4 (B) are stored in the ROM 101. Yes.

  Each of the normal big hit determination table 111 and the probability change big hit determination table 112 is based on setting data that associates a determination result indicating whether the display result of the special game is a big hit or a loss with a random number R1 for the big hit determination. It is configured. In the probability change big hit determination table 112, more random numbers R1 than the normal big hit determination table 111 are allocated to the determination result of “big hit”. That is, in the normal game state in which the display result of the special figure game is determined using the normal big hit determination table 111 by determining the display result of the special figure game using the probability big hit determination table 112 in the probability improvement state. The probability of becoming a big hit gaming state is increased.

  In this embodiment, in the normal jackpot determination table 111 shown in FIG. 4A, the random number generation circuit 17 generates “2001” among the numerical data “0” to “65335” generated as the random number R1 for jackpot determination. ”To“ 2184 ”are associated with determination results indicating“ big hit ”. On the other hand, in the probability variation big hit determination table 112 shown in FIG. 4B, among the numerical data “0” to “65335” generated as the random value R1 for big hit determination by the random number generation circuit 17, “2001” to “3104”. ”Is associated with a determination result indicating“ big hit ”.

  As other determination tables, there is a reach determination table that is referred to for determining whether or not the decorative display variable display mode in the image display device 5 is set as reach. FIG. 5 shows a configuration example of the reach determination table 113 used in this embodiment. The reach determination table 113 is configured by setting data for associating a determination result indicating whether or not the variable display mode of the decorative symbols is reach with a random value R2 for reach determination. In the reach determination table 113 shown in FIG. 5, among the numerical data “0” to “9” stored in the reach determination random counter 122 (FIG. 6) as the reach determination random value R2, “8” is “reach”. Is associated with the determination result.

  Further, the determination table stored in the ROM 101 includes a variable display pattern determination table for determining a variable display pattern used in the special display game by the special symbol display 4 and the variable display of the decorative symbol by the image display device 5. Etc. are included. As the variable display pattern determination table, a big hit variable display pattern determination table, a reach variable display pattern determination table, a normal loss variable display pattern determination table, and the like may be prepared in advance. Each variable display pattern determination table is started in a special figure game started in the special symbol display 4 or the image display device 5 based on the value of the random number for variable display pattern determination for determining the variable display pattern. What is necessary is just to be comprised from the data for a determination for determining the variable display pattern used by the variable display of a decoration symbol.

  In the RAM 102 of the game control microcomputer 100 mounted on the main board 11, various data used for controlling the execution of the special symbol game by the special symbol display 4 and the variable display of the decorative symbol on the image display device 5. For this purpose, a variable display data holding area 120 as shown in FIG. 6 is provided. The variable display data holding area 120 is provided with a special figure storage unit 121, a reach determination random counter 122, a start winning port switch timer 123, a reach number counter 124, and a normal lose number counter 125.

  The special figure holding storage unit 121 is a condition (execution condition) for the game ball to win the normal variable winning ball apparatus 6 and to execute the variable display of the decorative graphic in the special graphic game or the image display apparatus 5 by the special symbol display 4. ) Is established, but a pending state in which a condition (start condition) for actually starting variable display is not established due to reasons such as executing the previous variable display is stored. The special figure holding storage unit 121 uses the random variable R1 for jackpot determination acquired by the CPU 103 from the random number generation circuit 17 based on the establishment of the start condition by winning the game ball to the normal variable winning ball device 6 as the normal variable winning ball. In accordance with the winning order to the device 6, the number of starting winning prizes is stored in association with the hold number until a predetermined upper limit value (for example, “4”) is reached.

  The reach determination random counter 122 stores a reach determination random value R2 that is updated in synchronization with the jackpot determination random value R1 acquired by the CPU 103 from the random number generation circuit 17. The start winning port switch timer 123 stores a switch timer value to be added or cleared depending on whether the start winning signal SS input from the start winning port switch 70 is in an on state or an off state.

  The reach number counter 124 counts the number of times that the determination that the decorative display variable display mode in the image display device 5 is to be reached is made continuously. The normal loss count counter 125 counts the number of times that the determination that the variable display result of the loss is derived and displayed without reaching the variable display mode of the decorative pattern in the image display device 5 is made.

  Further, in the RAM 102, a game for setting a plurality of types of flags to be set or cleared in accordance with the gaming state in the pachinko gaming machine 1, signals transmitted from various switches other than the start winning port switch 70, and the like. A control flag setting area, a game control counter / timer setting area for storing data indicating a plurality of types of count values and timer values used for game control in the pachinko gaming machine 1 may be provided. The circuit used for flag setting and counter / timer may be constituted by a register circuit provided separately from the RAM 102.

  In the game control flag setting area, for example, a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a failure detection flag, a failure notification flag, and the like are provided.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (FIG. 20) described later. The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order.

  The big hit state flag is set to an on state when the display result of the special symbol display by the special symbol display device 4 and the variable display of the decorative symbols on the image display device 5 is a big hit, and is cleared when the big hit game state is ended. Is turned off. The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The failure detection flag is a flag that indicates whether a failure in the random number generation circuit 17 has been detected. For example, when no failure is detected in the random number generation circuit 17, the value of the failure detection flag is set to “0”. On the other hand, when the count value in the reach number counter 124 exceeds a predetermined reach continuous upper limit value (for example, “10”), the value of the failure detection flag is set to “1”. Further, when the count value in the normal loss frequency counter 125 exceeds a predetermined normal loss continuous upper limit value (for example, “50”), the value of the failure detection flag is set to “2”. The failure notification flag is set to an on state when a notification that a failure has been detected in the random number generation circuit 17 is given by, for example, an image displayed on the image display device 5.

  The switch circuit 107 shown in FIG. 2 takes in the start winning signal SS from the start winning port switch 70 and the detection signals from other winning port switches and transmits them to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The effect control board 12 controls the display operation in the image display device 5, the sound output operation from the speakers 8L and 8R, the lighting operation and the extinguishing operation of the game effect lamp 9. For example, the effect control board 12 performs control to execute various effect displays by causing the image display device 5 to execute an image switching display based on an effect control command transmitted from the main board 11. The effect control board 12 is connected to wiring for transmitting control signals to the audio output circuit 13 and the lamp driver circuit 14.

  An effect control CPU 105 is mounted on the effect control board 12. When receiving the effect control command from the main board 11, the effect control CPU 105 performs display control of the image display device 5, performs sound output control by outputting sound data to the sound output circuit 13, and the like. Lamp lighting control is performed by causing the driver circuit 14 to output lamp data.

  The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state. FIG. 7 is a block diagram showing a configuration example of the random number generation circuit 17. In the configuration example shown in FIG. 7, the random number generation circuit 17 includes a reference clock signal output circuit 171, a timer circuit 172, a latch signal output circuit 173, a counter 174, a clock signal generation circuit 175, and a random value storage circuit 179. It consists of and.

  The reference clock signal output circuit 171 generates a reference clock signal S1 having a predetermined frequency (for example, 20 MHz). The reference clock signal output circuit 171 outputs the generated reference clock signal S1 to the timer circuit 172 and the clock signal generation circuit 175.

  The timer circuit 172 measures the time during which the start winning signal SS is input from the start winning port switch 70, and when the measured time reaches a predetermined time (for example, 3 ms), the timer winning signal SS is a latch signal output circuit. To 173. In this embodiment, the timer circuit 172 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. While the input is at a high level, the timer circuit 172 counts up or down a predetermined timer value every time the reference clock signal S1 is input from the reference clock signal output circuit 171. When the timer value counted up or down reaches a value corresponding to 3 ms, the timer circuit 172 determines that the input signal is the start winning signal SS, and the start winning signal SS is latched. Output to the output circuit 173.

  The latch signal output circuit 173 is configured by a D-type flip-flop circuit or the like. The input terminal D of the latch signal output circuit 173 is connected to the output terminal of the timer circuit 172, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 175. The output terminal Q of the latch signal output circuit 173 is connected to the random value storage circuit 179. The latch signal output circuit 173 generates the latch signal SL by synchronizing the start winning signal SS input from the input terminal D with the rising edge of the latch clock signal S3 input from the clock terminal CK, and generates the output terminal Q. Output from.

  The counter 174 circulates the count value C to be output from a predetermined initial value to a predetermined final value in response to the rising edge of the count clock signal S2 input from the positive phase output terminal Q of the clock signal generation circuit 175. Update to In this embodiment, the counter 174 is a 16-bit binary counter, and counts up the count value C by 1 from “0” to “65535” each time the rising edge of the count clock signal S2 is input. Go. When the count value C is counted up to “65535”, the count value C is returned to “0” and counted up to “65535” again. That is, the count value C is cyclically updated as “0” → “1” →... → “65535” → “0” →... Each time the rising edge of the count clock signal S2 is input to the counter 174. The

  The clock signal generation circuit 175 is configured by a D-type flip-flop circuit or the like. The clock terminal CK of the clock signal generation circuit 175 is connected to the output terminal of the reference clock signal output circuit 171, and the positive phase output terminal Q is connected to the counter 174. Further, the anti-phase output terminal (inverted output terminal) Q (bar) of the clock signal generation circuit 175 is connected to the input terminal D and the clock terminal CK of the latch signal output circuit 173.

  The clock signal generation circuit 175 outputs a signal fed back from the reverse phase output terminal Q (bar) to the input terminal D at a timing when the reference clock signal S1 input from the reference clock signal output circuit 171 to the clock terminal CK rises. In synchronization, the signal is output from the positive phase output terminal Q, and the negative phase signal (inverted signal) of the signal output from the positive phase output terminal Q is output from the negative phase output terminal Q (bar). In this way, the clock signal generation circuit 175 generates two clock signals (counting clock signal S2 and latching clock signal S3) having the same period and different phases, and outputs the counting clock signal S2 in the normal phase. From the terminal Q, the latch clock signal S3 can be output from the negative phase output terminal Q (bar).

  Specifically, a count clock signal S2 having a frequency of 10 MHz is output from the positive phase output terminal Q, and a negative phase signal of the count clock signal S2, that is, a count is output from the negative phase output terminal Q (bar). Similarly to the clock signal S2, a latch clock signal S3 having a frequency of 10 MHz and having a phase different from the counting clock signal S2 by π (= 180 °) is output.

  The random value storage circuit 179 is a 16-bit register, and stores the random value R1 read in the start winning process in step S25 described later. In response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 173, the random value storage circuit 179 latches and stores the count value C input from the counter 174 as the random value R1. Thus, every time the start winning signal SS is input to the random number generation circuit 17, the stored random number value R1 is sequentially updated.

  FIG. 8 is a circuit diagram showing a configuration example of the random value storage circuit 179. The random value storage circuit 179 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 flip-flop circuits 210 to 225, and 16 OR circuits 230 to 245. Has been.

  The input terminal of the AND circuit 201 is connected to the output terminal Q of the latch signal output circuit 173 and the output terminal of the NOT circuit 204, and the output terminals are the input terminal of the NOT circuit 202 and the clock terminal CK0 of the flip-flop circuits 210 to 225. To CK15. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the I / O port 104 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 230 to 245.

  The input terminals D0 to D15 of the flip-flop circuits 210 to 225 are connected to the output terminal of the counter 174. The clock terminals CK0 to CK15 of the flip-flop circuits 210 to 225 are connected to the output terminal of the AND circuit 201, and the output terminals Q0 to Q15 are connected to the other input terminal of each of the OR circuits 230 to 245.

  The input terminals of the OR circuits 230 to 245 are connected to the output terminal of the NOT circuit 204 and each of the output terminals of the flip-flop circuits 210 to 225, and the output terminals are connected to the I / O port 104 of the game control microcomputer 100. It is connected. FIG. 9 is a diagram for explaining the details of the connection between the output terminals of the OR circuits 230 to 245 and the I / O port 104 of the game control microcomputer 100. In this embodiment, the output terminals of the OR circuits 230 to 245 and the bits of the input port of the jackpot determination random number included in the I / O port 104 are switched and connected as shown in FIG. Thereby, the randomness of the random number input to the game control microcomputer 100 can be enhanced.

  The operation of the random value storage circuit 179 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the gaming control microcomputer 100 (when one input of the AND circuit 203 is low level), the output terminal Q of the latch signal output circuit 173 At the timing when the input latch signal SL rises from low level to high level (in the example shown in FIG. 10, timings T1, T2, and T7), the inputs of the AND circuit 201 both become high level and are output from the output terminals. The signal SR becomes high level. The signal SR output from the AND circuit 201 is input to the clock terminals CK0 to CK15 of the flip-flop circuits 210 to 225.

  The flip-flop circuits 210 to 225 respond to the rising edge of the signal SR input from the clock terminals CK0 to CK15 and receive bit data C0 to C15 of the count value C input from the counter 174 via the input terminals D0 to D15. Are latched and stored as bit data R0 to R15 of the random number value, and the bit data RA0 to RA15 of the stored random number value R1 are output from the output terminals Q0 to Q15.

  When the output control signal SC is not input (in the example shown in FIG. 10, the period up to the timing T3 and the period after the timing T6), one of the inputs of the AND circuit 203 is at the low level, so that the output is output from the output terminal. The signal SG to be output becomes a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Thus, since one input of the OR circuits 230 to 245 is at the high level, regardless of whether the signal input to the other input terminal is at the high level or the low level, that is, the input random number value. Regardless of whether the value of the bit data RA0 to RA15 of R1 is “0” or “1”, the signals SO0 to SO15 output from the OR circuits 230 to 245 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 179 is always “635535 (= 1111h)”, and the random value R1 cannot be read from the random value storage circuit 179. That is, when the output control signal SC is not input, the random value storage circuit 179 is in a non-readable (disabled) state.

  When the output control signal SC is input from the gaming control microcomputer 100 when the latch signal SL input from the latch signal output circuit 173 is at a low level (in the example shown in FIG. 10, from the timing T4 to the timing T6). Since the inputs of the AND circuit 203 are both at a high level, the signal SG output from the output terminal is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminal of each of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the value of the bit data RA0 to RA15 of the random number value R1 input to the other input terminals of the OR circuits 230 to 245 is directly from the output terminal of the OR circuits 230 to 245 (the value of the bit data RA0 to RA15 is “1”). "1" is output when it is "," and "0" is output when it is "0." As a result, the random value R1 can be read from the random value storage circuit 179. That is, when the output control signal SC is input, the random value storage circuit 179 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 173 before the output control signal SC is input from the game control microcomputer 100, one input of the AND circuit 203 becomes low level. After that, even when the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 10, it is output from the output terminal). The signal SG remains at a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 becomes high level in this way, the output from the OR circuits 230 to 245 is performed regardless of whether the signal input to the other input terminal is high level or low level. The signals SO0 to SO15 all become high level, and the random number value R1 cannot be read from the random value storage circuit 179 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 179 becomes incapable of receiving the output control signal SC.

  Further, when the output control signal SC is input from the game control microcomputer 100 before the latch signal SL input from the latch signal output circuit 173 becomes high level, one input of the AND circuit 201 is low level. Therefore, after that, even if the input latch signal SL becomes high level (in the example shown in FIG. 10, at timing T5) while the output control signal SC is being input, the output is output from the output terminal. The signal SR to be kept remains at a low level. For this reason, the signal SR input to the clock terminals CK0 to CK15 of the flip-flop circuits 210 to 225 does not rise from the low level to the high level, and the bit data RA0 of the random number value R1 stored in the flip-flop circuits 210 to 225. ˜RA15 are not updated even when the latch signal SL input from the latch signal output circuit 173 rises. That is, when the output control signal SC is input, the random value storage circuit 179 becomes incapable of receiving the latch signal SL.

  FIG. 11 is a timing chart for explaining the operation in the configuration example of the random number generation circuit 17 shown in FIG.

  As shown in FIG. 11A, the reference clock signal output circuit 171 generates a reference clock signal S1 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. And to the clock terminal CK of the clock signal generation circuit 175.

  The clock signal generation circuit 175 responds to the rising edge of the reference clock signal S1 input from the clock terminal CK with the latch clock signal S3 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 11B, the positive phase output terminal Q outputs a counting clock signal S2 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12,.

  The clock signal generation circuit 175 inverts the count clock signal S2 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, a latch clock signal S3 having a frequency of 10 MHz rising from the low level to the high level is output from the reverse phase output terminal Q (bar) at the timings T11, T13,... As shown in FIG. Is done.

  Then, the counter 174 updates the count value C in response to the rising edge of the count clock signal S2 input from the positive phase output terminal Q of the clock signal generation circuit 175, as shown in FIG. Output. On the other hand, the latch signal output circuit 173 inputs the start winning signal SS shown in FIG. 11E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 175 to the clock terminal CK. In synchronization with the rising edge of the latching clock signal S3, the latch signal SL shown in FIG.

  The random value storage circuit 179 responds the count value C input from the counter 174 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 173 to the clock terminal CK. Then, by latching and storing as the random value R1, the stored random value R1 is updated as shown in FIG. In this way, the random number generation circuit 17 having the configuration shown in FIG. 7 can reliably change the update timing of the count value C and the latch timing of the count value C.

  FIG. 12 is a block diagram showing another configuration example of the random number generation circuit 17. In the random number generation circuit 17 shown in FIG. 12, the same components as those shown in FIG. In the configuration example shown in FIG. 12, the random number generation circuit 17 includes a reference clock signal output circuit 171, a timer circuit 172, a latch signal output circuit 173, a counter 174, a frequency divider circuit 176, a selector 177, and a random value. And a memory circuit 179.

  In the configuration example shown in FIG. 12, the reference clock signal S1 generated by the reference clock signal output circuit 171 is output to the timer circuit 172, the frequency divider circuit 176, and the selector 177. The frequency dividing circuit 176 divides the reference clock signal S1 input from the reference clock signal output circuit 171 by 2, and generates a divided clock signal S4. The frequency dividing circuit 176 outputs the generated divided clock signal S4 to the selector 177.

  The selector 177 includes, for example, two CMOS (Complementary Metal Oxide Semiconductor) transistors that form a differential pair. The selector 177 converts the reference clock signal S1 input from the reference clock signal output circuit 171 into the first and second output terminals O1 and O2 according to the level of the divided clock signal S4 input from the frequency dividing circuit 176. Output from either one of these. In this embodiment, when the frequency-divided clock signal S4 input from the frequency dividing circuit 176 is at a high level, the selector 177 turns on the first output terminal O1 and turns off the second output terminal O2, and the reference The reference clock signal S1 input from the clock signal output circuit 171 is output from the first output terminal O1. On the other hand, when the frequency-divided clock signal S4 input from the frequency divider circuit 176 is at a low level, the selector 177 turns off the first output terminal O1 and turns on the second output terminal O2, and the reference clock signal output circuit The reference clock signal S1 input from 171 is output from the second output terminal O2.

  In the configuration example shown in FIG. 12, the input terminal D of the latch signal output circuit 173 is connected to the output terminal of the timer circuit 172, and the clock terminal Clk is connected to the second output terminal O2 of the selector 177. The latch signal output circuit 173 synchronizes the start winning signal SS input from the input terminal D with the rising edge of the second output clock signal S6 input from the clock terminal Clk, and latch signal (high level signal) SL. As output from the output terminal Q.

  In the configuration example shown in FIG. 12, the counter 174 sets the count value C to a predetermined initial value in response to the rising edge of the first output clock signal S5 output from the first output terminal O1 of the selector 177. Is updated cyclically to a predetermined final value.

  FIG. 13 is a timing chart for explaining the operation in the configuration example of the random number generation circuit 17 shown in FIG.

  As shown in FIG. 13A, the reference clock signal output circuit 171 generates a reference clock signal S1 that rises from a low level to a high level at timings T20, T30,..., A timer circuit 172, and a frequency dividing circuit 176. And output to the selector 177.

  The frequency dividing circuit 176 divides the reference clock signal S1 input from the reference clock signal output circuit 171 by 2, and becomes a high level during a period from T20 to T30, a period from T21 to T31, and so on. The frequency-divided clock signal S4 shown in FIG. 13B, which is at the low level during the period from T31 to T22, is generated and output to the selector 177.

  The selector 177 receives an input from the reference clock signal output circuit 171 when the frequency-divided clock signal S4 input from the frequency-dividing circuit 176 is at a high level, that is, a period from T20 to T30, a period from T21 to T31,. The reference clock signal S1 is output from the first output terminal O1. As a result, the first output terminal O1 of the selector 177 outputs the first output clock signal S5 shown in FIG. 13C, which rises from the low level to the high level at the timing T20, T21,. The first output clock signal S5 is supplied to the counter 174. Then, as shown in FIG. 13D, the counter 174 updates the count value C every time the rising edge of the first output clock signal S5 supplied from the selector 177 is input, and the random value storage circuit. To 179.

  On the other hand, the selector 177 receives the reference clock signal output circuit 171 when the frequency-divided clock signal S4 input from the frequency divider circuit 176 is at a low level, that is, during the period from T30 to T21, from T31 to T22,. The reference clock signal S1 input from is output from the second output terminal O2. Accordingly, the second output terminal O2 of the selector 177 outputs the second output clock signal S6 shown in FIG. 13E, which rises from the low level to the high level at the timings T30, T31,. The second output clock signal S6 is supplied to the latch signal output circuit 173. The latch signal output circuit 173 synchronizes the start winning signal SS shown in FIG. 13 (F) input from the input terminal D with the rising edge of the second output clock signal S6 supplied from the selector 177. The latch signal SL shown in G) is output.

  The random value storage circuit 179 responds the count value C input from the counter 174 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 173 to the clock terminal CK. Then, by latching and storing as the random value R1, the stored random value R1 is updated as shown in FIG. In this manner, the random number generation circuit 17 having the configuration shown in FIG. 12 can reliably change the update timing of the count value C and the latch timing of the count value C.

  FIG. 14 is a block diagram showing still another configuration example of the random number generation circuit 17. In the random number generation circuit 17 shown in FIG. 14, the same components as those shown in FIGS. 7 and 12 are denoted by the same reference numerals. In the configuration example shown in FIG. 14, the random number generation circuit 17 includes a reference clock signal output circuit 171, a timer circuit 172, a latch signal output circuit 173, a counter 174, a delay circuit 178, and a random value storage circuit 179. It is configured.

  In the configuration example shown in FIG. 14, the reference clock signal S1 generated by the reference clock signal output circuit 171 is output to the timer circuit 172, the counter 174, and the delay circuit 178. The delay circuit 178 delays the reference clock signal S1 input from the reference clock signal output circuit 171 by a period that is different from a period that is an integral multiple of the period of the reference clock signal S1, thereby generating a delayed clock signal S7. The delay circuit 178 outputs the generated delayed clock signal S7 to the latch signal output circuit 173.

  In the configuration example shown in FIG. 14, the input terminal D of the latch signal output circuit 173 is connected to the output terminal of the timer circuit 172, and the clock terminal Clk is connected to the output terminal of the delay circuit 178. The latch signal output circuit 173 synchronizes the start winning signal SS input from the input terminal D with the rising edge of the delayed clock signal S7 input from the clock terminal Clk, and outputs it as a latch signal (high level signal) SL. Output from Q.

  In the configuration example shown in FIG. 14, the counter 174 circulates the count value C from a predetermined initial value to a predetermined final value in response to the rising edge of the reference clock signal S1 input from the reference clock signal output circuit 171. Update automatically.

  FIG. 15 is a timing chart for explaining the operation in the configuration example of the random number generation circuit 17 shown in FIG.

  As shown in FIG. 15A, the reference clock signal output circuit 171 generates a reference clock signal S1 that rises from a low level to a high level at timings T40, T41,..., A timer circuit 172, a counter 174, and a delay. Output to circuit 178.

  As shown in FIG. 15C, the counter 174 updates the count value C every time the rising edge of the reference clock signal S1 supplied from the reference clock signal output circuit 171 is input, and the random value storage circuit 179. Output to. On the other hand, the delay circuit 178 delays the inputted reference clock signal S1 by ΔT (≠ nT: n is an integer), and shows a period T rising from the low level to the high level at timings T50, T51,. A delayed clock signal S7 shown in FIG. 5B is generated and output to the clock terminal Clk of the latch signal output circuit 173.

  Then, the latch signal output circuit 173 synchronizes the start winning signal SS shown in FIG. 15D input from the input terminal D with the rising edge of the delayed clock signal S7 input from the clock terminal Clk. The latch signal SL shown in E) is output.

  The random value storage circuit 179 responds the count value C input from the counter 174 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 173 to the clock terminal CK. Then, by latching and storing as the random value R1, the stored random value R1 is updated as shown in FIG. In this way, the random number generation circuit 17 having the configuration shown in FIG. 14 can reliably change the update timing of the count value C and the latch timing of the count value C.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 16 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S12) after setting the interrupt prohibition (step S11). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, after interrupting is permitted (step S13), a loop process is started.

  When the CPU 103 executing the game control main process shown in FIG. 16 receives the interrupt request signal from the CTC and accepts the interrupt request, the CPU 103 executes the game control interrupt process shown in the flowchart of FIG.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined switch process (step S21). In the switch processing, it is determined whether or not various detection signals such as a start winning signal SS input from the start winning port switch 70 via the switch circuit 107 are in an on state. When the start winning signal SS is ON, the timer value in the start winning port switch timer 123 is incremented by “1”. On the other hand, when the start winning signal SS is in the OFF state, the timer value in the start winning port switch timer 123 is cleared.

  Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary according to the diagnosis result (step S22). Thereafter, a determination random number update process for updating a predetermined determination random number (step S23), and a display random number update process for updating a predetermined display random number excluding the reach determination random number (random number R2) (step S24). And are executed sequentially.

  Next, the CPU 103 executes a start winning process (step S25). In the start winning process, when the winning of the game ball to the normal variable winning ball apparatus 6 is detected, the numerical data indicating the random number value R1 serving as the jackpot determination random number is obtained from the random number generation circuit 17 and stored in the special figure holding memory. The process etc. which are memorize | stored in the part 121 are performed. Thereafter, the CPU 103 executes special symbol process processing (step S26). In the special symbol process process, in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state, the corresponding process is selected and executed according to the special symbol process flag provided in the game control flag setting area. Following the special symbol process, the CPU 103 executes a normal symbol process (step S27). In the normal symbol process, in order to control the normal symbol display 40 in a predetermined order, the corresponding process is selected and executed according to the normal symbol process flag provided in the game control flag setting area.

  Further, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the effect control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S28). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in the predetermined command transmission table, and so on, for the sub-side control board such as the effect control board 12, etc. A control signal for controlling the progress of the game is transmitted. The effect control command sent from the main board 11 by this command control processing is received by the effect control CPU 105 of the effect control board 12, and display control of the image display device 5 is performed according to the display control command.

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S29). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to a predetermined information terminal board.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movable blade piece in the normal variable winning ball device 6 and open / close the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S30). Thereafter, by executing predetermined prize ball processing, the number of prize balls can be set based on the start winning signal SS input from the start winning opening switch 70, and a payout control command can be output to the payout control board. (Step S31).

  FIG. 18 is a flowchart illustrating an example of a process executed in step S25 illustrated in FIG. 17 as the start winning process. In this start winning process, the CPU 103 first determines whether or not the game ball has won the normal variable winning ball apparatus 6 by checking the timer value in the start winning port switch timer 123 (step S201). In step S201, the CPU 103 loads the timer value in the start winning a prize opening switch timer 123, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). As a result, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is performed a predetermined number of times (for example, twice) (for example, 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is less than the switch-on determination value “2”, the start winning process is finished as it is. On the other hand, when the timer value is the switch-on determination value “2” or more, the game ball is won. (Step S201; Yes), the timer value in the start winning a prize opening switch timer 123 is cleared (Step S202). At this time, it is determined whether or not the number of starting winning prizes stored in the special figure storage unit 121 has reached a predetermined upper limit (eg, “4”) (step S203). Here, when the random number value R1 is stored in the special figure reservation storage unit 121 in association with the maximum value of the reservation number, it is determined that the start winning storage number has reached the upper limit value.

  When the start winning memorized number has reached the upper limit (step S203; Yes), the start winning process is terminated as it is, with the start detection by the current winning being invalidated. On the other hand, when the start winning memorized number is less than the upper limit value (step S203; No), the random number value memory circuit 179 can be read by sending the output control signal SC to the random number value memory circuit 179 provided in the random number generator circuit 17 ( (Enable) state (step S204).

  Subsequently, the CPU 103 reads out and acquires the random value R1 from the random value storage circuit 179 (step S205), and stores the acquired random value R1 in, for example, a predetermined buffer area provided in the RAM 102 (step S206). ), The transmission of the output control signal SC to the random value storage circuit 179 is stopped, and the random value storage circuit 179 is controlled to be unreadable (disabled) (step S207). Then, the CPU 103 adds “1” to the starting prize storage number (step S208), and sets and stores the random number value R1 stored in the predetermined buffer area at the head of the empty entry in the special figure storage unit 121 (step S208). S209).

  After executing the processing of step S209, the reach determination random counter value corresponding to the random value R1 acquired in step S205 is set as the random value R2 in the reach determination random counter 122 (step S210). For example, as shown in FIG. 19, the CPU 103 sets the reach determination random value R2 to any one of “0” to “9” according to the random value R1 acquired in step S205, and reaches the reach determination. Set to the random counter 122. Thus, the reach determination random counter 122 updates the reach determination random value R2 in synchronization with the random value R1 read from the random value storage circuit 179.

  FIG. 20 is a flowchart showing an example of the process executed in step S26 of FIG. 17 as the special symbol process. In the special symbol process shown in FIG. 20, the following steps S110 to S118 are executed according to the value of the special symbol process flag provided in the game control flag setting area such as the RAM 102.

  The special symbol normal process of step S110 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of starting winning prizes stored in the special figure storage unit 121 is “0”. Here, in the special figure hold storage unit 121, when various data such as the random number R1 corresponding to the hold number “1” is not stored, it is determined that the start winning storage number is “0”. If the start winning memory number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the image display device 5 via the effect control board 12. On the other hand, if it is determined that the start winning memorized number is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S111 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 21, the CPU 103 first reads the random number value R1 stored corresponding to the hold number “1” from the special figure hold storage unit 121 (step S221). At this time, “1” is subtracted from the start winning memorized number and stored in the lower four entries (second to fourth entries corresponding to the holding numbers “2” to “4”) in the special figure holding storage unit 121. The random number value R1 is shifted up by one entry (step S222).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability is changing) (step S223). If the probability is being changed (step S223; Yes), whether or not the display result of the special figure game is a big hit. As a table for determining whether or not, a probability change big hit determination table 112 as shown in FIG. 4B is set (step S224). On the other hand, if the probability change is not in progress (step S223; No), it is determined that the game is in the normal gaming state, and the normal big hit determination table 111 as shown in FIG. 4A is set (step S225).

  Based on the random number value R1 read in step S221, the CPU 103 determines whether the display result of the special figure game is a big hit using the big hit determination table 111 or 112 set in step S224 or S225 (step S226). And when it is determined to be a big hit (step S226; Yes), the big hit state flag provided in the game control flag setting area is set to an on state (step S227), and when it is decided to be lost (Step S226; No), the big hit state flag is cleared and turned off (step S228). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the special symbol stop symbol determination process (step S229).

  The special symbol stop symbol determination process of step S112 shown in FIG. 20 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 determines whether or not the big hit state flag provided in the game control flag setting area is on. Then, according to the determination result, a final confirmed symbol in the special symbol game by the special symbol display 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S113 is a process executed when the value of the special symbol process flag is “3”. In this process, as shown in FIG. 22, the CPU 103 first determines whether or not the big hit state flag is on (step S241). When the big hit state flag is ON (step S241; Yes), a big hit variable display pattern determination table is set as a table used to determine the variable display pattern (step S242). At this time, the count values in the reach number counter 124 and the normal loss number counter 125 are cleared and set to “0” (step S243).

  When the big hit state flag is OFF in step S241 (step S241; No), the reach determination random value R2 stored in the reach determination random counter 122 is acquired (step S244). Then, with reference to the reach determination table 113 shown in FIG. 5, it is determined whether or not the variable display mode of the decorative symbols in the image display device 5 is to be reached (step S245).

  When it is determined in step S245 that reach is to be reached (step S245; Yes), a reach variable display pattern determination table is set as a table used to determine the variable display pattern (step S246). At this time, the count value in the normal loss count counter 125 is cleared and set to “0” (step S247), and the count value in the reach count counter 124 is incremented by “1” (step S248).

  When it is determined in step S245 that the reach is not performed (step S245; No), a normal loss variable display pattern determination table is set as a table used for determining the variable display pattern (step S249). At this time, the count value in the reach count counter 124 is cleared and set to “0” (step S250), and the count value in the normal loss count counter 125 is incremented by “1” (step S251).

  After executing any one of steps S243, S248, and S251, the variable set in any of steps S242, S246, and S249 based on the value of the variable display pattern determination random number obtained from a predetermined random counter, for example. By referring to the display pattern determination table, etc., the variable display pattern to be used in the variable display of the special figure game and the decorative design satisfying the start condition is determined (step S252).

  Subsequently, the CPU 103 determines whether or not the count value in the reach number counter 124 exceeds a predetermined reach continuous upper limit value (for example, “10”) (step S253). When the count value in the reach number counter 124 exceeds the reach continuous upper limit value (step S253; Yes), it is determined that a failure is detected in the random number generation circuit 17, and the value of the failure detection flag is set to “1”. (Step S254).

  When it is determined in step S253 that the count value in the reach count counter 124 is equal to or less than the reach continuous upper limit value (step S253; No), the count value in the normal lose count counter 125 is a predetermined normal lose continuous upper limit value (for example, “50”). It is determined whether or not “)” is exceeded (step S255). When the count value in the normal loss count counter 125 exceeds the normal loss continuous upper limit value (step S255; Yes), it is determined that a failure in the random number generation circuit 17 has been detected, and the value of the failure detection flag is set to “ 2 "(step S256).

  When it is determined in step S255 that the count value in the normal losing count counter 125 is equal to or less than the normal losing continuous upper limit value (step S255; No), or after executing any of the processes in steps S254 and S256, the special symbol The value of the process flag is updated to “4” corresponding to the variable display start control process (step S257).

  The variable display start control process of step S114 is a process executed when the value of the special symbol process flag is “4”. FIG. 23 is a flowchart illustrating an example of processing executed as variable display start control processing. In the process shown in FIG. 23, the CPU 103 first determines whether or not the value of the failure detection flag is “0” (step S261). When the value of the failure detection flag is “0” (step S261; Yes), for example, control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S113 described above is transmitted as a predetermined command. The variable display start command is set so as to be able to be sent to the effect control board 12 by setting it in the table (step S262).

  Subsequently, for example, the CPU 103 sets the variable display time of the special symbol corresponding to the variable display pattern to a predetermined variable display time timer provided in the game control counter / timer setting area, starts the countdown, and displays the special symbol display. The setting for starting the variable display of the special symbol by the special symbol display 4 is performed, such as starting the lighting / extinguishing operation of each segment in the device 4 (step S263). Thereafter, the value of the special symbol process flag is updated to “5” which is a value corresponding to the special symbol variable display processing (step S264).

  When it is determined in step S261 that the value of the failure detection flag is other than “0” (step S261; No), it is determined whether or not the failure notification flag is on (step S265). If it is off (step S265; No), for example, control data corresponding to the value of the failure detection flag is set in the command transmission table so that the failure detection command can be sent to the effect control board 12. Setting is made (step S266). At this time, the failure notification flag is set to ON (step S267).

  When the variable display start control process shown in FIG. 23 is further executed after the failure notification flag is set in the ON state, it is determined in step S265 that the failure notification flag is on (step S265; Yes). ), It is determined whether or not a predetermined reset switch provided in the pachinko gaming machine 1 has been turned on (for example, pressed) (step S268). If the reset switch has not been turned on (step S268; No), the variable display start control process ends as it is. Thus, after the failure detection command is sent to the effect control board 12 and the notification that the failure has been detected is started, the special symbol game or image by the special symbol display 4 is kept until the reset switch is turned on. Execution of variable display of decorative symbols on the display device 5 is stopped, and the progress of the game in the pachinko gaming machine 1 is stopped. Even when the progress of the game in the pachinko gaming machine 1 is stopped in this way, for example, when it is detected by the start winning port switch 70 or the like that a game ball has been won at the winning port of the normal variable winning ball device 6 or the like. The payout control command may be output to the payout control board to cause the award ball to be paid out so as not to give the player the disadvantage caused by the progress of the game in the pachinko gaming machine 1 being stopped. .

  When it is determined in step S268 that the reset switch has been turned on (step S268; Yes), the failure notification flag is cleared and turned off (step S269), and the value of the failure detection flag is set to “ It is updated to “0” (step S270).

  Further, as the variable display start control process in step S114, a process as shown in FIG. 24 may be executed. In the process shown in FIG. 24, when it is determined in step S261 that the value of the failure detection flag is other than “0” (step S261), a failure detection command can be sent to the effect control board 12. After setting (step S271), after clearing the failure detection flag and setting its value to “0” (step S272), the process proceeds to step S262, and the special symbol display 4 displays the special symbol variablely or the image. Setting for starting variable display of decorative symbols on the display device 5 is performed.

  In the variable display start control process shown in FIG. 24, even when a failure is detected in the random number generation circuit 17, the special symbol display by the special symbol display 4 and the variable display of the decorative symbol by the image display device 5 can be executed. Yes, the progress of the game in the pachinko gaming machine 1 is not stopped. In this case, in response to receiving the failure detection command from the main board 11 on the side of the effect control board 12, the normal time (including the normal gaming state, the probability improvement state, the jackpot gaming state, as will be described later) By executing a specific effect different from that in the pachinko gaming machine 1 in which no failure is detected in the random number generation circuit 17, it is possible to specify that a failure in the random number generation circuit 17 has been detected. By notifying, it is possible to prevent the player from being disadvantaged.

  The special symbol variable display process in step S115 is a process executed when the value of the special symbol process flag is “5”. This process is repeatedly executed until the variable display time timer times out, and when the time out occurs, a setting for sending a variable display end command from the main board 11 to the effect control board 12 is performed. Specifically, the variable display end command is set to be able to be sent to the effect control board 12 by setting control data corresponding to the variable display end command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S116 is a process executed when the value of the special symbol process flag is “6”. In this processing, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S117 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches, for example, 16, the condition for ending the specific gaming state (big hit gaming state) is established. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S118 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the effect control board 12. Moreover, CPU103 clears the big hit state flag provided in the game control flag setting area, and makes it an OFF state. Then, the value of the special symbol process flag is updated to “0”.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, the effect control CPU 105 determines whether or not a predetermined timer interrupt flag is turned on, for example, detects the occurrence of a timer interrupt every 33 milliseconds. Various timer interrupt processing programs stored in advance in a predetermined ROM or the like mounted on the substrate 12 for effect control are executed. In addition, the effect control CPU 105 generates an interrupt for receiving the effect control command from the main board 11 separately from the timer interrupt that occurs every 33 milliseconds. This interruption is generated when, for example, an effect control INT signal from the main board 11 is turned on. When an interruption occurs due to the turn-on of the effect control INT signal, the effect control CPU 105 automatically sets the interrupt prohibited state, but uses a CPU that does not automatically enter the interrupt prohibited state. Preferably issues an interrupt disable instruction (DI instruction).

  When the production control INT signal from the main board 11 is turned on, an interruption is generated in the production control CPU 105, for example, a predetermined command reception interrupt process is executed, and the control signal transmitted from the main board 11 is transmitted. The effect control command read from the predetermined input port that receives is stored in the reception command buffer. For example, when the effect control command has a 2-byte configuration, the first byte (MODE) and the second byte (EXT) are sequentially received and stored in the reception command buffer, and then the interrupt permission is set.

  FIG. 25 is a flowchart showing an example of the display control process executed every time the effect control CPU 105 detects the occurrence of a timer interrupt. When the display control process shown in FIG. 25 is started, first, it is determined whether or not a failure detection command is received from the main board 11 (step S141). When it is determined that a failure detection command has been received (step S141; Yes), a setting is made to notify that a failure has been detected in the random number generation circuit 17 in accordance with the received failure detection command (step S142). ).

  For example, when the failure detection command from the main board 11 is the command B000 (h) transmitted when the number of continuous determinations to reach reach exceeds the reach continuous upper limit value, The CPU 105 controls the display operation in the image display device 5 to display character information as shown in FIG. 26A, for example, to notify that a failure in the random number generation circuit 17 has been detected. The production is executed. On the other hand, when the failure detection command from the main board 11 is a command B001 (h) transmitted when the number of times of continuous determination of normal loss exceeds the normal continuous upper limit value, The control CPU 105 controls the display operation in the image display device 5 to display character information as shown in FIG. 26B, for example, to notify that a failure in the random number generation circuit 17 has been detected. A specific performance is executed.

  When the process shown in FIG. 24 is executed as the variable display start control process of step S114, the decorative display variable display by the image display device 5 is executed even when a failure in the random number generation circuit 17 is detected. May be. In this case, when the failure control command from the main board 11 is received, the effect control CPU 105 displays the random number generation circuit including the normal game state, the probability improvement state, and the jackpot game state by the display of the image display device 5. By executing a specific effect different from that in the gaming state in the pachinko gaming machine 1 in which no failure is detected in 17, the fact that a failure in the random number generation circuit 17 has been detected is notified. As a specific example, when the background color of the image displayed on the image display device 5 is white in the normal gaming state and orange in the probability improvement state, when a failure detection command is received from the main board 11, What is necessary is just to make it display an image different from normal time, such as changing a background color to green. Alternatively, when the variable display of the decorative symbol is started when the failure detection command is received, the decorative symbol is displayed in a reduced size compared with the normal time, and the random number generating circuit 17 displays the display region generated by the reduced display. Character information or the like for notifying that a failure has been detected may be displayed.

  When it is determined in step S141 that a failure detection command has not been received (step S141; No), after executing the process of step S142, the process is shown in FIG. 25 based on the value of a predetermined display control process flag. One of the six processes of steps S150 to S155 is selected. Below, each process of step S150-S155 is demonstrated.

  The variable display start command reception waiting process in step S150 is a process executed when the value of the display control process flag is “0”. In this process, the effect control CPU 105 determines whether or not a variable display start command from the main board 11 has been received. If it is determined that it has been received, the value of the display control process flag is set to the decorative symbol variable display start process. The corresponding value is updated to “1”.

  The decorative symbol variable display start process in step S151 is a process executed when the value of the display control process flag is “1”. In this process, the effect control CPU 105 controls the image display device 5 so as to start variable display of all the decorative symbols. For example, the effect control CPU 105 variably displays decorative symbols in the image display device 5 based on the variable display pattern specified by the variable display start command received in the variable display start command reception waiting process of step S150 described above. The final symbol of the decorative symbol to be derived and displayed is set as the final display result. Then, display control of the image display device 5 is performed to start variable display of decorative symbols, and then the value of the display control process flag is updated to “2” which is a value corresponding to the processing during variable decorative symbols display.

  The decorative symbol variable display process of step S152 is a process executed when the value of the display control process flag is “2”. In this process, the effect control CPU 105 performs display control of the image display device 5 during variable display of decorative symbols. For example, the production control CPU 105 has elapsed since the variable display pattern designated by the variable display start command received in the variable display start command reception waiting process of step S150 described above, or the variable display of the decorative design was started. Corresponding to the time and the like, image data stored in advance in a predetermined CGROM mounted on the effect control board 12 is read out to a predetermined VDP (Video Display Processor) or the like, and the decorative pattern in the image display device 5 is read. An effect by displaying an image according to the progress of variable display is executed. Then, when the elapsed time from the start of the variable display of the decorative symbol reaches the variable display time corresponding to the variable display pattern, the value of the display control process flag is a value corresponding to the decorative symbol stop waiting process “3”. Update to

  The decorative symbol stop waiting process in step S153 is a process executed when the value of the display control process flag is “3”. In this process, the effect control CPU 105 determines whether or not the variable display end command from the main board 11 has been received. If it is determined that the command has been received, the display result is displayed by the variable display of the decorative pattern on the image display device 5. The fixed symbol that becomes is derived and displayed, and the variable display of the decorative symbol is terminated. When the display result of variable display is a big hit, the value of the display control process flag is updated to “4” which is a value corresponding to the display process during the big hit, and when the display is lost, the value of the display control process flag is changed to “4”. Update to "0".

  The big hit display process in step S154 is a process executed when the value of the display control process flag is “4”. In this process, the effect control CPU 105 performs display control of the image display device 5 to display an image corresponding to the big hit gaming state. For example, by displaying the number of rounds corresponding to a predetermined jackpot round number command transmitted from the main board 11 on the image display device 5, the number of rounds being executed in the jackpot gaming state can be specified for the player. Can be notified. When the round executed in the big hit gaming state becomes the final round (for example, the 16th round), the value of the display control process flag is updated to “5”, which is a value corresponding to the big hit end display processing.

  The big hit end display process in step S155 is a process executed when the value of the display control process flag is “5”. In this processing, the effect control CPU 105 performs control for causing the image display device 5 to execute effect display for notifying that the big hit gaming state has ended.

  As described above, according to this embodiment, in the random number generation circuit 17 having the configuration as shown in FIG. 7, the clock signal generation circuit 175 is connected from the negative phase output terminal Q (bar) to the input terminal D. The latch clock signal S3 fed back is latched in response to the rising edge of the reference clock signal S1 input from the clock terminal CK, thereby generating the count clock signal S2 and outputting it from the positive phase output terminal Q. To do. Further, the clock signal generation circuit 175 inverts the generated count clock signal S2 and outputs the latch clock signal S3 from the reverse phase output terminal Q (bar).

  The counter 174 sequentially updates the count value C at timings T10, T12,... When the count clock signal S2 input from the positive phase output terminal Q of the clock signal generation circuit 175 rises from the low level to the high level. .

  When a game ball wins the normal variable winning ball apparatus 6 which is a starting winning opening, the starting winning opening switch 70 sends a starting winning signal SS to the main board 11 and the random number generating circuit 17, and the random number generating circuit. The start winning signal SS sent to 17 is input to the input terminal D of the latch signal output circuit 173 via the timer circuit 172. The latch signal output circuit 173 converts the start winning signal SS input to the input terminal D into a latch clock signal S3 input from the reverse phase output terminal Q (bar) of the clock signal generation circuit 175 to the clock terminal CK. The latched clock signal S3 is output from the output terminal Q as the latch signal SL at the timing T11 when the latch clock signal S3 rises from the low level to the high level.

  The random value storage circuit 179 responds the count value C input from the counter 174 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 173 to the clock terminal CK. Then, it is latched and stored as a random value R1.

  In this way, the random number generation circuit 17 having the configuration as shown in FIG. 7 includes the timings T10, T11,... At which the reference clock signal S1 output from the reference clock signal output circuit 171 rises from the low level to the high level. The count value C can be updated at timings T10, T12,..., And the latch signal SL can be output at timings T11, T13,. Thereby, the update timing of the count value C by the counter 174 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 173 can be reliably made different. In addition, since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S1, even if the falling edge of the reference clock signal S1 is gentle, the update is performed. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R1.

  In the random number generation circuit 17 having the configuration shown in FIG. 12, the selector 177 is input from the reference clock signal output circuit 171 when the frequency-divided clock signal S4 input from the frequency-dividing circuit 176 is at a high level. By outputting the reference clock signal S1 from the first output terminal O1, the first output clock signal S5 rising from the low level to the high level is supplied to the counter 174 at the timings T20, T21,. On the other hand, when the divided clock signal S4 is at the low level, the reference clock signal S1 is output from the second output terminal, and the second output clock signal S6 that rises from the low level to the high level at timings T30, T31,. Is supplied to the latch signal output circuit 173.

  The counter 174 sequentially updates the count value C at the timings T20, T21,... At which the first output clock signal S5 input from the first output terminal O1 in the selector 177 rises from the low level to the high level. . The latch signal output circuit 173 synchronizes the start winning signal SS input from the start winning port switch 70 with the second output clock signal S6 input from the second output terminal O2 to the clock terminal CK in the selector 177. At the timing T31 when the second output clock signal S6 rises from the low level to the high level, it is output to the random value storage circuit 179 as the latch signal SL.

  In this way, the random number generation circuit 17 having the configuration as shown in FIG. 12 has the timings T20, T30, T21, T31 when the reference clock signal S1 output from the reference clock signal output circuit 171 rises from the low level to the high level. ,..., The count value C can be updated at timings T20, T21,..., And the latch signal SL can be output at timings T30, T31,. Thereby, the update timing of the count value C by the counter 174 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 173 can be reliably made different. In addition, since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S1, even if the falling edge of the reference clock signal S1 is gentle, the update is performed. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R1.

  In the random number generation circuit 17 having the configuration as shown in FIG. 14, the counter 174 includes timings T40, T41,... At which the reference clock signal S1 having a period T input from the reference clock signal output circuit 171 rises from a low level to a high level. , The latch signal output circuit 173 causes the delay signal 178 to delay the reference clock signal S1 by ΔT (≠ nT) by the delay circuit 178. In synchronization with the generated delay clock signal S7, the delay clock signal S7 is output to the random value storage circuit 179 as a latch signal SL at a timing T51 when the delay clock signal S7 rises from a low level to a high level.

  In this way, the random number generation circuit 17 having the configuration shown in FIG. 14 counts at the timings T40, T41,... At which the reference clock signal S1 output from the reference clock signal output circuit 171 rises from the low level to the high level. The value C is updated, and the latch signal SL can be output at timings T50, T51,... Different from the timings T40, T41,. Thereby, the update timing of the count value by the counter 174 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 173 can be reliably made different. Further, since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S1, the update timing is updated even when the rising edge of the reference clock signal S1 is gradual. And latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R1.

  On the other hand, on the main board 11 side, the CPU 103 continues the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). When the input is detected, the processing after step S202 shown in FIG. 18 is executed to enable acquisition of the random value R1 from the random number generation circuit 17. In this processing, the CPU 103 sends an output control signal SC to the random value storage circuit 179 to control the random value storage circuit 179 to a readable (enable) state, and then reads the random value R1 from the random value storage circuit 179. Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 179 and controls the random value storage circuit 179 so that it cannot be read (disabled), and then the read random value R1 becomes the predetermined determination value “ It is determined whether or not the display result of the special symbol display by the special symbol display device 4 or the variable symbol display on the image display device 5 is a big hit by determining whether or not it coincides with “2001 to 2184” or the like. .

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 179 to the readable state only when the CPU 103 reads the random number value R1. Can do. In addition, since the CPU 103 reads the random number value R1 from the random value storage circuit 179 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  Further, the random number generation circuit 17 does not directly input the start winning signal SS output from the start winning port switch 70 to the latch signal output circuit 173, but instead inputs the start winning signal SS to the timer circuit 172 and inputs the start winning signal SS. The time is measured, and when the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 173. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 173 from erroneously outputting the latch signal SL to the random value storage circuit 179 due to the influence of noise or the like. Since the timer circuit 172 is set to “3 ms” shorter than “4 ms” between the executions of the two timer interrupt processes, the random number value R1 read out from the random number storage circuit 179 by the CPU 103 is the previous value. It is possible to prevent the random value R1 read at the time of winning from being the same value.

  When the latch signal SL is input from the latch signal output circuit 173, the random value storage circuit 179 converts the output control signal (high level signal) SC input from the game control microcomputer 100 into a low level signal. By doing so, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R1 from the random value storage circuit 179 when the random value R1 stored in the random value storage circuit 179 is updated. 1 can update the random number value R1 reliably and stably.

  Further, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 179 converts the latch signal (high level signal) SL input from the latch signal output circuit 173 into a low level signal. By converting to, the latch signal SL is controlled so as not to be received. Thereby, when the game control microcomputer 100 reads the random value R1 from the random value storage circuit 179, it is possible to prevent the random value R1 stored in the random value storage circuit 179 from being updated. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R1.

  Every time the CPU 103 acquires the random number R1 for jackpot determination from the random value storage circuit 179 in step S205 of FIG. 18, the random number R2 for reach determination corresponding to the acquired random number R1 is determined in step S210. Set in the reach determination random counter 122. Thus, the reach determination random value R2 stored in the reach determination random counter 122 is updated in synchronization with the jackpot determination random value R1 read from the random value storage circuit 179 of the random number generation circuit 17. become. The reach determination random counter R2 set in the reach determination random counter 122 is read by the CPU 103 in step S244 shown in FIG. 22, and is used to determine whether or not to reach in step S245. Is done. For this reason, when the random number generation circuit 17 fails and the random number value R1 is not updated, the reach determination random number value R2 is not updated, and the decorative pattern can be changed a plurality of times in the image display device 5. In the display, the variable display mode is continuously reached, or the display is normally lost without reaching reach for a long period of time.

  With such a variable display mode of decorative symbols, the player can estimate whether or not a failure has occurred in the random number generation circuit 17 and can prevent a significant disadvantage from being caused when a failure occurs. Generally, the probability that the variable display mode of decorative symbols will reach is set to be higher than the probability that the variable display result will be a big hit. The occurrence of a failure can be estimated in a shorter period than when it is estimated that a failure has occurred in the circuit 17.

  Therefore, when the determination to reach is made in step S245, the number of times that the determination to reach is made continuously over a plurality of variable displays is performed, and the count value of the reach number counter 124 is set in step S248. Count by adding "1". Further, when it is determined in step S245 that the reach is not reached, the number of times that the determination of normal loss is made continuously over a plurality of variable displays is made, and in step S251, the normal loss count counter 125 is counted. Count by adding "1" to the value. Then, when it is determined in step S253 that the count value of the reach counter 124 exceeds a predetermined reach continuous upper limit value, or in step S255, the count value of the normal lose count counter 125 is set to a predetermined normal lose. When it is determined that the continuous upper limit value is exceeded, it is determined that a failure has been detected in the random number generation circuit 17 and the failure detection flag is set in step S266 shown in FIG. 23 or step S271 shown in FIG. A setting is made so that a failure detection command corresponding to the value can be sent from the main board 11 to the effect control board 12.

  On the side of the production control board 12, the production control CPU 105 makes a setting for notifying that a failure has been detected in step S142 of FIG. 25 in response to the failure detection command from the main board 11, for example, FIG. As shown to (A) and (B), the specific effect by the display in the image display apparatus 5 different from normal time is performed, and it can alert | report that a failure was detected. By this notification, the player can easily recognize that a failure has occurred in the random number generation circuit 17 and can prevent being disadvantaged.

  Note that the random determination value R2 for reach determination is updated in synchronization with the random value R1 for jackpot determination, even if the random value R1 for jackpot determination itself is used as the random value R2 for reach determination. Good. In this case, as shown in FIG. 27, the reach determination table 113 is configured from setting data that associates a determination result indicating whether or not the variable display mode of the decorative symbol is a reach with a random value R1 for determining the big hit. . Then, in step S210 in FIG. 18, the jackpot determination random value R1 itself acquired from the random number generation circuit 17 may be set in the reach determination random counter 122 as the reach determination random value R2.

  The numerical data updated in synchronization with the jackpot determination random number R1 is not limited to the reach determination random value R2, but is, for example, a notice determination randomness used for determining the effect mode in the notice effect. The random display pattern determination random number value used for determining the variable display pattern that determines the numerical value and the variable display mode of the decorative design may be updated in synchronization with the random number R1 for jackpot determination. . In this case, as in the case of the reach determination random value R2 in the above embodiment, for example, in step S210 in FIG. 18, a table for associating the jackpot determination random value R1 with each random value is referred to. Then, it may be updated to a random value corresponding to the random number R1 for jackpot determination acquired from the random number generation circuit 17. Further, the random number R1 for jackpot determination may be used as various random values. For example, when the random number value for determining the notice is updated in synchronization with the random number value R1 for determining the jackpot, when the random number generation circuit 17 has failed and the random number value R1 has not been updated, Since the random number value for determining the notice will not be updated, the notice effect that is the same effect form is continuously executed in the special display game and the variable display of the decorative pattern multiple times, or the notice effect is given over a long period of time. Will not be executed. With such an execution mode of the notice effect, the player can estimate whether or not a failure has occurred in the random number generation circuit 17, and can be prevented from suffering a significant disadvantage when a failure occurs.

  In the above embodiment, the random number value R2 for reach determination is updated in synchronization with the random number value R1 for jackpot determination read from the random value storage circuit 179 of the random number generation circuit 17, so that the decorative pattern is updated. The occurrence of a failure in the random number generation circuit 17 can be estimated when the variable display mode is continuously reached or the display result is normal loss without reaching for a long time. On the other hand, the game control microcomputer 100 holds the jackpot determination random number value R1 acquired from the random number generation circuit 17, and the random number value R1 acquired from the random number generation circuit 17 for the predetermined number of times is the same value. The occurrence of a failure in the random number generation circuit 17 may be estimated. Hereinafter, an example of the pachinko gaming machine 1 that can estimate the occurrence of a failure in the random number generation circuit 17 by holding the random number value R1 acquired from the random number generation circuit 17 will be described.

  In this embodiment, for example, a RAM 102 provided in the game control microcomputer 100 is provided with a jackpot determination random value holding area 130 as shown in FIG. In the jackpot determination random value holding area 130, the jackpot determination random number R1 obtained from the random number generation circuit 17 is set and held. The variable display data holding area 120 is provided with a coincidence counter 126. The coincidence number counter 126 is for counting the number of times that the random number value R1 held in the jackpot determination random number value holding area 130 and the random number value R1 acquired from the random number generation circuit 17 are matched continuously.

  FIG. 29 is a flowchart showing an example of a process executed in step S25 of FIG. 17 as the start winning process in this embodiment. The processes in steps S201 to S209 shown in FIG. 29 are the same as the processes in steps S201 to S209 shown in FIG. In the start winning process shown in FIG. 29, after the process of step S209 is executed, a failure detection process as shown in FIG. 30 is executed (step S211).

  In the failure detection process shown in FIG. 30, the CPU 103 first determines that the random number value R1 held in the jackpot determination random value holding area 130 is the random value R1 acquired from the random number generation circuit 17 in step S205 of FIG. It is determined whether or not they match (step S301). Then, when the stored random number value is different from the acquired random number value (step S301; No), the coincidence number counter 126 is cleared and the count value is set to “0” (step S302). In step S205, the random value R1 acquired from the random number generation circuit 17 is set and held in the jackpot determination random value holding area 130 (step S303).

  When it is determined in step S301 that the stored random number value matches the acquired random number value (step S301; Yes), the count value of the matching number counter 126 is incremented by “1” (step S301). S304). Then, it is determined whether or not the count value of the match count counter 126 added with “1” in step S304 exceeds a predetermined match count upper limit value (for example, “10”) (step S305). At this time, if the count value of the coincidence counter 126 is equal to or less than the upper limit of coincidence (step S305; No), the failure detection process is terminated as it is.

  On the other hand, when the count value of the match count counter 126 exceeds the match count upper limit value in step S305 (step S305; Yes), the failure detection flag provided in the game control flag setting area is set to the on state. To do. Then, when the process shown in FIG. 23 is executed as the variable display control process in step S114 in the special symbol process shown in FIG. 20, it is determined whether or not the failure detection flag is turned on in step S261. When it is off, steps S262 to S264 are executed, and when it is on, steps S265 to S270 are executed. When the process as shown in FIG. 24 is executed as the variable display control process in step S114, it is determined in step S261 whether or not the failure detection flag is on. The processing of S272 is executed, and when it is off, those processing is skipped and the processing of steps S262 to S264 is executed.

  On the side of the production control board 12, when the production control CPU 105 executes the display control process shown in FIG. 25 and determines that a failure detection command is received in step S141 (step S141; Yes), in step S142. Settings are made to notify that a failure has been detected in the random number generation circuit 17.

  For example, when the process as shown in FIG. 23 is executed as the variable display process in step S114, the image display device 5 is set until the predetermined reset switch is turned on after the failure detection flag is set to the on state. Execution of the variable display of the decorative pattern in is stopped. Therefore, the effect control CPU 105 controls the display operation in the image display device 5 to display the character information as shown in FIG. 31A, for example, so that a failure in the random number generation circuit 17 is detected. What is necessary is just to perform the specific production which alert | reports to the effect. On the other hand, when the process as shown in FIG. 24 is executed as the variable display control process in step S114, even when a failure in the random number generation circuit 17 is detected, the decorative display variable display by the image display device 5 is performed. May be executed. Therefore, for example, as shown in FIG. 31 (B), the effect control CPU 105 indicates that the failure in the random number generation circuit 17 has been detected by displaying the character information 60 even during the variable display of the decorative symbols. What is necessary is just to perform the specific production to alert | report. When the background color of the image displayed on the image display device 5 is white in the normal gaming state and orange in the probability improvement state, the effect control CPU 105 receives a failure detection command from the main board 11. In addition, the image display device 5 may execute an image display different from the normal time, such as changing the background color to green.

  As described above, according to this embodiment, every time the random number value R1 is read from the random number generation circuit 17 in step S205 in FIG. 29, the read random number value and the jackpot determination random value holding area 130 are read. It is determined in step S301 in FIG. When it is determined that they do not match, the random number value R1 acquired from the random number generation circuit 17 is set and held in the jackpot determination random value holding area 130. By adding “1” to the count value, the number of times that the match is continuously determined is counted. Thereafter, when it is determined in step S305 that the count value of the match count counter 126 exceeds the predetermined match count upper limit value, it is determined that a failure in the random number generation circuit 17 has been detected, and FIG. In step S266 shown in FIG. 24 and step S271 shown in FIG. 24, a setting is made so that a failure detection command can be sent from the main board 11 to the effect control board 12.

  On the side of the production control board 12, the production control CPU 105 makes a setting for notifying that a failure has been detected in step S142 in FIG. 25 in response to the failure detection command from the main board 11, for example, FIG. As shown in 31 (A) and (B), it is possible to notify that the failure has been detected by executing a specific effect by display on the image display device 5 different from the normal time. By this notification, the player can easily recognize that a failure has occurred in the random number generation circuit 17 and can prevent being disadvantaged.

  Note that it may be determined that a failure in the random number generation circuit 17 has been detected when a predetermined period has elapsed without updating the random number value held in the jackpot determination random value holding area 130. In this case, for example, an elapsed time timer that measures an elapsed time since the random number value R1 acquired from the random number generation circuit 17 is set in the jackpot determination random value holding area 130 is provided. Then, when the random number value R1 is acquired from the random number generation circuit 17 in step S205 in FIG. 29, whether or not the random number value acquired in the same manner as in step S301 in FIG. 30 matches the stored random number value. When it is determined that they do not match, the acquired random number value is set in the jackpot determination random value holding area 130 and measurement of the elapsed time by the elapsed time timer is started.

  On the other hand, when it is determined that the acquired random number value does not match the stored random number value, it is determined whether or not the elapsed time measured by the elapsed time timer has reached a predetermined failure detection reference time. When it is determined that the failure detection reference time has been reached, it may be determined that a failure in the random number generation circuit 17 has been detected. Note that when the player finishes the game in the pachinko gaming machine 1, the measurement of the elapsed time by the elapsed time timer may be ended. For example, it is detected by a touch sensor or the like whether or not the hitting operation handle provided in the pachinko gaming machine 1 is operated, and when the handle operation is not performed, the elapsed time timer is cleared and the elapsed time measurement is ended. You can do it. As a result, since the game is not performed in the pachinko gaming machine 1, the random number value R1 is not read from the random number generation circuit 17, and accordingly, the random number value held in the big hit determination random value holding area 130 is also updated. Therefore, it is possible to prevent the elapsed time measured by the elapsed time timer from reaching the failure detection reference time and erroneously detecting that a failure has occurred in the random number generation circuit 17.

  In addition, the present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, the start winning port switch 70 outputs a start winning signal SS only to the main board 11, and the CPU 103 mounted on the main board 11 executes a timer interruption process a predetermined number of times (for example, twice). The start winning signal SS for latch is sent to the latch signal output circuit 173 of the random number generation circuit 17 based on the continuous input of the start winning signal SS from the start winning port switch 70 during the period (for example, for 4 ms). You may do it.

  For example, in the random number generation circuit 17 configured as shown in FIG. 7, the timer circuit 172 is removed, and the input terminal D of the latch signal output circuit 173 is an output terminal for outputting a latch start winning signal at the I / O port 104. Connect to. Thus, the latch signal output circuit 173 synchronizes the latch start winning signal input from the input terminal D with the latch clock signal S3 input from the clock terminal CK, and at the rising edge of the latch clock signal S3. A latch signal SL rising from the low level to the high level is output from the output terminal Q.

  Further, in the random number generation circuit 17 configured as shown in FIG. 12, the timer circuit 172 is removed, and the output for outputting the start winning signal for latching at the input terminal D of the latch signal output circuit 173 at the I / O port 104. Connect to the terminal. Accordingly, the latch signal output circuit 173 synchronizes the latch start winning signal input from the input terminal D with the second output clock signal S6 input from the clock terminal CK, and the second output clock signal S6 It is output from the output terminal Q as a latch signal SL that rises from a low level to a high level at the rising edge.

  Further, in the random number generation circuit 17 configured as shown in FIG. 14, the timer circuit 172 is removed, and the input terminal D of the latch signal output circuit 173 is output to output a start winning signal for latching at the I / O port 104. Connect to the terminal. As a result, the latch signal output circuit 173 synchronizes the latch start winning signal input from the input terminal D with the delayed clock signal S7 input from the clock terminal CK, and at a low level at the rising edge of the delayed clock signal S7. Is output from the output terminal Q as a latch signal SL that rises from high to low.

  Even in this case, the random number generation circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In such a case, in the start winning process executed in step S25 of FIG. 17, it is first determined whether or not a predetermined random value read flag provided in the game control flag setting area is on. This random value read flag is set to the on state when the latch start winning signal is sent to the latch signal output circuit 173, and is cleared to the off state when the random value R1 is read from the random value storage circuit 179. .

  When the random number read flag is off, the same processing as steps S201 to S204 shown in FIG. 18 is executed. When the start winning memorized number is less than the predetermined upper limit value in step S204, a latch start winning signal is sent to the latch signal output circuit 173 and the random number read flag is set to the on state.

  If the random value read flag is on when the start winning process is started, an output control signal SC is sent to the random value storage circuit 179 to control the random value storage circuit 179 to a readable (enable) state. . Subsequently, the CPU 103 reads the random value R1 from the random value storage circuit 179, stores the read random value R1 in, for example, a predetermined buffer area provided in the RAM 102, and then controls output to the random value storage circuit 179. The transmission of the signal SC is stopped, and the random value storage circuit 179 is controlled to be unreadable (disabled). Thereafter, the CPU 103 adds “1” to the number of starting winning prizes stored, sets the random value R1 stored in the predetermined buffer area at the head of the empty entry in the special figure reservation storage unit 121, and clears the random number read flag. To turn it off.

  According to the above configuration, the CPU 103 of the main board 11 receives the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Based on the continuous input, it is determined that the game ball has won the normal variable winning ball apparatus 6, and a latch start winning signal is sent to the random number generation circuit 17. For this reason, the pachinko gaming machine 1 does not need to be provided with a path for supplying the start winning signal SS from the start winning port switch 70 to the random number generation circuit 17, and the hardware configuration can be simplified.

  The latch start winning signal sent to the random number generation circuit 17 is input to the input terminal D of the latch signal output circuit 173 and is output from the output terminal Q as the latch signal SL. Thereby, in the random number generation circuit 17, the update timing of the count value C by the counter 174 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 173 can be reliably made different. In addition, since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S1, even if the falling edge of the reference clock signal S1 is gentle, the update is performed. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R1.

  Further, the CPU 103 determines that the game ball has won the normal variable winning ball device 6 based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. Therefore, the pachinko gaming machine 1 can prevent the latch start winning signal from being erroneously output to the random number generation circuit 17 due to the influence of noise or the like.

  When the CPU 103 determines that a game ball has won the normal variable winning ball apparatus 6, the CPU 103 reads the random value R1 from the random value storage circuit 179 in the first timer interruption process. It is possible to prevent the numerical value R1 from becoming the same value as the previously read random number value R1.

  In the above embodiment, it is determined whether or not the count value of the reach number counter 124 exceeds the predetermined reach continuous upper limit value in step S253 shown in FIG. 22, and the normal loss count counter is determined in step S255. By determining whether or not the count value of 125 exceeds a predetermined normal loss continuous upper limit value, the variable display mode is continuously reached in variable display of a plurality of decorative symbols, and over a long period of time. It has been described that it is determined that a failure has been detected in the random number generation circuit 17 in both cases where the display result of normal loss is obtained without reaching reach. However, the present invention is not limited to this, and in the case where the variable display mode is continuously reached in the variable display of the decorative pattern a plurality of times, and the display result of normal loss without reaching reach for a long period of time. In at least one of the cases, it may be determined that a failure in the random number generation circuit 17 has been detected. For example, when the variable display mode is continuously reached in the variable display of a plurality of decorative symbols by removing the normal lose count counter 125 and counting only the number of times of reach continuously by the reach count counter 124, It can be determined that a failure in the random number generation circuit 17 has been detected. Further, for example, when the reach number counter 124 is removed and only the number of times of normal loss is continuously detected by the normal loss number counter 125, a random number is displayed when a normal loss display result is obtained without reaching reach for a long period of time. It can be determined that a failure in the generation circuit 17 has been detected.

  Notification that a failure has been detected in the random number generation circuit 17 is executed as a specific effect by display on the image display device 5 after the variable display of the decorative symbols on the image display device 5 or after the end of the big hit gaming state. May be. Furthermore, for example, the count value of the reach count counter 124 exceeds the reach continuous upper limit value in step S253 shown in FIG. 22, or the count value of the normal lose count counter 125 exceeds the normal lose continuous upper limit value in step S255. Or when it is determined in step S305 in FIG. 30 that the count value of the match count counter 126 exceeds the match count upper limit value or the like, it is determined that a fault has been detected in the random number generation circuit 17. This is stored in a predetermined backupable RAM or non-volatile memory (for example, EEPROM), and once the pachinko gaming machine 1 is turned off, the failure is detected when the power is turned on next time. May be notified. When a failure is detected in the random number generation circuit 17, not only a display operation by the image display device 5, but also an operation of turning on a predetermined error lamp or generating a warning sound from the speakers 8L and 8R. In addition, it may be notified that a failure in the random number generation circuit 17 has been detected only by turning on an error lamp or generating a warning sound.

  In the random number generation circuit 17 configured as shown in FIG. 7, the positive phase output terminal Q of the clock signal generation circuit 175 is used as the clock terminal CK of the latch signal output circuit 173, and the negative phase output terminal Q (bar) is used as the input terminal of the counter 174. , Each may be connected. The counter 174 is not limited to an up counter, and may be a down counter. Further, the numerical value updating means is not limited to that by the counter 174, and may be a pseudo random number generation circuit. Further, the connection between the output terminal of the bit data C0 to C15 of the count value C of the counter 174 and the input terminal of the bit data C0 to C15 of the count value C of the random value storage circuit 179 may be rearranged. Thereby, the randomness of the count value C input to the random value storage circuit 179 can be improved.

  In the above embodiment, the random value storage circuit 179 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 230 to 245 to control the reception of the latch signal SL and the output control signal SC, and to output the random value R1. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 179 is provided with a switching element such as a field effect transistor (FET) between the I / O port 104 and the latch signal output circuit 173, and the latch signal SL. In response to the input of the output control signal SC and the path to the I / O port 104 and the latch signal output circuit 173, the latch signal SL and the enable / disable control of the output control signal SC are performed. Also good.

  Further, in the above embodiment, the timer circuit 172 is activated in response to the input of the high level signal, and the reference clock signal from the reference clock signal output circuit 171 while the input is at the high level. In response to the input of S1, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, it is determined that the input signal is a high level signal. The signal is output to the latch signal output circuit 173. However, the present invention is not limited to this, and the timer circuit 172 measures the time during which the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. Any signal may be used as long as it outputs the winning signal SS to the latch signal output circuit 173.

  In the above embodiment, the timer circuit 172 measures the signal input time using the reference clock signal S1 sequentially input from the reference clock signal output circuit 171, but the present invention is not limited to this. Instead, the timer circuit 172 may use a clock signal obtained by dividing the reference clock signal S1 or a clock signal output from a clock signal output circuit different from the reference clock signal output circuit 171. In the above embodiment, the timer circuit 172 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, and from the 4 ms, which is the execution time of two timer interrupt processes. Any time can be set as long as the time is short.

  Further, in the above-described embodiment, the CPU 103 performs the processes after step S202 shown in FIG. 18 based on the fact that the start winning signal SS is continuously input while the timer interruption process is executed twice. Was running. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. May be executed on and after step S202 shown in FIG. In this case, the timer circuit 172 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  The game control microcomputer 100 may incorporate a random number generation circuit 17. When the random number generation circuit 17 is incorporated in the game control microcomputer 100 as described above, it is possible to secure a board space and to generate a random number value generated by the random number generation circuit 17 by installing an illegal board or the like. It is difficult to rewrite the numerical data indicating the value from the outside, and forgery can be prevented.

  In the above-described embodiment, the gaming machine can perform a variable display start condition (for example, the special symbol game 4 by the special symbol display 4 and the previous special game after the variable display execution condition (for example, winning the normal variable winning ball device 6) is established) A variable display device (for example, the special symbol display 4 or the image display device) that variably displays a plurality of types of identification information (for example, special symbols or decorative symbols) that can be identified based on the fact that the big hit gaming state is completed) 5) and described as a pachinko gaming machine 1 that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of the variable display becomes a predetermined specific display result. did.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  As shown in FIG. 32, the gaming machine of the present invention can start a game by setting the number of bets for one game, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 32 uses a game control means (for example, a main board) or a random number generation circuit as a start winning signal output means of the present invention based on a start lever 1011 operated by a player. A start switch (not shown) for outputting to (for example, a random number generation circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 32 functions as an effect unit, and for example, a specific effect is executed by the display of the liquid crystal display 1001 in the same manner as the image display device 5 in the above embodiment. Thus, it may be notified that a failure has been detected in the random number generation circuit.

  As long as the gaming machine of the present invention has an image display device, it may be, for example, a general electric machine or a ball game machine with a probability setting function called a pachi-kon. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  Further, the device configuration shown in FIGS. 1 and 32, the block configuration shown in FIGS. 2, 7, 9, 12, and 14, the command configuration shown in FIG. 3, the tables shown in FIGS. 4, 5, and 27. Configuration, memory configuration shown in FIGS. 6 and 28, circuit configuration shown in FIG. 8, timing chart configurations shown in FIGS. 10, 11, 13, and 15, FIG. 16, FIG. 17, FIG. 18, FIG. 22, FIG. 23, FIG. 24, FIG. 25, FIG. 29 and FIG. 30, the random number configuration shown in FIG. 19, and the display examples shown in FIGS. 26 and 31 do not depart from the spirit of the invention. Changes and modifications can be arbitrarily made within the range.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a figure which shows an example of the content of an effect control command. It is a figure which shows the structural example of a big hit determination table. It is a figure which shows the structural example of a reach determination table. It is a block diagram which shows the structural example of the data holding area for variable display. It is a block diagram which shows the structural example of a random number generation circuit. It is a circuit diagram which shows the structural example of a random value storage circuit. It is a figure for demonstrating the connection of the output terminal of the OR circuit of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random value storage circuit. It is a timing chart for demonstrating operation | movement of the random number generation circuit of FIG. It is a block diagram which shows the other structural example of a random number generation circuit. 13 is a timing chart for explaining the operation of the random number generation circuit of FIG. 12. It is a block diagram which shows the further another structural example of a random number generation circuit. It is a timing chart for demonstrating operation | movement of the random number generation circuit of FIG. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a game control interruption process. It is a flowchart which shows an example of a start winning process. It is a figure which shows an example which sets the random value for reach determination. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a big hit determination process. It is a flowchart which shows an example of a variable display pattern setting process. It is a flowchart which shows an example of a variable display start control process. It is a flowchart which shows another example of the variable display start control process. It is a flowchart which shows an example of a display control process process. It is a figure which shows the example of a display in an image display apparatus. It is a figure which shows the other structural example of a reach determination table. It is a block diagram which shows the other structural example in the data holding area for variable displays. It is a flowchart which shows another example of a start winning process. It is a flowchart which shows an example of failure detection processing. It is a figure which shows the other example of a display in an image display apparatus. It is a front view of a slot machine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Special symbol display device 5 ... Image display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp DESCRIPTION OF SYMBOLS 11 ... Main board 12 ... Production control board 13 ... Audio | voice output circuit 14 ... Lamp driver circuit 17 ... Random number generation circuit 21, 22 ... Solenoid 40 ... Normal symbol display 70 ... Start winning port switch 100 ... Game control microcomputer 101 ... ROM
102 ... RAM
103 ... CPU
104 ... I / O port 105 ... Production control CPU
DESCRIPTION OF SYMBOLS 107 ... Switch circuit 108 ... Solenoid circuit 111 ... Normal big hit judgment table 112 ... Probability change big hit judgment table 113 ... Reach judgment table 120 ... Variable display data holding area 121 ... Special figure reservation memory | storage part 122 ... Reach judgment random counter 123 ... Start winning port switch timer 124 ... Reach count counter 125 ... Normal loss count counter 126 ... Match count counter 130 ... Big hit determination random value holding area 171 ... Reference clock signal output circuit 172 ... Timer circuit 173 ... Latch signal output circuit 174 ... Counter 175 ... Clock signal generation circuit 176 ... Frequency divider 177 ... Selector 178 ... Delay circuit 179 ... Random value storage circuits 201, 203 ... AND circuits 202, 204 ... NOT circuits 210-225 ... Flop circuit 230~245 ... OR circuit

Claims (12)

A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
A clock signal generating means for generating a plurality of signals having the same period and different phases based on the reference clock signal;
The clock signal generation means includes
A clock terminal to which the reference clock signal is input from the reference clock signal output means;
An input terminal to which the first signal is input;
A first output terminal that outputs a signal in which a change state of the first signal is synchronized with a timing that changes at every predetermined period of the reference clock signal input from the clock terminal;
A second output terminal that outputs a signal having the same period and a different phase as the signal output from the first output terminal;
The clock signal generation means includes
By connecting the second output terminal and the input terminal, the first clock signal output from the first output terminal and the first clock signal output from the second output terminal And a second clock signal having the same period and different phases,
The random number generating means includes
Numerical data updating means for updating numerical data at a first timing when the first clock signal generated by the clock signal generating means changes in a predetermined manner;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing when the second clock signal generated by the clock signal generation means changes in the predetermined manner; ,
Random number storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Numerical data acquisition means for acquiring numerical data updated in synchronization with the numerical data updated by the numerical data update means;
Effect determining means for determining whether or not to execute a predetermined effect by determining whether or not the numerical data acquired by the numerical data acquisition means matches predetermined effect determination value data ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
Numerical value updating means for updating numerical data at a first timing among a plurality of timings at which the reference clock signal output from the reference clock signal output means changes in a predetermined manner every predetermined period;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing different from the first timing among the plurality of timings;
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Numerical data acquisition means for acquiring numerical data updated in synchronization with the numerical data updated by the numerical data update means;
Effect determining means for determining whether or not to execute a predetermined effect by determining whether or not the numerical data acquired by the numerical data acquisition means matches predetermined effect determination value data ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
A clock signal delay for generating a delayed clock signal by delaying a reference clock signal input from the reference clock signal output means by a period different from a period that is an integral multiple of the predetermined period, and outputting the generated delayed clock signal Means,
A first timing at which a reference clock signal input from the reference clock signal output means changes in a predetermined manner at each predetermined period and a delayed clock signal input from the clock signal delay means at every predetermined period. Numerical value updating means for updating numerical data at any one of the second timing that changes in a predetermined manner;
The start signal input from the start signal output means is output as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means among the first timing and the second timing. Latch signal output means;
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Numerical data acquisition means for acquiring numerical data updated in synchronization with the numerical data updated by the numerical data update means;
Effect determining means for determining whether or not to execute a predetermined effect by determining whether or not the numerical data acquired by the numerical data acquisition means matches predetermined effect determination value data ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. An effect continuation number measuring means for measuring the number of times that the variable display start condition for which the determination to execute the predetermined effect is made by the effect determining means is established,
An effect avoidance frequency measuring means for measuring the number of times that the variable display start condition is continuously established, which is determined not to execute the predetermined effect by the effect determining means,
Production continuous notification control means for performing control for notifying that the production continuous upper limit number has been exceeded when the number of times measured by the production continuous number measurement unit exceeds a predetermined production continuous upper limit number;
When the number of times measured by the effect avoidance number measuring means exceeds a predetermined effect avoidance upper limit number of times, the effect avoidance notification control means for performing control to notify that the effect avoidance upper limit number of times has been exceeded,
The gaming machine according to claim 1, 2, or 3. The production continuous notification control means performs control to notify that the production continuous upper limit has been exceeded by causing a specific production to be executed,
The effect avoidance notification control means performs control to notify that the effect avoidance upper limit number has been exceeded by executing the specific effect.
The gaming machine according to claim 4, wherein: A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
A clock signal generating means for generating a plurality of signals having the same period and different phases based on the reference clock signal;
The clock signal generation means includes
A clock terminal to which the reference clock signal is input from the reference clock signal output means;
An input terminal to which the first signal is input;
A first output terminal that outputs a signal in which a change state of the first signal is synchronized with a timing that changes at every predetermined period of the reference clock signal input from the clock terminal;
A second output terminal that outputs a signal having the same period and a different phase as the signal output from the first output terminal;
The clock signal generation means includes
By connecting the second output terminal and the input terminal, the first clock signal output from the first output terminal and the first clock signal output from the second output terminal And a second clock signal having the same period and different phases,
The random number generating means includes
Numerical data updating means for updating numerical data at a first timing when the first clock signal generated by the clock signal generating means changes in a predetermined manner;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing when the second clock signal generated by the clock signal generation means changes in the predetermined manner; ,
Random number storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Random number value holding means for holding a random value read from the random value storage means;
Random number value matching judgment means for judging whether or not the random number value read from the random number value storage means matches the random number value held in the random number value holding means;
Random value update for updating a random value to be held in the random value holding means to a new random value read from the random value storage means when it is determined by the random value match judging means that they do not match Means,
A continuous number counting unit that counts the number of times that the determination that the random number value matching unit matches is made; and
Continuous number determination means for determining whether the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit;
A failure detection means for detecting that a failure has occurred in the reference clock signal output means by determining that the continuous upper limit value has been exceeded by the continuous frequency determination means ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
Numerical value updating means for updating numerical data at a first timing among a plurality of timings at which the reference clock signal output from the reference clock signal output means changes in a predetermined manner every predetermined period;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing different from the first timing among the plurality of timings;
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Random number value holding means for holding a random value read from the random value storage means;
Random number value matching judgment means for judging whether or not the random number value read from the random number value storage means matches the random number value held in the random number value holding means;
Random value update for updating a random value to be held in the random value holding means to a new random value read from the random value storage means when it is determined by the random value match judging means that they do not match Means,
A continuous number counting unit that counts the number of times that the determination that the random number value matching unit matches is made; and
Continuous number determination means for determining whether the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit;
A failure detection means for detecting that a failure has occurred in the reference clock signal output means by determining that the continuous upper limit value has been exceeded by the continuous frequency determination means ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
The random number generating means includes
Reference clock signal output means for generating and outputting a reference clock signal of a predetermined period;
A clock signal delay for generating a delayed clock signal by delaying a reference clock signal input from the reference clock signal output means by a period different from a period that is an integral multiple of the predetermined period, and outputting the generated delayed clock signal Means,
A first timing at which a reference clock signal input from the reference clock signal output means changes in a predetermined manner at each predetermined period and a delayed clock signal input from the clock signal delay means at every predetermined period. Numerical value updating means for updating numerical data at any one of the second timing that changes in a predetermined manner;
The start signal input from the start signal output means is output as a latch signal at a timing different from the timing at which the numerical data is updated by the numerical value update means among the first timing and the second timing. Latch signal output means;
Random number value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means,
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Random number value holding means for holding a random value read from the random value storage means;
Random number value matching judgment means for judging whether or not the random number value read from the random number value storage means matches the random number value held in the random number value holding means;
Random value update for updating a random value to be held in the random value holding means to a new random value read from the random value storage means when it is determined by the random value match judging means that they do not match Means,
A continuous number counting unit that counts the number of times that the determination that the random number value matching unit matches is made; and
Continuous number determination means for determining whether the continuous number counted by the continuous number counting means exceeds a predetermined continuous upper limit;
A failure detection means for detecting that a failure has occurred in the reference clock signal output means by determining that the continuous upper limit value has been exceeded by the continuous frequency determination means ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. When the failure detection means detects that a failure has occurred in the reference clock signal output means, the failure detection means comprises a failure occurrence notification control means for performing a control for notifying that a failure has occurred in the reference clock signal output means,
The gaming machine according to claim 6, 7 or 8. The random number generation means measures a time during which a start signal is input from the start signal output means, and outputs a start signal to the latch signal output means when the measured time reaches a predetermined time. Including means,
The gaming machine according to any one of claims 1 to 9, wherein the gaming machine is characterized by that. The game control means includes a timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal input periodically.
The display result determining means is based on the fact that a start signal is continuously input from the start signal output means while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes. Read the random value from the random value storage means,
The timer means includes
Setting means for setting, as the predetermined time, a time shorter than a time when a predetermined number of timer interrupt processes are executed by the timer interrupt process executing means;
When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.
The gaming machine according to claim 10. The random value storage means includes an output control signal reception control means for controlling the output control signal output from the read control means to an unreceivable state when a latch signal is input from the latch signal output means. ,
The gaming machine according to any one of claims 1 to 11 , characterized in that:

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