JP2003190483A - Pachinko game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To update a counter not by software but by hardware. <P>SOLUTION: A pachinko game machine includes a random number clock generating circuit for generating a random number clock by a prescribed frequency, a random number clock inverting circuit for generating an inversion clock which is obtained by inverting the random number clock, a clock counting circuit for counting the number of clocks based on the input of the starting edge of one of the random number clock and the inversion clock, a latch signal output circuit for synchronizing a start prize-winning signal from a start prize- winning port with the input of the starting edge of the other one of the random number clock and the inversion clock and outputting it as a latch signal and a count value storage circuit for storing a count value counted by the clock counting circuit based on the latch signal. The storage value of the count value storage circuit is referred to based on a prescribed condition and, then, winning is determined concerning prize-winning in the start prize-winning port based on the storage value. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to winning determination in a ball game machine, and more particularly, to winning determination in which random numbers for lottery are generated by hardware based on winning of a hit ball at a starting winning opening.

[0002]

2. Description of the Related Art Conventionally, in a ball game machine, a winning opening called a starting winning opening is provided in a game area on a game board, and a winning decision is made based on the winning of a hit ball at the starting winning opening. Those that provide a predetermined profit for a player (for example, a so-called jackpot game) based on the result of the winning are widely used.

In such a ball game machine, usually, the reference clock of the CPU that controls the game is counted by software, and the value of this count is obtained as a random number when the start winning hole is won. The winning decision is being made. It should be noted that the count of the reference clock or the like, which is the source of the random number, is not a random number in a strict sense because it is regularly performed, for example, by incrementing by 1, but the trigger for the acquisition is the start winning a prize hole. The value of the count thus obtained substantially functions as a random number because it is a randomly occurring event such as winning a prize. Such random numbers are called software random numbers.

[0004]

However, when the random number is generated by the above method, there is a problem that the load of software processing becomes large. In addition, there is a problem that one cycle of the counter becomes relatively long due to the nature of the software random number that the addition interval of the counter has to be set in milliseconds because of software processing. Therefore, if there are a plurality of winning random numbers to be compared with the count value, setting them close to each other or increasing the total range of the random numbers increases the time required for one cycle of the counter, resulting in a win. There is a problem in that fraud prevention is difficult because the time that can take a random value is limited.

Furthermore, in recent years, updating of random number values and CPU
There is a new problem that an illegal act such as manipulating the winning signal to forcibly win the prize is performed because the operation is synchronized with the action of, and the solution of this problem is urgently required. Therefore, in the present invention, by updating the counter not by software but by hardware, high speed and CPU
By using a random number generation means that is asynchronous with the operation of, not only the burden on the software, which is a problem of the conventional technology, can be reduced, but also a random number with a large range can be used and fraud from outside is not likely to occur. The purpose is to realize the winning decision.

[0006]

In view of the above problems, the ball game machine according to the present invention has a starting winning opening for generating a starting winning signal by winning a hit ball and a random number for generating a random number clock at a predetermined frequency. A clock generating circuit; a random number clock inverting circuit that generates an inverted clock by inverting the random number clock from the random number clock generating circuit; and a rising edge or a falling edge of one of the random number clock and the inverted clock. A clock counting circuit that counts the number of clocks based on an input, and the start winning signal is output as a latch signal in synchronization with the input of the rising edge or the falling edge of the other clock of the random number clock and the inverted clock. Latch signal output circuit and the clock based on the latch signal And a count value storage circuit for storing the count value counted by the count circuit, referring to the stored value of the count value storage circuit based on a predetermined condition, and winning the start winning opening based on the stored value. It is characterized in that the winning decision relating to is performed.

With the above configuration, it is possible to generate a random number by hardware. Also, from the above configuration, when the clock count circuit counts based on the rising edge of the random number clock, the latch signal is output by the rising edge of the inverted clock, and the random number clock When counting is performed based on the input of the falling edge of, the latch signal is output by the input of the falling edge of the inverted clock, and the count is performed based on the input of the rising edge of the inverted clock in the clock count circuit. If the rising edge of the random number clock is input, the latch signal is output, and if counting is performed based on the input of the falling edge of the inverted clock in the clock count circuit, the rising edge of the random number clock is output. Falling edge Since the latch signal is output by the input of the clock, in either case, the timing of incrementing the count and the timing with the latch are shifted by a half cycle, and it is possible to obtain a stable count in the state where the increment is fixed. It is possible.

In view of the above problems, the ball game machine according to the present invention provides a first starting winning opening for generating a first starting winning signal by winning a hit ball and a second starting winning signal by winning a hit ball. A ball game machine equipped with a second starting winning opening to be generated and a starting winning signal judging means for judging the input of the first starting winning signal and the second starting winning signal, and a random number clock at a predetermined frequency. A random number clock generating circuit for generating the random number clock, a random number clock inverting circuit for generating an inverted clock by inverting the random number clock from the random number clock generating circuit, and a rising edge or a rising edge of one of the random number clock and the inverted clock. A clock count circuit for counting the number of clocks based on the input of the falling edge, and the first start winning signal for the random number clock and the A first latch signal output circuit that outputs a first latch signal in synchronization with an input of a rising edge or a falling edge of the other clock of the inverted clock; and a second start winning signal of the random number clock and the inverted clock. A second latch signal output circuit that outputs a second latch signal in synchronization with an input of a rising edge or a falling edge of the other clock, and a count value counted by the clock count circuit based on the first latch signal And a second count value storage circuit for storing the count value counted by the clock count circuit based on the second latch signal, the first winning value determination means The first cow is determined based on the determination that there is a prize at the starting winning opening. It is determined that the winning value relating to the winning in the first starting winning opening is determined based on the stored value of the automatic starting value storing circuit, and that the starting winning determining means has won the second starting winning opening. Based on the determination, the stored value of the second count value storage circuit is referred to, and based on the stored value, the winning determination regarding the winning of the second starting winning opening is performed.

With the above configuration, it is possible to generate a random number by hardware. Further, according to the above configuration, when counting is performed in the clock count circuit based on the input of the rising edge of the random number clock, the first latch signal and the second latch signal are output by the input of the rising edge of the inverted clock. When the clock count circuit performs counting based on the falling edge input of the random number clock, the first latch signal and the second latch signal are output by the input of the falling edge of the inverted clock, and the clock count circuit In the case where the counting is executed based on the input of the rising edge of the inverted clock in, the first latch signal and the second latch signal are output by the input of the rising edge of the random number clock, and the inverted clock of the inverted clock is output in the clock count circuit. Falling edge input When the counting is performed based on, the first latch signal and the second latch signal are output by the input of the falling edge of the random number clock. Therefore, in either case, the count increment is performed. The timing between the latch and the latch is shifted by a half cycle, and a stable count can be obtained in a state where the increment is fixed. Furthermore, 2
Even when the winnings at the one starting winning opening occur simultaneously or at extremely short intervals, it is possible to separately obtain the counts as random numbers without the winnings interfering with each other.

Further, in the ball game machine according to the present invention, even when three or more starting winning openings are provided, by providing a latch signal output circuit and a count value storage circuit respectively corresponding to them. Even when the winnings to the respective winning a prize openings occur simultaneously or at extremely short intervals, it is possible to separately obtain the counts as random numbers without the winnings interfering with each other.

In view of the above problems, the ball game machine according to the present invention includes a starting winning opening for generating a starting winning signal by winning a hit ball, and a random number clock generating circuit for generating a random number clock at a predetermined frequency. A random number clock inverting circuit that generates an inverted clock by inverting the random number clock from the random number clock generation circuit, and based on input of a rising edge or a falling edge of one of the random number clock and the inverted clock. A clock count circuit that counts the number of clocks, and a latch signal that synchronizes a signal generated based on the input of the start winning signal with the input of the rising edge or the falling edge of the other clock of the random number clock and the inverted clock. And a latch signal output circuit that outputs the And a count value storage circuit for storing the count value counted by the clock count circuit, referring to the stored value of the count value storage circuit based on a predetermined condition, and based on the stored value, the starting winning opening It is characterized in that the winning determination relating to winning the prize is performed.

With the above configuration, it is possible to generate a random number by hardware. Also, from the above configuration,
The start winning signal controls the ball game machine, for example, CP
When a signal (such as a signal for urging the latching of the count value) that is input to the control unit including U and RAM and is generated by the control unit is output to the latch signal output circuit, a random number is generated in the clock count circuit. When counting is performed based on the input of the rising edge of the clock, the latch signal is output by the input of the rising edge of the inverted clock, and the count is performed based on the input of the falling edge of the random number clock in the clock count circuit. If the falling edge of the inverted clock is input, the latch signal is output, and if the clock count circuit counts based on the input of the rising edge of the inverted clock, A latch signal is output by the input, and In the clock count circuit, when counting is performed based on the input of the falling edge of the inverted clock, the latch signal is output by the input of the falling edge of the random number clock. Also, the timing of the increment of the count and the timing of the latch are shifted by a half cycle, and it is possible to obtain the stable count in the state where the increment is fixed.

In view of the above-mentioned problems, the ball game machine according to the present invention provides a first starting winning opening for generating a first starting winning signal by winning a hit ball and a second starting winning signal by winning a hit ball. A ball game machine equipped with a second starting winning opening to be generated and a starting winning signal judging means for judging the input of the first starting winning signal and the second starting winning signal, and a random number clock at a predetermined frequency. A random number clock generating circuit for generating the random number clock, a random number clock inverting circuit for generating an inverted clock by inverting the random number clock from the random number clock generating circuit, and a rising edge or a rising edge of one of the random number clock and the inverted clock. A clock count circuit that counts the number of clocks based on the input of the falling edge, and a signal generated based on the input of the first start winning signal Based on a first latch signal output circuit that outputs a first latch signal in synchronization with an input of a rising edge or a falling edge of the other clock of the random number clock and the inverted clock, based on an input of the second start winning signal A second latch signal output circuit for synchronizing the generated signal with a rising edge or a falling edge of the other clock of the random number clock and the inverted clock and outputting the second latch signal, and the first latch signal. A first count value storage circuit that stores the count value counted by the clock count circuit based on the second count value storage circuit, and a second count value storage circuit that stores the count value counted by the clock count circuit based on the second latch signal. And the starting winning a prize determination means to the first starting winning a prize mouth The stored value of the first count value storage circuit is referred to on the basis that it is determined that there is a winning, and the winning determination relating to the winning on the first starting winning opening is performed based on the stored value, and the starting winning Based on the determination means that the second start winning opening has been won, the stored value of the second count value storage circuit is referred to, and the second starting winning opening is won based on the stored value. It is characterized in that the winning decision relating to is performed.

With the above configuration, it is possible to generate a random number by hardware. Also, from the above configuration,
The first start prize signal and the second start prize signal are input to a control unit including a CPU, a ROM, and the like that controls the ball game machine, for example, and a signal generated by the control unit based on the signal (prompts to latch the count value) Signal) is output to the first latch signal output circuit and the second latch signal output circuit, respectively. When counting is performed in the clock count circuit based on the input of the rising edge of the random number clock, , When the rising edge of the inverted clock is input, the first latch signal and the second latch signal are output, and when the clock count circuit performs counting based on the input of the falling edge of the random number clock, the rising edge of the inverted clock When the falling edge is input, the first latch signal and the second latch signal are output. If the counting circuit executes counting based on the input of the rising edge of the inverted clock, the first latch signal and the second latch signal are output by the input of the rising edge of the random number clock, and When counting is performed based on the input of the falling edge of the clock, the first latch signal and the second latch signal are output according to the input of the falling edge of the random number clock. Even in this case, the timing between the increment of the count and the latch is shifted by a half cycle, and the stable count can be acquired in the state where the increment is fixed. Furthermore, 2
Even when the winnings at the one starting winning opening occur simultaneously or at extremely short intervals, it is possible to separately obtain the counts as random numbers without the winnings interfering with each other.

Further, in the ball game machine according to the present invention, even when three or more starting winning openings are provided, by providing a latch signal output circuit and a count value storage circuit respectively corresponding thereto. Even when the winnings to the respective winning a prize openings occur simultaneously or at extremely short intervals, it is possible to separately obtain the counts as random numbers without the winnings interfering with each other.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION (1) First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a front view showing an outer appearance of a game board 20 of a ball game machine 10 according to the present embodiment. Figure 2
FIG. 3 is a block diagram conceptually showing a part related to random number generation in the present embodiment. 3 and 4 conceptually show the components of this embodiment in a tree diagram. FIG. 5 is a random number generator according to the present embodiment.
50 is a circuit diagram. FIG. 6 is a timing chart showing signals generated in this embodiment. Then, FIG. 7 to FIG. 10 are flowcharts showing the procedure of obtaining and using the random number in the present embodiment.

(1-1) Appearance of Ball Gaming Machine The appearance of the game board 20 of the ball gaming machine 10 according to the present embodiment will be described below with reference to FIG. A symbol display device 21 for variably displaying a "special symbol" composed of a combination of three-digit symbols on a liquid crystal screen is located in the approximate center of the game board 20. It should be noted that, of these special symbols, those in which all three digits are made up of a combination of the same types of symbols are referred to as "big hit symbols". Further, above the symbol display device 21, four special symbol holding lamps 90, 90, 90, 90 are provided.

Below the symbol display device 21, there is provided a first starting winning opening 22 through which a hit ball can be won. This first
The opening of the starting winning opening 22 is provided with an enlarging device 91 for enlarging the width of the first starting winning opening 22. The expanding device 91 normally keeps a width such that one hit ball can pass but two hit balls cannot pass at the same time. It becomes easy to win a prize in the winning opening 22. In addition, in the flow path of the ball hitting from the first starting winning opening 22, a first starting winning sensor 23 for detecting the winning of the hit ball is provided.

Below the first starting winning opening 22, an attacker unit 92 is attached, and a part of the attacking unit 92 serves as a large winning opening 26 which is opened during a jackpot game described later. Also, on the left and right ends of this attacker unit 92,
Winning holes 93, 93 are provided. Further, on the front surface of the attacker unit 16, a normal symbol display device 94 by a 7-segment light emitting diode is provided, and four ordinary symbol holding lamps 95, 95, 95, 95 are provided around it. This normal symbol display device 94 has "5",
A "normal design" consisting of a single digit number selected from three types of numbers "6" and "7" is displayed. In addition, among these ordinary symbols, "7" is referred to as "enlarged symbol".

On the left side of the symbol display device 21, a gate 96 through which a hit ball can pass is provided. The gate 96 is provided with a sensor (not shown) that detects passage of a hit ball. On the right side of the symbol display device 21, there is provided a second starting winning opening 24 in which a hit ball can be won. This second start winning hole 24
In the flow path of the hit ball from the
A start winning sensor 25 is provided.

Winning holes 93, 93 are also provided on the left and right sides of the first starting winning hole 22. Furthermore, at the lower end of the game board 20, a hit ball that cannot be won at any of the first start winning opening 22, the second starting winning opening 24, the big winning opening 26, and each of the winning openings 93, 93, 93, 93. An outlet 97 is provided for discharging. In addition to the above, the game board 20 is provided with windmills 98, 98, 98, 98, 98, 98 and nails (not shown) for changing the falling direction of the hit ball. The front surface of the game board 20 is covered with a glass plate (not shown). Furthermore, game board
Below the 20, a ball handle, a prize ball payout opening, and a ball tray (not shown) are located.

(1-2) Outline of the game The outline of the game in the ball game machine 10 is as follows. First, the player operates a ball handle (not shown) to hit a ball on the game board 20. This hit ball drops the game board 20 while contacting each windmill 98, 98, 98, 98, 98, 98, the nail (not shown), or the like. Then, when one of the winning openings 93, 93, 93, 93 is won in the process of dropping, five prize balls are paid out to the player from the prize ball payout opening (not shown).

When the hit ball passes through the gate 96, the normal symbol starts changing in the normal symbol display device 94. And
Normally, 30 seconds after the fluctuation starts,
A predetermined ordinary symbol that has already been determined at the start of fluctuation is stopped and displayed. When the normal symbol that is stopped and displayed is the enlarged symbol "7", the enlarging device 91 operates for 0.5 seconds, and the width of the first start winning opening 22 is enlarged, so that the winning in the first starting winning opening 22 is won. Will be easier. Further, when the normal symbol displayed in a stopped state is "5" or "6" which is not the enlarged symbol, the enlarging device 91 does not operate, but even in this case, the winning to the first start winning port 22 is possible. In addition, ordinary symbol display device
When the hit ball passes through the gate 96 during the variation display at 94, the normal symbol holding lamps 95, 95, 95, 95 are 4 at maximum.
It is supposed to illuminate up to the individual pieces. That is, the operation of the normal symbol display device 94 thereafter is guaranteed by the number of times corresponding to the number of the normal symbol holding lamps 95, 95, 95, 95 being lit.

When there is a prize at the first starting winning opening 22 or the second starting winning opening 24, five prize balls are paid out to the player from the prize ball payout opening (not shown), and a symbol is displayed. The device 21 operates and the fluctuation of the symbol is started. As a result of this change, when the special symbol displayed in a stopped state is the big hit symbol, a "big hit game" occurs. In this jackpot game, the jackpot 26 that is normally closed is opened. When there is a prize in the special winning opening 26, 15 prize balls are paid out to the player from the prize ball payout opening (not shown). This special winning opening 26 opens for 30 seconds or 10
It will be closed once there is a winning ball. And while this big winning opening 26 is open, this big winning opening
When there is a prize in a V zone (not shown) provided inside 26, the special winning opening 26 is to be closed and then opened again. As a result, the opening of the special winning opening 26
It is possible to continue up to 16 times. In addition, when the big winning opening 26 finishes opening 16 times, or when there is no winning in the above-mentioned V zone while opening the big winning opening 26, this big hit game ends. In addition, when the ball hits the first starting winning opening 22 or the second starting winning opening 24 during the variable display on the symbol display device 21, the special symbol holding lamps 90, 90, 90, 90 are 4 at maximum. It is supposed to illuminate up to the individual pieces. That is, this special symbol holding lamp 90, 90, 90,
The subsequent operation of the symbol display device 21 is guaranteed only for the number of times 90 is lit.

(1-3) Game board In the ball game machine 10 according to the present embodiment, as described above, a prize is generated on the game board 20, which triggers the variable display of the special symbol on the symbol display device 21. Two start winning openings are provided. These are the first starting winning opening 22 and the second starting winning opening 24.
Called. By the winning of any of the starting winning openings, the variable display of the special symbol is similarly performed.

As shown in FIG. 2 and FIG. 3, a first starting prize sensor 23 using an optical sensor is provided in the flow path of the hit ball from the first starting prize hole 22. The first starting winning a prize sensor 23 outputs a first starting winning a prize signal having two states of a high signal and a low signal. This first start winning signal outputs a high signal when the hit ball is not detected (that is, when the detection light beam is not blocked), but while the hit ball is passing (that is, It outputs a low signal only when the detection beam is blocked. In addition, in another embodiment different from the present embodiment, a magnetic or mechanical sensor may be used as the first start winning sensor 23.

In the flow path of the hit ball from the second starting winning opening 24,
Second start prize sensor 25 using an optical sensor (see Fig. 3)
Is provided. The second start prize sensor 25 outputs a second start prize signal having two states of a high signal and a low signal. The second start winning signal outputs a high signal when a hit ball is not detected, but outputs a low signal only while the hit ball is passing. In addition, in another embodiment different from this embodiment, a magnetic or mechanical sensor may be used as the second start winning sensor 25.

The special winning opening 26 provided in the game board 20 is a winning opening that is opened and closed by the operation of the solenoid 27 when a special symbol of a predetermined type is displayed as a result of the variable display on the symbol display device 21. . (1-4) Game control device As shown in FIGS. 2 and 3, the game control device 15 controls the main control unit 30 and a main control unit 30 that executes control of the ball game machine 10 according to a control program. And a random number generation device 50 for generating a random number regardless of.

(1-4-1) Main control section (1-4-1-1) Reference clock generation circuit, CPU, R
The OM / RAM main control unit 30 includes a reference clock generation circuit 31.
Is provided. The reference clock generation circuit 31 is a circuit that generates a reference clock that serves as an operation reference of the CPU 32 that is the center of control, and generates a pulse at a predetermined interval using a crystal oscillator, a crystal oscillator, or the like. In this embodiment, the reference clock generation circuit 31 is 4.096M.
A pulse of Hz is generated and this pulse itself is used as a reference clock. In another embodiment, a reference clock may be obtained by appropriately dividing this pulse.

The control program to be executed by the CPU 32 and the data required in the control process are stored in the ROM 33. The numerical values of the parameters generated and changed during the control process are temporarily stored in the RAM 34. (1-4-1-2) Input circuit unit Since the input circuit unit 35 receives the input information from the outside of the game control device 15 and the random number generated by the random number generator 50 provided in the game control device 15. I for the buffer
It is composed of C and the like.

Specifically, the input circuit section 35 receives the input signals from the first start prize winning sensor 23 and the first sensor input section 36 and the second start prize sensor 25. The second sensor input unit 37, the upper random number reading unit 38 into which the upper 8 bits of the random number generated by the random number generator 50 is input, and the lower random number reading unit 39 into which the lower 8 bits are input
Is provided.

Each of the first sensor input section 36 and the second sensor input section 37 is provided with a capacitor for removing chattering of the winning signal and an inverting circuit for logically inverting. Therefore, the signals passing through these input sections are input as a high signal when winning and a low signal when not winning. (1-4-1-3) Output circuit section The output circuit section 40 is a signal such as a control signal to electric parts outside the game control device 15 and a random number generated by the random number generation device 50 provided in the game control device 15. Is for outputting a signal for reading, and is composed of an IC such as a buffer.

Specifically, in the output circuit section 40, a game control device such as the symbol display device 21 or a prize ball control device (not shown).
A sub-control signal output unit 42 that outputs a signal to a sub-control device (not shown) that executes control of each unit based on a control signal from 15, a solenoid that outputs a drive signal that drives the solenoid 27 for opening and closing the special winning opening 26. When the drive signal output unit 43 and the game control device 15 determine that the first start winning port 22 has won, the first read signal that triggers the reading of the random number value corresponding to the first winning is output. When the read signal output unit 44 and the game control device 15 determine that the second start winning opening 24 has won, the second read signal that triggers the reading of the random number value corresponding to this winning is output. Read signal output unit 45
Is provided.

In another embodiment, the first read signal and the second read signal are directly output as the address signal generated by the address decoding circuit without passing through the output circuit section 40. Good. (1-4-2) Random Number Generator Next, the functional blocks of the random number generator will be described with reference to FIGS. 2 and 4.

The random number generator generates a count value used as a random number. Specifically, the random number clock generation circuit 51, the random number clock inverting circuit 55, the first latch signal output circuit 60, the second latch. The signal output circuit 65, the clock count circuit 70, the first count value storage circuit 80, and the second count value storage circuit 85. In addition, in the present invention, the random number is not only a value randomly generated in a mathematical sense, but even if the generation is regular, the timing of its acquisition is random, so that it substantially functions as a random number. It also means possible values.

(1-4-2-1) Random Number Clock Generating Circuit The random number clock generating circuit 51 is for generating a clock for a random number and is provided with a random number clock output section 52 for outputting the generated random number clock. There is. Specifically, a crystal oscillator (OCS) that generates a 14.9105 MHz clock (hereinafter referred to as “original oscillation”) that is asynchronous with the reference clock described above.
1) and 74HC74 (IC15) connected to the output terminal of this crystal oscillator and functioning as a flip-flop circuit that divides the original oscillation by 1/2 and outputs it as a random number clock to the clock count circuit 70 (IC1 to IC4) ). That is, in the IC15 of FIG. 5, as the random number clock obtained by dividing the original oscillation by 1/2, the random number clock output unit 52, 1Q.
The functional part that outputs from the terminal is the random number clock generation circuit 51
It is supposed to form a part of.

Here, the flip-flop circuit is interposed so that when the output from the oscillator is directly output, fan-out (malfunction due to capacity over of the output terminal)
This is because there may be a problem of (1) or the waveform may be distorted. With this configuration, it is possible to output a clock having a stable waveform to another device.

In another embodiment, another device such as a gate IC may be interposed in order to avoid the above problems. In other embodiments, like the reference clock generation circuit 31 described above,
Other devices such as a crystal oscillator may be used as the circuit configuration. Furthermore, regarding the oscillation frequency, the above-mentioned 14.810
Although not limited to 5 MHz, using the same frequency as the reference clock generation circuit 31 for the CPU 32 or a frequency that is an integral multiple thereof may generate random numbers in synchronization with the reference clock. , Not preferable.

In the present embodiment, the above flip-flop circuit (IC15) is the random number clock inverting circuit described below.
It also has 55 functions. In this way, by sharing the circuit with a part of the random number clock generation circuit 51 and the random number clock inversion circuit 55, the number of devices can be reduced. (1-4-2-2) Random Number Clock Inversion Circuit The random number clock inversion circuit 55 (IC15) is composed of 74HC74.

That is, the random number clock inverting circuit 55 is provided by the random number clock generating circuit 51 to the random number clock output section 52.
The random number clock output via (1Q) is inverted, and the inverted clock is used as the inverted clock.
Q) is output to the first latch signal output circuit 60 (IC13) and the second latch signal output circuit 65 (IC14). That is, in the IC15 of FIG. 5, a signal obtained by inverting the signal output from the 1Q terminal is used as the inverted signal, and the inverted clock output unit
58 The functional portion that outputs from the barrel inverting 1Q terminal constitutes the random number clock inverting circuit 55.

That is, the rising edge of the random number clock corresponds to the falling edge of the inverted clock, and the falling edge of the random number clock corresponds to the rising edge of the inverted clock (see FIG. 6). In the present embodiment, the random number clock inverting circuit 55 is configured using the flip-flop circuit, but in other embodiments, instead of this, an I / O gate such as a NOT gate is used.
It may be configured by using C.

(1-4-2-3) Clock Counting Circuit The clock counting circuit 70 comprises a random number clock input section 71 for inputting a random number clock and a count output section 72 for outputting the counted value. Specifically, as shown in FIG. 5, it is composed of a circuit in which four 4-bit increment counters (IC1 to IC4) are cascade-connected, and the addition is performed at the rising edge of the random number clock generated by the random number clock generation circuit 51. , A circuit for outputting the addition result. Each increment counter has 74
Composed of HC161.

A random number clock from the random number clock generation circuit 51 is input to the clock count circuit 70 via a random number clock input section 71 (each CK terminal). By inputting the random number clock, first, in IC1, a count is added from "0000" to "1111". Then, "111
When it changes from "1" to "0000" again, the carry signal of IC1
Output from the CO pin to the ENT pin of IC2. In IC2, the count is added only when the carry signal and the random number clock are simultaneously input.

Similarly, the carry addition signal from IC2 is required for the count addition of IC3, and the carry signal input from IC3 is required for the count addition of IC4. In this way, the clock count circuit 70
A 16-bit binary number is to be generated. That is, of the 16-digit binary number, IC1 is the lowest 4 digits, I
C2 is in charge of the upper 4 digits, IC3 is in charge of the upper 4 digits, and IC4 is in charge of the upper 4 digits.

The counts added by the clock count circuit 70 are counted by the count output section 72 (each QA, Q
It is output to the first count value storage circuit 80 and the second count value storage circuit 85 via the B, QC and QD terminals. In this embodiment, the count is incremented by the random number clock generated by the random number clock generation circuit 51, but in another embodiment, the random number clock generated by the random number clock generation circuit 51 is changed to a latch signal described later. It may be configured to output to the output circuit and increment using the inverted clock. Further, although the count is incremented by the rising edge of the random number clock in the present embodiment, it may be incremented by the falling edge of the random number clock in other embodiments. Furthermore, although an addition type increment counter is used in the present embodiment, a subtraction type decrement counter may be used in other embodiments.

Further, in the present embodiment, the 16-bit random number is generated by four 4-bit counters, but in other embodiments, not limited to this, two 8-bit counters are used. Etc. can be changed as appropriate. Furthermore, although 16-bit random numbers are generated in the present embodiment, the number of bits is not limited to 16 in other embodiments and may be changed as appropriate.

(1-4-2-4) Latch signal output circuit The latch signal output circuit is a first latch signal output circuit 60 (IC13) for obtaining a random number associated with winning in the first starting winning opening 22.
And a second latch signal output circuit 65 (IC14) for obtaining a random number associated with winning in the second starting winning opening 24. Each of these is composed of a 74HC74 flip-flop circuit.

The inversion clock from the random number clock inversion circuit 55 is input to the first latch signal output circuit 60 via the first inversion clock input section 61 (2CK). At the same time, the first start prize signal from the first start prize sensor 23 is input through the first start signal input section 62 (2D). The first latch signal output circuit 60 inputs the rising edge of this start signal from the first inversion clock input section 61 when the signal of the start mouth winning (high signal) is input as the first start winning signal. It is delayed so as to be synchronized with the rising edge of the inverted clock and is output to the first count value storage circuit 80 as the first latch signal via the first latch signal output unit 63 (2Q).

Here, the above-mentioned first start-up winning signal is also input to the main control section 30 as will be described later, and is also used in software processing as the timing of random number acquisition. The effective output width of the first start winning signal (that is, the time during which the hit ball blocks the light beam of the detection unit) is guaranteed to exceed 4 msec (the unit for winning detection described later). It is a circuit that can be delayed (synchronized).

The inversion clock from the random number clock inversion circuit 55 is input to the second latch signal output circuit 65 via the second inversion clock input section 66 (1CK). At the same time, the second start prize signal from the second start prize sensor 25 is inputted through the second start signal input section 67 (1D). The second latch signal output circuit 65 receives the rising edge of this signal from the second inverted clock input section 66 when the signal of the starting mouth winning (high signal) is input as the second starting winning signal. It is delayed so as to be synchronized with the rising edge of the inverted clock and is output to the second count value storage circuit 85 as the second latch signal via the second latch signal output unit 68 (1Q).

Here, the second start winning signal is also input to the main control unit 30 as will be described later, and is also used in software processing as the timing of random number acquisition. The effective output width of the second start winning signal (that is, the time during which the hit ball blocks the light beam of the detection unit) is guaranteed to exceed 4 msec (a unit for winning detection described later). It is a circuit that can be delayed (synchronized).

(1-4-2-5) Count value storage circuit The count value storage circuit is a first count value storage circuit for temporarily storing random numbers derived from winning in the first starting winning opening 22.
It is divided into 80 and a second count value storage circuit 85 for temporarily storing random numbers derived from winning in the second starting winning opening 24. The first count value storage circuit 80 stores the random number value counted by the clock count circuit 70 based on the first latch signal from the first latch signal output circuit 60, and the first count value from the main control unit 30. The stored random number is output based on the read signal.

The second count value storage circuit 85 stores the random number value counted by the clock count circuit 70 as the second count value.
The random number is stored based on the second latch signal from the latch signal output circuit 65, and the stored random number is output based on the second read signal from the main control section 30.
As shown in FIG. 5, the first count value storage circuit 80 includes a register unit (IC5 and IC6) made up of two 8-bit ICs (74HC273) and a buffer unit made up of two 8-bit ICs (74HC541). It is composed of IC9 and IC10).

Similarly, the second count value storage circuit 85 also has 8
Register unit consisting of 2 bit ICs (74HC273) (IC7
And IC8) and a buffer section (IC11 and IC12) consisting of two 8-bit ICs (74HC541). Among the register units of the first count value storage circuit 80, IC5 is
A four digit count from D1 through D4, and
The 4-digit count from IC2 is input through D5 to D8. That is, D1 to D8 of IC5 function as the first count input unit 81, and IC5 has the first count input unit 81 through them.
The lower 8 digits of the 16-bit binary random number derived from the starting winning opening 22 are input.

In the register section of the first count value storage circuit 80, the 4-digit count from IC3 passes through D1 to D4 and the 4-digit count from IC4 passes through D5 to D in IC6.
Entered through 8. That is, D1 to D8 of IC6 function as the first count input unit 81, and the upper 8 digits of the 16-bit binary random number derived from the first starting winning opening 22 are input to IC6 through them. It

In the register section of the second count value storage circuit 85, in IC7, the 4-digit count from IC1 is passed through D1 to D4, and the 4-digit count from IC2 is from D5 to D4.
Entered through 8. That is, D1 to D8 of IC7 function as the second count input unit 86, and the lower 8 digits of the 16-bit binary random number derived from the second starting winning opening 24 are input to IC7 through them. .

In the register section of the second count value storage circuit 85, the 4-digit count from IC3 passes through D1 to D4 and the 4-digit count from IC4 passes through D5 to D in IC8.
Entered through 8. That is, D1 to D8 of IC8 function as the second count input unit 86, and the upper 8 digits of the 16-bit binary random number derived from the second starting winning opening 24 are input to IC8 through them. It

The first latch signal from the first latch signal output circuit 60 is input from the CLK terminal in the register section (IC5 and IC6) of the first count value storage circuit 80. That is, these CLK terminals function as the first latch signal input section 82. The count input from the clock count circuit 70 at the rising edge when the first latch signal input from the first latch signal input unit 82 becomes a high signal is stored in the register unit as a random number. .

The second latch signal from the second latch signal output circuit 65 is input from the CLK terminal in the register section (IC7 and IC8) of the second count value storage circuit 85. That is, these CLK terminals function as the second latch signal input section 87. The count input from the clock count circuit 70 at the time of the rising edge when the second latch signal input from the second latch signal input unit 87 becomes a high signal is stored in the register unit as a random number. .

From the G1 terminal in the buffer section (IC9 and IC10) of the first count value storage circuit 80, the first read signal (inverted RD1 and inverted RD) from the first read signal output section 44 is inputted.
2) is input. That is, these G1 terminals are
It functions as the read signal input unit 83. The random number stored in the register section at the time of the falling edge at which the first read signal input from the first read signal input section 83 becomes a low signal is output to the CPU data bus via the Y1 to Y8 terminals. It is supposed to be done. That is, these terminals function as the first random number output unit 84.

Among the random numbers output from the first random number output unit 84, those passing through the buffer unit of the IC9 are input to the CPU 32 via the lower random number reading unit 39 of the input circuit unit 35, and 16 digits Will be treated as the lower 8 digits of the random number. Further, among the random numbers output from the first random number output unit 84, those that pass through the buffer unit of the IC 10 are transferred to the CPU through the upper random number reading unit 38 of the input circuit unit 35.
It will be input to 32 and will be treated as the upper 8 digits of the 16-digit random number.

From the G1 terminal in the buffer section (IC11 and IC12) of the second count value storage circuit 85, the second read signal (inverted RD3 and inverted RD) from the second read signal output section 45 is inputted.
4) is input. That is, these G1 terminals are
It functions as the read signal input unit 88. The random number stored in the register at the time of the falling edge at which the second read signal input from the second read signal input section 88 becomes a low signal is output to the CPU data bus via the Y1 to Y8 terminals. It is supposed to be done. That is, these terminals function as the second random number output unit 89.

Among the random numbers output from the second random number output unit 89, those passing through the buffer unit of the IC 11 are input to the CPU 32 via the lower random number reading unit 39 of the input circuit unit 35, and 16 digits Will be treated as the lower 8 digits of the random number. Further, among the random numbers output from the second random number output unit 89, those passing through the buffer unit of the IC 12 are transferred to the CPU via the upper random number reading unit 38 of the input circuit unit 35.
It will be input to 32 and will be treated as the upper 8 digits of the 16-digit random number.

(1-5) Signal Timing Next, the signal timing in this embodiment will be described with reference to FIG.
This will be described with reference to the timing chart of FIG. The original oscillation generated by the crystal oscillator (OSC1 in FIG. 5) of the random number clock generation circuit 51 is generated in the flip-flop circuit of the random number clock generation circuit 51 and the IC 15 which constitutes the random number clock inversion circuit 55.
Input from CK.

At the time of the rising edge of the original oscillation (CK), for example, at the time of A in the chart, it is actually output from the inverted clock output unit 58 (inverted Q) and fed back from the D terminal. When the signal is a high signal, the same high signal as this signal is output from the random number clock output unit 52 (Q) as a random number clock. At the same time, a low signal obtained by inverting the signal output from the random number clock output unit 52 (Q) is output from the inverted clock output unit 58 (inverted Q) as an inverted clock. The inverted clock is also fed back to the D terminal at the same time and output, and is output as the next random number clock.

On the other hand, at the time of the rising edge of the original oscillation (CK), for example, at the time of B in the chart, it is actually output from the inverted clock output unit 58 (inverted Q) and fed back from the D terminal. When the existing signal is a low signal, the same low signal as this signal is output from the random number clock output unit 52 (Q) as a random number clock. At the same time, a high signal obtained by inverting the signal output from the random number clock output unit 52 (Q) is output from the inverted clock output unit 58 (inverted Q) as an inverted clock. The inverted clock is also fed back to the D terminal at the same time and output, and is output as the next random number clock.

In the clock count circuit 70 (IC1 to IC4), the random number clock is input from the random number clock input section 71 (CK). This random number clock has the same high signal and low signal periods as those of the random number clock output unit 52 (Q). The rising edge of the random number clock causes the clock count circuit 70 to increment the count. Here, immediately before and after the rising edge of the random number clock, the count increment is in an unstable state in which it is not yet fixed.

In the first latch signal output circuit 60 (IC13), the inverted clock is input from the first latch signal input section 82 (CK). This inverted clock has the periods of the high signal and the low signal reversed from those of the random clock output unit 52 (Q). Here, the first start signal input unit 62
When the first start signal input from (D) indicates a rising edge, for example, at the time point C in the chart, the second rising edge (time point E in the chart) of the inverted clock causes the first start signal to be input. 1 Latch signal output section 63 (Q)
Outputs the first latch signal. That is, the output of the first latch signal is synchronized with the time of the falling edge when viewed from the random number clock. The fluctuation of the above signal is the same in the second latch signal output circuit 65 (IC14).

That is, the count latched at the time point E in the chart is incremented at the previous rising point (D) of the random number clock, and at the time point E, the increment is fixed. It is in a state of being. That is, the count is incremented at the rising edge of the random number clock, and the count is latched at the falling edge of the random number clock, which is delayed by a half cycle. Therefore, it is possible to always obtain a stable count with a fixed increment as a random number.

Even when the winnings to the first starting winning opening 22 and the second starting winning opening 24 occur simultaneously or at extremely short intervals, random numbers derived from the same count are latched separately. It has become. (1-6) Acquisition and Utilization of Random Numbers Next, the procedure of acquisition and utilization of random numbers in an actual game will be described with reference to the flowcharts of FIGS. 7 to 10.

When the power of the ball game machine 10 is turned on, necessary parameters are initialized and the game process is executed according to the main routine shown in FIG. First, R1
The normal game processing subroutine shown in is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine, first, at the stage shown in S100 of FIG. 8, the winning of the hit ball to each winning opening 93, the first starting winning opening 22 and the second starting winning opening 24 is checked.

Here, the interrupt cycle of the CPU 32 is set to about 2 msec in this embodiment. And
Only when a low signal is detected in a certain interrupt cycle and a high signal is detected twice in succession with the next interrupt cycle and the next interrupt cycle, it is determined that the winning is valid. Therefore, in this process, the winning signal is at least 4ms
If the detection width of ec is not obtained, it is not determined that the winning is achieved, but in the present embodiment, the respective winning sensors such as the starting winning sensor are arranged so as to guarantee at least this detection width.

When a prize is won, a process of paying out a predetermined number of prize balls is executed. Then, the process proceeds to the step shown in S110. At the stage shown in S110, it is determined whether or not there is a winning in the first starting winning opening 22. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached 4, the process proceeds to the step shown in S180 of FIG. On the other hand, if the number of reserved balls is less than 4 and it is determined that a prize has been won, the number of reserved balls is incremented by 1, and the process proceeds to step S120.

At the stage shown in S120, the output circuit unit 40
The first read signal output unit 44 outputs the first read signal for the upper 8 bits of the 16-bit random number. Then, the first read signal for the upper 8 bits (inversion of FIG. 5)
RD2) is input from the first read signal input unit 83 (G1 of IC10) of the first count value storage circuit 80. Then, the count value stored in the register unit (IC6) from the IC3 and IC4 of the clock count circuit 70 by the input of the first latch signal based on the winning is the first random number output unit of the buffer unit (IC10).
It is output from 84 (Y1 to Y8). Then, the process proceeds to the step shown in S130.

In the step shown in S130, the count value output in the above step is input from the higher random number reading section 38 of the input circuit section 35 to the main control section 30 via the CPU data bus. Then, the process proceeds to the step shown in S140. In the step shown in S140, the count value input in the above step is stored in the RAM 34 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to the step shown in S150.

At the stage shown in S150, the output circuit unit 40
The first read signal output unit 44 outputs the first read signal for the lower 8 bits of the 16-bit random number. Then, the first read signal for the lower 8 bits (inversion of FIG. 5)
RD1) is input from the first read signal input unit 83 (G1 of IC9) of the first count value storage circuit 80. Then, the count value stored in the register unit (IC5) from the IC1 and IC2 of the clock count circuit 70 by the input of the first latch signal based on the winning is the first random number output unit 8 of the buffer unit (IC9).
It is output from 4 (Y1 to Y8). Then, the process proceeds to the step shown in S160.

In the step shown in S160, the count value output in the above step is input from the lower random number reading section 39 of the input circuit section 35 to the main control section 30 via the CPU data bus. Then, the process proceeds to the step shown in S170. In the step shown in S170, the count value input in the above step is stored in the RAM 34 as the lower 8 bits of the 16-bit random number. And the previous S140
1 together with the upper 8 bits stored at the stage shown in
It will be handled as a 6-bit random number. Then, the process proceeds to the step shown in S180 of FIG.

At the stage shown in S180 of FIG. 9, it is determined whether or not there is a winning in the second starting winning opening 24. Here, when it is determined that there is no winning, and when there are winnings but the number of reserved balls has already reached 4,
Proceed to step S250. On the other hand, if the number of reserved balls is less than 4,
If it is determined that a prize has been won, the number of reserved balls is incremented by 1, and the process proceeds to step S190.

At the stage shown in S190, the output circuit section 40
The second read signal output unit 45 outputs the second read signal for the upper 8 bits of the 16-bit random number. Then, the second read signal for the upper 8 bits (inversion of FIG. 5)
RD4) is input from the second read signal input unit 88 (G1 of IC12) of the second count value storage circuit 85. Then, the count value stored in the register unit (IC8) from the IC3 and IC4 of the clock count circuit 70 by the input of the second latch signal based on the winning is the second random number output unit of the buffer unit (IC12).
It is output from 89 (Y1 to Y8). Then, the process proceeds to the step shown in S200.

In the step shown in S200, the count value output in the above step is input from the higher random number reading section 38 of the input circuit section 35 to the main control section 30 via the CPU data bus. Then, the process proceeds to the step shown in S210. In the step shown in S210, the count value input in the above step is stored in the RAM 34 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to the step shown in S220.

At the stage shown in S220, the output circuit unit 40
The second read signal output unit 45 outputs the second read signal for the lower 8 bits of the 16-bit random number. Then, the second read signal of the lower 8 bits (inversion of FIG. 5)
RD3) is input from the second read signal input unit 88 (G1 of IC11) of the second count value storage circuit 85. Then, the count value stored in the register unit (IC7) from IC1 and IC2 of the clock count circuit 70 by the input of the second latch signal based on the winning is the second random number output unit of the buffer unit (IC11).
It is output from 89 (Y1 to Y8). Then, the process proceeds to the step shown in S230.

In the step shown in S230, the count value output in the above step is input from the lower random number reading section 39 of the input circuit section 35 to the main control section 30 via the CPU data bus. Then, the process proceeds to the step shown in S240. In the step shown in S240, the count value input in the above step is stored in the RAM 34 as the lower 8 bits of the 16-bit random number. And the previous S210
1 together with the upper 8 bits stored at the stage shown in
It will be handled as a 6-bit random number. Then, the process proceeds to the step shown in S250.

At the stage shown in S250, various software random numbers used for determining the special symbol are acquired,
These are also stored in the RAM 34. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 7, next, the symbol variation processing subroutine shown in R2 is executed according to the flowchart shown in FIG.

In the symbol variation processing subroutine, first, at the stage shown in S300 of FIG. 10, it is determined whether or not the number of reserved balls is 1 or more. If the number of reserved balls is 0,
The symbol variation process is not executed, and the process returns to the main routine shown in FIG. On the other hand, if the number of reserved balls is 1 or more, the process proceeds to the step shown in S310. At the stage shown in S310, 1 is subtracted from the number of reserved balls. Then, the process proceeds to the step shown in S320.

At the stage shown in S320, of the 16-bit random numbers (maximum 4) stored in the RAM 34 in the previous normal game processing subroutine, the one stored first is from the relevant storage area in the RAM 34, It is read into the working storage area. Then, this random number is deleted from the storage area. Then, the process proceeds to the step shown in S330. In the step shown in S330, the random number read into the work storage area in the above step is compared with the numerical value for determination,
It is determined whether or not it is won. If not, proceed to S350. On the other hand, in the case of winning, the process proceeds to step S340.

At the stage shown in S340, the special game flag is set. Then, the process proceeds to the step shown in S350. S3
In the stage shown in 50, after the type of special symbol according to the presence or absence of winning is determined using the software random number acquired in the stage shown in S250 of the previous normal game processing subroutine, the special symbol is finally determined. The variable display as shown in is executed by the symbol display device 21 on the game board 20. Then, the process returns to the main routine shown in FIG.

In the main routine shown in FIG. 7, the special game processing subroutine shown in R3 is then executed.
In the special game processing subroutine, if the special game flag is set in S340 of the previous symbol variation processing subroutine, the special game, that is, the jackpot game described above is executed. And after the jackpot game is over,
It is supposed to return to the main routine after clearing the special game flag. On the other hand, if the special game flag is not set, the main routine is immediately returned to.

Then, in the main routine, by repeating the above-mentioned subroutines R1 to R3,
The game is to be continued. (2) Second Embodiment Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Note that FIG. 11 is a block diagram conceptually showing the part related to the generation of random numbers in the present embodiment. 12 and 13 conceptually show the components of this embodiment in a tree diagram. Figure 14
1 is a circuit diagram showing a random number generation device 50 in the present embodiment. FIG. 15 is a timing chart showing signals generated in this embodiment. Then, FIG. 7, FIG. 16, FIG. 17, and FIG. 10 are flowcharts showing the procedure of obtaining and using the random number in the present embodiment.

(2-1) Appearance of Ball Gaming Machine The appearance of the game board 20 of the ball gaming machine 10 according to this embodiment is the same as that described in the first embodiment. (2-2) Outline of Game The outline of the game in the ball game machine 10 is the same as that described in the first embodiment.

(2-3) Game Board In the ball game machine 10 according to the present embodiment, as described above, a prize is generated on the game board 20, which triggers the variable display of the special symbol on the symbol display device 21. Two start winning openings are provided. These are the first starting winning opening 22 and the second starting winning opening 24.
Called. By the winning of any of the starting winning openings, the variable display of the special symbol is similarly performed.

As shown in FIG. 11 and FIG. 12, a first starting prize sensor 23 using an optical sensor is provided in the flow path of the hit ball from the first starting prize hole 22. The first starting winning a prize sensor 23 outputs a first starting winning a prize signal having two states of a high signal and a low signal. This first start winning signal outputs a high signal when the hit ball is not detected (that is, when the detection light beam is not blocked), but while the hit ball is passing (that is, It outputs a low signal only when the detection beam is blocked. In addition,
In another embodiment different from the present embodiment, a magnetic or mechanical sensor may be used as the first starting prize sensor 23.

In the flow path of the hit ball from the second starting winning opening 24,
A second start winning sensor 25 (see FIG. 12) using an optical sensor is provided. This second start winning sensor 25,
A second start winning signal which takes two states of a high signal and a low signal is output. The second start winning signal outputs a high signal when a hit ball is not detected, but outputs a low signal only while the hit ball is passing. In addition, in another embodiment different from this embodiment, a magnetic or mechanical sensor may be used as the second start winning sensor 25.

The special winning opening 26 provided on the game board 20 is a winning opening that is opened and closed by the operation of the solenoid 27 when a special symbol of a predetermined type is displayed as a result of the variable display on the symbol display device 21. . (2-4) Game Control Device As shown in FIGS. 11 and 12, the game control device 15 includes a main control unit 30 that executes control of the ball game machine 10 according to a control program, and the main control unit 30.
And a random number generation device 50 for generating a random number regardless of the control.

(2-4-1) Main control section (2-4-1-1) Reference clock generation circuit, CPU, R
The OM / RAM main control unit 30 includes a reference clock generation circuit 31.
Is provided. The reference clock generation circuit 31 is a circuit that generates a reference clock that serves as an operation reference of the CPU 32 that is the center of control, and generates a pulse at a predetermined interval using a crystal oscillator, a crystal oscillator, or the like. In this embodiment, the reference clock generation circuit 31 is 4.096M.
A pulse of Hz is generated and this pulse itself is used as a reference clock. In another embodiment, a reference clock may be obtained by appropriately dividing this pulse.

The control program to be executed by the CPU 32 and the data required in the control process are stored in the ROM 33. The numerical values of the parameters generated and changed during the control process are temporarily stored in the RAM 34. (2-4-1-2) Input circuit unit Since the input circuit unit 35 receives the input information from the outside of the game control device 15 and the random number generated by the random number generation device 50 provided in the game control device 15. I for the buffer
It is composed of C and the like.

Specifically, the input circuit section 35 receives the input signals from the first start prize winning sensor 23 and the first sensor input section 36 and the second start prize sensor 25. The second sensor input unit 37, the upper random number reading unit 38 into which the upper 8 bits of the random number generated by the random number generator 50 are input, and the lower random number reading unit 39 into which the lower 8 bits are input.
Is provided.

The first sensor input section 36 and the second sensor input section 37 are respectively provided with a capacitor for removing chattering of the winning signal and an inverting circuit for logically inverting. Specifically, as shown in FIG. 14, SW1 as the first start winning sensor 23 is electrically connected to CN1.
The signal input via this CN1 is divided into appropriate voltage values by R1, R2 and C1, chattering is removed, and then input to the 1A terminal of the IC14. And
Input from the 1Y pin of IC14 to the A1 pin of IC15, and finally Y1
Input from the terminal to the first sensor input unit 36. Similarly, the signals from the second start winning sensor 25 (SW2) are CN2 to R3,
Via R4 and C2, the 2A and 2Y terminals of IC14 and
It is input to the second sensor input unit 37 via the A2 terminal and the Y2 terminal of the IC15. Therefore, the signals passing through these input sections are input as a high signal when winning and a low signal when not winning. The input buffer IC15 is designed to output the data input to the An terminal from the Yn terminal when the inverted R5 signal is input from the control unit 100 having the CPU 32, the ROM 33, and the RAM 34.

(2-4-1-3) Output Circuit Section The output circuit section 40 is based on signals such as control signals to electric parts outside the game control apparatus 15 and the random number generating apparatus 50 provided in the game control apparatus 15. It outputs a signal for reading the generated random numbers, and is configured by an IC such as a buffer. Specifically, the output circuit section 40 includes the symbol display device.
21, a sub-control signal output unit 42 for outputting a signal to a sub-control device (not shown) that controls each part based on a control signal from the game control device 15, such as a prize ball control device (not shown), for opening and closing the special winning opening 26 Solenoid drive signal output unit 43 for outputting a drive signal for driving the solenoid 27, game control device
When 15 determines that the first start winning port 22 has won, the first latch trigger signal output unit 46 that outputs the first latch trigger signal that triggers the latching of the random number value corresponding to this winning, the game control device When 15 determines that there is a prize in the second start winning port 24, a second latch trigger signal output unit 47 that outputs a second latch trigger signal that triggers the latching of the random number value corresponding to this prize, the game control device Fifteen is the first
When it is determined that there is a winning in the starting winning port 22, the first reading signal output unit 44 and the game control device 15 that output the first reading signal that triggers the reading of the random number value corresponding to this winning,
A second read signal output unit 45 is provided that outputs a second read signal that triggers the reading of the random number value corresponding to the winning when it is determined that the second start winning opening 24 has won.

In the other embodiment, the first read signal and the second read signal are directly output as the address signal generated by the address decoding circuit without passing through the output circuit section 40. Good. (2-4-2) Random Number Generator Next, the functional blocks of the random number generator will be described with reference to FIGS. 11 and 13.

The random number generator generates a count value used as a random number. Specifically, the random number clock generation circuit 51, the random number clock inversion circuit 55, the first latch signal output circuit 60, the second latch. The signal output circuit 65, the clock count circuit 70, the first count value storage circuit 80, and the second count value storage circuit 85. In addition, in the present invention, the random number is not only a value randomly generated in a mathematical sense, but even if the generation is regular, the timing of its acquisition is random, so that it substantially functions as a random number. It also means possible values.

(2-4-2-1) Random Number Clock Generating Circuit The random number clock generating circuit 51 is for generating a clock for random numbers, and is provided with a random number clock output section 52 for outputting the generated random number clock. There is. Specifically, a crystal oscillator (OCS) that generates a 14.9105 MHz clock (hereinafter referred to as “original oscillation”) that is asynchronous with the reference clock described above.
1) and 74HC74 (IC18) that is connected to the output terminal of this crystal oscillator and functions as a flip-flop circuit that divides the original oscillation by 1/2 and outputs it as a random number clock to the clock count circuit 70 (from IC1 to IC4) ). That is, in the IC 18 of FIG. 14, the random number clock output unit 52 is a random number clock obtained by dividing the original oscillation by 1/2.
The functional part that outputs from the 1Q pin is the random number clock generator
It is supposed to form part of 51.

Here, the flip-flop circuit is interposed so that when the output from the oscillator is directly output, fan-out (malfunction due to capacity over of the output terminal)
This is because there may be a problem of (1) or the waveform may be distorted. With this configuration, it is possible to output a clock having a stable waveform to another device.

Further, in another embodiment, another device such as a gate IC may be interposed in order to avoid the above problem. In other embodiments, like the reference clock generation circuit 31 described above,
Other devices such as a crystal oscillator may be used as the circuit configuration. Furthermore, regarding the oscillation frequency, the above-mentioned 14.810
Although not limited to 5 MHz, using the same frequency as the reference clock generation circuit 31 for the CPU 32 or a frequency that is an integral multiple thereof may generate random numbers in synchronization with the reference clock. , Not preferable.

In the present embodiment, the above flip-flop circuit (IC18) is the random number clock inverting circuit described below.
It also has 55 functions. In this way, by sharing the circuit with a part of the random number clock generation circuit 51 and the random number clock inversion circuit 55, the number of devices can be reduced. (2-4-2-2) Random Number Clock Inversion Circuit The random number clock inversion circuit 55 (IC18) is composed of 74HC74.

That is, the random number clock inverting circuit 55 is provided by the random number clock generating circuit 51 to the random number clock output section 52.
The random number clock output via (1Q) is inverted, and the inverted clock is used as the inverted clock.
Q) outputs to the first latch signal output circuit 60 (IC16) and the second latch signal output circuit 65 (IC17). That is, in the IC 18 of FIG. 14, a function part that outputs a signal obtained by inverting the signal output from the 1Q terminal as an inversion signal from the inversion 1Q terminal, which is the inversion clock output section 58, constitutes the random number clock inversion circuit 55. Has become.

That is, the rising edge of the random number clock corresponds to the falling edge of the inverted clock, and the falling edge of the random number clock corresponds to the rising edge of the inverted clock (see FIG. 15).
In the present embodiment, the random number clock inverting circuit 55 is configured by using the flip-flop circuit, but in other embodiments, it may be configured by using an IC such as a NOT gate instead. good.

(2-4-2-3) Clock Count Circuit The clock count circuit 70 has a random number clock input section 71 for inputting a random number clock and a count output section 72 for outputting the counted value. Specifically, FIG.
As shown in, the 4-bit increment counter
This is a circuit that is composed of individual (IC1 to IC4) cascade-connected circuits, adds at the rising edge of the random number clock generated by the random number clock generation circuit 51, and outputs the addition result. Each increment counter has 74
Composed of HC161.

The random number clock from the random number clock generation circuit 51 is input to the clock count circuit 70 via the random number clock input section 71 (each CK terminal). By inputting the random number clock, first, in IC1, a count is added from "0000" to "1111". Then, "111
When it changes from "1" to "0000" again, the carry signal of IC1
Output from the CO pin to the ENT pin of IC2. In IC2, the count is added only when the carry signal and the random number clock are simultaneously input.

Similarly, the carry addition signal from IC2 is required for the count addition of IC3, and the carry signal from IC3 is required for the count addition of IC4. In this way, the clock count circuit 70
A 16-bit binary number is to be generated. That is, of the 16-digit binary number, IC1 is the lowest 4 digits, I
C2 is in charge of the upper 4 digits, IC3 is in charge of the upper 4 digits, and IC4 is in charge of the upper 4 digits.

The count added by the clock count circuit 70 is the count output unit 72 (each QA, Q
It is output to the first count value storage circuit 80 and the second count value storage circuit 85 via the B, QC and QD terminals. In this embodiment, the count is incremented by the random number clock generated by the random number clock generation circuit 51, but in another embodiment, the random number clock generated by the random number clock generation circuit 51 is changed to a latch signal described later. It may be configured to output to the output circuit and increment using the inverted clock. Further, although the count is incremented by the rising edge of the random number clock in the present embodiment, it may be incremented by the falling edge of the random number clock in other embodiments. Furthermore, although an addition type increment counter is used in the present embodiment, a subtraction type decrement counter may be used in other embodiments.

Further, in this embodiment, a 16-bit random number is generated by four 4-bit counters, but in other embodiments, not limited to this, two 8-bit counters are used. Etc. can be changed as appropriate. Furthermore, although 16-bit random numbers are generated in the present embodiment, the number of bits is not limited to 16 in other embodiments and may be changed as appropriate.

(2-4-2-4) Latch Signal Output Circuit The latch signal output circuit is the first latch signal output circuit 60 (IC16) for obtaining a random number associated with winning in the first starting winning opening 22.
And a second latch signal output circuit 65 (IC17) relating to acquisition of a random number associated with winning in the second starting winning opening 24. Each of these is composed of a 74HC74 flip-flop circuit.

The inversion clock from the random number clock inversion circuit 55 is input to the first latch signal output circuit 60 via the first inversion clock input section 61 (1CK). At the same time, after the first latch trigger signal from the first latch trigger signal output section 46 is input to the IC 13 from the 1D terminal and further output from the 1Q terminal, the first latch trigger signal input section 64
Input via (1D).

Then, when the signal for winning the starting opening (high signal) is input as the first latch trigger signal, the first latch signal output circuit 60 changes the rising edge of this signal to the first inverted clock input section 61. The first latched signal output section 63 (1
It outputs to the 1st count value storage circuit 80 via Q).

Here, the first start winning signal is also input to the main control unit 30 as will be described later, and is also used in software processing as the timing of random number acquisition. Second latch signal output circuit
The inverted clock from the random number clock inversion circuit 55 is input to the 65 via the second inverted clock input unit 66 (2CK). Along with this, the second latch trigger signal output unit 47
The second latch trigger signal from is input to the IC 13 from the 2D terminal, further output from the 2Q terminal, and then input via the second latch trigger signal input section 69 (2D).

The second latch signal output circuit 65 receives the rising edge of this signal when the start opening winning signal (high signal) is input as the second latch trigger signal, and outputs the rising edge of this signal to the second inverted clock input section 66. It is delayed so as to be synchronized with the rising edge of the inverted clock input from the second latch signal output unit 68 (1
And output to the second count value storage circuit 85 via Q).

Here, the second start winning signal is also input to the main control unit 30 as described later, and is also used in software processing as the timing of random number acquisition. (2-4-2-5) Count value storage circuit The count value storage circuit is a first count value storage circuit that temporarily stores random numbers derived from winning in the first start winning port 22.
It is divided into 80 and a second count value storage circuit 85 for temporarily storing random numbers derived from winning in the second starting winning opening 24.

The first count value storage circuit 80 stores the random number value counted by the clock count circuit 70 as the first count value.
The random number is stored based on the first latch signal from the latch signal output circuit 60, and the stored random number is output based on the first read signal from the main control section 30.
The second count value storage circuit 85 includes the clock count circuit 70.
Storing the random number value counted by the second latch signal output circuit 65 based on the second latch signal, and outputting the stored random number based on the second read signal from the main control unit 30. Is.

As shown in FIG. 14, the first count value storage circuit 80 includes a register section (IC5 and IC6) consisting of two 8-bit ICs (74HC273) and an 8-bit IC (74HC54).
1) It consists of two buffer units (IC9 and IC10). Similarly, the second count value storage circuit 85 also includes a register section (IC7 and IC7 and 74HC273) including two ICs (74HC273).
IC8) and a buffer unit (IC11 and IC12) consisting of two 8-bit ICs (74HC541).

In the register section of the first count value storage circuit 80, the 4-digit count from IC1 is passed through D1 to D4 and the 4-digit count from IC2 is passed from D5 to D5 in IC5.
Entered through 8. That is, D1 to D8 of IC5 function as the first count input unit 81, and the lower 8 digits of the 16-bit binary random number derived from the first start winning opening 22 are input to IC5 through these. .

In the register section of the first count value storage circuit 80, the 4-digit count from IC3 passes through D1 to D4, and the 4-digit count from IC4 passes through D5 to D in IC6.
Entered through 8. That is, D1 to D8 of IC6 function as the first count input unit 81, and the upper 8 digits of the 16-bit binary random number derived from the first starting winning opening 22 are input to IC6 through them. It

In the register section of the second count value storage circuit 85, the 4-digit count from IC1 is passed through D1 to D4 and the 4-digit count from IC2 is passed from D5 to D in IC7.
Entered through 8. That is, D1 to D8 of IC7 function as the second count input unit 86, and the lower 8 digits of the 16-bit binary random number derived from the second starting winning opening 24 are input to IC7 through them. .

In the register section of the second count value storage circuit 85, the 4-digit count from IC3 passes through D1 to D4, and the 4-digit count from IC4 passes through D5 to D in IC8.
Entered through 8. That is, D1 to D8 of IC8 function as the second count input unit 86, and the upper 8 digits of the 16-bit binary random number derived from the second starting winning opening 24 are input to IC8 through them. It

The first latch signal from the first latch signal output circuit 60 is input from the CLOCK terminal in the register section (IC5 and IC6) of the first count value storage circuit 80. That is, these CLOCK terminals are connected to the first latch signal input section 8
Functioning as 2. The count input from the clock count circuit 70 at the rising edge when the first latch signal input from the first latch signal input unit 82 becomes a high signal is stored in the register unit as a random number. .

The second latch signal from the second latch signal output circuit 65 is input from the CLOCK terminal in the register section (IC7 and IC8) of the second count value storage circuit 85. That is, these CLOCK terminals are connected to the second latch signal input section 8
Functioning as 7. The count input from the clock count circuit 70 at the time of the rising edge when the second latch signal input from the second latch signal input unit 87 becomes a high signal is stored in the register unit as a random number. .

From the G1 terminal in the buffer section (IC9 and IC10) of the first count value storage circuit 80, the first read signal (inverted RD1 and inverted RD) from the first read signal output section 44 is input.
2) is input. That is, these G1 terminals are
It functions as the read signal input unit 83. The random number stored in the register section at the time of the falling edge at which the first read signal input from the first read signal input section 83 becomes a low signal is output to the CPU data bus via the Y1 to Y8 terminals. It is supposed to be done. That is, these terminals function as the first random number output unit 84.

Of the random numbers output from the first random number output unit 84, those passing through the buffer unit of the IC9 are input to the CPU 32 via the lower random number reading unit 39 of the input circuit unit 35, and 16 digits Will be treated as the lower 8 digits of the random number. Further, among the random numbers output from the first random number output unit 84, those that pass through the buffer unit of the IC 10 are transferred to the CPU through the upper random number reading unit 38 of the input circuit unit 35.
It will be input to 32 and will be treated as the upper 8 digits of the 16-digit random number.

From the G1 terminal in the buffer section (IC11 and IC12) of the second count value storage circuit 85, the second read signal (inverted RD3 and inverted RD) from the second read signal output section 45 is inputted.
4) is input. That is, these G1 terminals are
It functions as the read signal input unit 88. The random number stored in the register at the time of the falling edge at which the second read signal input from the second read signal input section 88 becomes a low signal is output to the CPU data bus via the Y1 to Y8 terminals. It is supposed to be done. That is, these terminals function as the second random number output unit 89.

Among the random numbers output from the second random number output unit 89, those passing through the buffer unit of the IC 11 are input to the CPU 32 via the lower random number reading unit 39 of the input circuit unit 35, and 16 digits Will be treated as the lower 8 digits of the random number. Further, among the random numbers output from the second random number output unit 89, those passing through the buffer unit of the IC 12 are transferred to the CPU via the upper random number reading unit 38 of the input circuit unit 35.
It will be input to 32 and will be treated as the upper 8 digits of the 16-digit random number.

(2-5) Signal Timing Next, the signal timing in this embodiment is shown in FIG.
This will be described with reference to the timing chart of FIG. The original oscillation generated by the crystal oscillator (OSC1 in FIG. 14) of the random number clock generation circuit 51 is an IC that constitutes the flip-flop circuit of the random number clock generation circuit 51 and the random number clock inversion circuit 55.
Input from 18 1CK.

At the time of the rising edge of this original oscillation (1CK), for example, at the time of A in the chart, it is actually output from the inverted clock output unit 58 (inverted 1Q) and fed back from the 1D terminal. When the signal is a high signal, the same high signal as this signal is output from the random number clock output unit 52 (1Q) as a random number clock. At the same time, a low signal obtained by inverting the signal output from the random number clock output unit 52 (1Q) is output from the inverted clock output unit 58 (inverted 1Q) as an inverted clock. Further, this inversion clock is fed back to the 1D terminal at the same time and output, and is output as the next random number clock.

On the other hand, at the time of the rising edge of the original oscillation (1CK), for example, at the time of B in the chart, it is actually output from the inverted clock output unit 58 (inverted 1Q) and fed back from the 1D terminal. When the existing signal is a low signal, the same low signal as this signal is output as a random number clock from the random number clock output unit 52 (1Q).
At the same time, a high signal obtained by inverting the signal output from the random number clock output unit 52 (1Q) is output from the inverted clock output unit 58 (inverted 1Q) as an inverted clock. Also,
This inverted clock is fed back to the 1D terminal at the same time and output, and is output as the next random number clock.

In the clock count circuit 70 (IC1 to IC4), the random number clock is input from the random number clock input section 71 (CK). This random number clock has the same high signal and low signal periods as those of the random number clock output unit 52 (1Q). The rising edge of the random number clock causes the clock count circuit 70 to increment the count. Here, immediately before and after the rising edge of the random number clock, the count increment is in an unstable state in which it is not yet fixed.

In the first latch signal output circuit 60 (IC16), the inverted clock is input from the first latch signal input section 82 (1CK). This inversion clock has the periods of the high signal and the low signal inverted from those of the random number clock output unit 52 (1Q). Here, if the first latch trigger signal input from the first latch trigger signal input unit 64 (1D) indicates a rising edge, for example, at time C in the chart, the next rising edge of the inverted clock (E in the chart). The input of the first latch signal is output from the first latch signal output unit 63 (1Q).
That is, the output of the first latch signal is synchronized with the time of the falling edge when viewed from the random number clock. The fluctuation of the above signal is caused by the second latch signal output circuit 65.
The same applies to (IC17).

That is, the count latched at the time point E in the chart is incremented at the previous rising point (D) of the random number clock, and at the time point E, the increment is fixed. It is in a state of being. That is, the count is incremented at the rising edge of the random number clock, and the count is latched at the falling edge of the random number clock, which is delayed by a half cycle. Therefore, it is possible to always obtain a stable count with a fixed increment as a random number.

Even when the winnings to the first starting winning opening 22 and the second starting winning opening 24 occur at the same time or at extremely short intervals, random numbers derived from the same count are latched separately. It has become. (2-6) Acquisition and Utilization of Random Numbers Next, the procedure of acquisition and utilization of random numbers in an actual game will be described with reference to the flowcharts of FIGS. 7, 16 and 17 and FIG.

When the power of the ball game machine 10 is turned on, necessary parameters are initialized, and then the game process is executed according to the main routine shown in FIG. First, R1
The normal game processing subroutine shown in FIG.
It is executed according to the flowchart shown in. In the normal game processing subroutine, first, at the stage shown in S400 of FIG. 16, the winning of the hit ball to each winning opening 93, the first starting winning opening 22 and the second starting winning opening 24 is checked.

Here, the interrupt cycle of the CPU 32 is set to about 2 msec in this embodiment. And
Only when a low signal is detected in a certain interrupt cycle and a high signal is detected twice in succession with the next interrupt cycle and the next interrupt cycle, it is determined that the winning is valid. Therefore, in this process, the winning signal is at least 4ms
If the detection width of ec is not obtained, it is not determined that the winning is achieved, but in the present embodiment, the respective winning sensors such as the starting winning sensor are arranged so as to guarantee at least this detection width.

When a prize is won, a process of paying out a predetermined number of prize balls is executed. Then, the process proceeds to the step shown in S410. At the stage shown in S410, it is determined whether or not there is a winning in the first starting winning opening 22. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached 4, the process proceeds to the step shown in S480 of FIG. On the other hand, if the number of reserved balls is less than 4, and
If it is determined that there is a prize, the number of reserved balls is incremented by 1, and the process proceeds to the step shown in S415.

At the stage shown in S415, the output circuit unit 40
The first latch trigger signal output section 46 outputs the first latch trigger signal to the first latch signal output circuit 60. Then, the process proceeds to the step shown in S420. The time required to shift from the step shown in S415 to the step shown in S420 requires time for synchronization, that is, about one cycle of the random number clock generation circuit 51, so that reliable random number acquisition is possible. Is secured. Furthermore, when the processing time cannot be secured, the weight processing for that amount may be inserted between these steps.

At the stage shown in S420, the output circuit section 40
The first read signal output unit 44 outputs the first read signal for the upper 8 bits of the 16-bit random number. Then, the first read signal (inverted RD2 in FIG. 14) for the upper 8 bits is input from the first read signal input unit 83 (G1 of IC10) of the first count value storage circuit 80. Then, the count value stored in the register unit (IC6) from the IC3 and IC4 of the clock count circuit 70 by the input of the first latch signal based on the winning is the first random number output unit 84 (from Y1 of the buffer unit (IC10). Output up to Y8). Then, it proceeds to the step shown in S430.

At the stage shown in S430, the count value outputted at the above stage is inputted from the higher random number reading unit 38 of the input circuit unit 35 to the main control unit 30 via the CPU data bus. Then, the process proceeds to the step shown in S440. In the step shown in S440, the count value input in the above step is stored in the RAM 34 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to the step shown in S450.

At the stage shown in S450, the output circuit section 40
The first read signal output unit 44 outputs the first read signal for the lower 8 bits of the 16-bit random number. Then, the lower 8 bits of the first read signal (inverted RD1 in FIG. 14) is input from the first read signal input unit 83 (G1 of IC9) of the first count value storage circuit 80. Then, the count value stored in the register unit (IC5) from the IC1 and IC2 of the clock counting circuit 70 by the input of the first latch signal based on the winning is changed to the first random number output unit 84 (from Y1 of the buffer unit (IC9). Output up to Y8). Then, the process proceeds to the step shown in S460.

At the stage shown in S460, the count value outputted at the above stage is inputted from the lower random number reading unit 39 of the input circuit unit 35 to the main control unit 30 via the CPU data bus. Then, the process proceeds to the step shown in S470. In the step shown in S470, the count value input in the above step is stored in the RAM 34 as the lower 8 bits of the 16-bit random number. And the previous S440
1 together with the upper 8 bits stored at the stage shown in
It will be handled as a 6-bit random number. Then, the process proceeds to the step shown in S475.

At the stage shown in S475, the output circuit section 40
The output of the first latch trigger signal from the first latch trigger signal output section 46 is completed. Note that this step may be performed at any time after the step shown in S415. However, when the above-described wait processing is executed between the step shown in S415 and the step shown in S420, it may be performed after that. Then, the process proceeds to the step shown in S480 of FIG.

At the stage shown in S480 of FIG. 17, the second
It is determined whether or not there is a winning in the starting winning opening 24. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached 4, the process proceeds to step S550. On the other hand, if it is determined that the number of reserved balls is less than 4 and that a prize has been won, the number of reserved balls is incremented by 1, and the process proceeds to step S485.

At the stage shown in S485, the output circuit section 40
The second latch trigger signal output section 47 outputs the second latch trigger signal to the second latch signal output circuit 65. Then, the process proceeds to the step shown in S490. It should be noted that the time required to shift from the step shown in S485 to the step shown in S490 requires time for synchronization, that is, about one cycle of the random number clock generation circuit 51, so that reliable random number acquisition is possible. Is secured. Furthermore, when the processing time cannot be secured, the weight processing for that amount may be inserted between these steps.

At the stage shown in S490, the output circuit section 40
The second read signal output unit 45 outputs the second read signal for the upper 8 bits of the 16-bit random number. Then, the second read signal (inverted RD4 in FIG. 14) for the upper 8 bits is input from the second read signal input unit 88 (G1 of IC12) of the second count value storage circuit 85. Then, the count value stored in the register unit (IC8) from the IC3 and IC4 of the clock count circuit 70 by the input of the second latch signal based on the winning is the second random number output unit 89 (from Y1 of the buffer unit (IC12). Output up to Y8). Then, the process proceeds to the step shown in S500.

In the step shown in S500, the count value output in the above step is input from the higher random number reading section 38 of the input circuit section 35 to the main control section 30 via the CPU data bus. Then, the process proceeds to the step shown in S510. In the step shown in S510, the count value input in the above step is stored in the RAM 34 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to the step shown in S520.

At the stage shown in S520, the output circuit section 40
The second read signal output unit 45 outputs the second read signal for the lower 8 bits of the 16-bit random number. Then, the second read signal (inverted RD3 in FIG. 14) for the lower 8 bits is input from the second read signal input unit 88 (G1 of IC11) of the second count value storage circuit 85. Then, the count value stored in the register unit (IC7) from the IC1 and IC2 of the clock count circuit 70 by the input of the second latch signal based on the winning is changed to the second random number output unit 89 (from Y1 of the buffer unit (IC11). Output up to Y8). Then, the process proceeds to the step shown in S530.

At the stage shown in S530, the count value outputted at the above stage is inputted from the lower random number reading unit 39 of the input circuit unit 35 to the main control unit 30 via the CPU data bus. Then, the process proceeds to the step shown in S540. In the step shown in S540, the count value input in the above step is stored in the RAM 34 as the lower 8 bits of the 16-bit random number. And the previous S210
1 together with the upper 8 bits stored at the stage shown in
It will be handled as a 6-bit random number. Then, the process proceeds to the step shown in S545.

At the stage shown in S545, the output circuit section 40
The output of the first latch trigger signal from the second latch trigger signal output section 47 is completed. Note that this step may be performed at any time after the step shown in S485. However, when the aforementioned wait processing is executed between the step shown in S485 and the step shown in S490, it may be performed after that. Then, the process proceeds to the step shown in S550.

At the step shown in S550, various software random numbers used for determining the special symbol are acquired,
These are also stored in the RAM 34. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 7, next, the symbol variation processing subroutine shown in R2 is executed according to the flowchart shown in FIG. 10, but this is performed in the same manner as in the first embodiment.

In the main routine shown in FIG. 7, the special game processing subroutine shown in R3 is then executed, which is also carried out in the same manner as in the first embodiment.
Then, in the main routine, the game is to be continued by repeating the above-mentioned subroutines from R1 to R3.

[0155]

Since the present invention is configured as described above, it has the following effects. That is, in the present invention, by updating the counter not by software but by hardware, a random number generating means that is high-speed and asynchronous with the operation of the CPU is used, thereby reducing the load of software, which is a problem of the prior art. In addition, it is possible to use a random number with a large range and to realize the determination of the winning that is less likely to cause fraud from the outside.

[Brief description of drawings]

FIG. 1 is a front view showing a game board of a ball-and-ball game machine according to first and second embodiments of the present invention.

FIG. 2 is a block diagram conceptually showing a part related to random number generation in the first embodiment of the invention.

FIG. 3 conceptually shows a tree diagram of the constituent elements of the first embodiment of the present invention.

FIG. 4 conceptually shows a tree diagram of the constituent elements of the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a random number generator according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing signals generated in the first embodiment of the present invention.

FIG. 7 shows a main routine in a procedure for obtaining and using a random number according to the first and second embodiments of the present invention.

FIG. 8 shows a part of a normal game processing subroutine in a procedure for obtaining and using a random number according to the first embodiment of the present invention.

FIG. 9 shows a part of a normal game processing subroutine in a procedure of obtaining and using a random number according to the first embodiment of the present invention.

FIG. 10 shows a symbol variation processing subroutine in a procedure of obtaining and using a random number in the first and second embodiments of the present invention.

FIG. 11 is a block diagram conceptually showing a part related to random number generation in the second embodiment of the invention.

FIG. 12 conceptually shows a tree diagram of the components of the second embodiment of the present invention.

FIG. 13 is a tree diagram conceptually showing the components of the second embodiment of the present invention.

FIG. 14 is a circuit diagram showing a random number generator according to a second embodiment of the present invention.

FIG. 15 is a timing chart showing signals generated in the second embodiment of the present invention.

FIG. 16 shows a part of a normal game processing subroutine in a procedure of obtaining and using a random number according to the first embodiment of the present invention.

FIG. 17 shows a part of a normal game processing subroutine in the procedure of obtaining and using a random number according to the first embodiment of the present invention.

[Explanation of symbols]

10 ball game machine 15 Game control device 20 game board 21 pattern display device 22 1st starting prize hole 23 1st starting prize sensor 24 2nd starting prize hole 25 2nd starting prize sensor 26 Winner 27 Solenoid 30 Main control section 31 Reference clock generator 32 CPU 33 ROM 34 RAM 35 Input circuit section 36 1st sensor input section 37 2nd sensor input section 38 Upper random number reading unit 39 Lower random number reading unit 40 Output circuit block 42 Sub control signal output section 43 Solenoid drive signal output section 44 1st read signal output section 45 2nd read signal output section 46 1st latch trigger signal output section 47 Second latch trigger signal output section 50 random number generator 51 Random clock generator 52 Random clock output section 55 Random number clock inversion circuit 58 Inverted clock output section 60 First latch signal output circuit 61 First inverted clock input section 62 1st start signal input section 63 First latch signal output section 64 1st latch trigger signal input section 65 Second latch signal output circuit 66 Second inverted clock input section 67 Second start signal input section 68 Second latch signal output section 69 Second latch trigger signal input section 70 clock count circuit 71 Random number clock input section 72 Count output section 80 1st count value memory circuit 81 1st count input section 82 1st latch signal input section 83 1st read signal input section 84 1st random number output section 85 Second count value storage circuit 86 Second count input section 87 Second latch signal input section 88 Second read signal input section 89 Second random number output section 90 Special pattern hold lamp 91 Enlargement device 92 Attacker unit 93 Winner 94 Normal symbol display 95 Normal symbol hold lamp 96 Gate 97 Out Exit 98 windmill 100 control

Claims (2)

[Claims] 1. A starting winning opening for generating a starting winning signal by hitting a hit ball, a random number clock generating circuit for generating a random number clock at a predetermined frequency, and an inverted clock obtained by inverting the random number clock from the random number clock generating circuit. A random number clock inverting circuit for generating a clock, a clock count circuit that counts the number of clocks based on an input of a rising edge or a falling edge of one of the random number clock and the inverted clock, and the start winning signal. A latch signal output circuit that outputs a latch signal by synchronizing with a rising edge or a falling edge of the other clock of the random number clock and the inverted clock, and counted by the clock count circuit based on the latch signal Cow to memorize count value A count value storage circuit, the stored value of the count value storage circuit is referred to on the basis of a predetermined condition, and the winning determination relating to the winning at the starting winning opening is determined based on the stored value. Ball game machine. 2. A start winning opening for generating a start winning signal by hitting a hit ball, a random number clock generating circuit for generating a random number clock at a predetermined frequency, and an inverted clock obtained by inverting the random number clock from the random number clock generating circuit. A random number clock inverting circuit for generating a clock, a clock count circuit for counting the number of clocks based on an input of a rising edge or a falling edge of one of the random number clock and the inverted clock, and a start winning signal A latch signal output circuit that synchronizes a signal generated based on the input with an input of a rising edge or a falling edge of the other clock of the random number clock and the inverted clock and outputs the latch signal, and the latch signal output circuit based on the latch signal. Counted by the clock count circuit A count value storage circuit that stores a count value is provided, the stored value of the count value storage circuit is referred to based on a predetermined condition, and the winning determination regarding the winning at the starting winning port is performed based on the stored value. Ball game machine characterized by that.