JP4711666B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  Currently, in game machines, a random number used to determine whether or not to make a “big hit” (a big hit determination random number) is generated by the CPU executing a predetermined application program. However, such a random number generation method has a problem that the processing load on the CPU at the time of generation increases.

To solve this problem, a game machine that generates a big hit determination random number using a random number generation circuit, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. However, a gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 1).
JP-A-7-124296 (page 3-4, FIG. 1).

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). A gaming machine that stores random numbers is also disclosed (for example, see Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2).

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  Further, in the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gentle, the rising edge of the inverted clock pulse also becomes gentle. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reliably and stably obtaining a random value.

In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, a special symbol) that variably displays a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified based on the fact that the previous variable display in 4 and the end of the jackpot gaming state have been established. A display device 41 and a variable display device 4), and a gaming machine (for example, a pachinko gaming machine 1) that makes a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of the identification information becomes the specific display result. And a game control microcomputer (for example, a game control microcomputer mounted on the main board 11) including a game control CPU (for example, CPU 103) for controlling the progress of the game. And a random number generation circuit (for example, random number generation circuit 17 or 27) for generating a random number (for example, random R), and the random number generation circuit has a reference clock signal (for example, a reference clock signal) having a predetermined period. Reference clock signal output means (for example, reference clock signal output circuit 171) for outputting S0) and clock signal generation means for generating a plurality of signals having the same period and different phases based on the reference clock signal (for example, clock signal generation) Circuit 172), and the clock signal generation means includes a clock terminal (for example, an input terminal CK of the clock signal generation circuit 172) to which the reference clock signal is input from the reference clock signal output means, and a first signal Input terminal (for example, input terminal D of the clock signal generation circuit 172), and the first Timing of changing the signal change state for each predetermined period of the reference clock signal input from the clock terminal (for example, timing T10, T11, T12,..., Etc. when the reference clock signal S0 rises from low level to high level) The first output terminal (for example, the positive phase output terminal Q of the clock signal generation circuit 172) that outputs a signal synchronized with the first output terminal and a signal that has the same period and a different phase from the signal output from the first output terminal A second output terminal (for example, a reverse phase output terminal Q (bar) of the clock signal generation circuit 172), and the clock signal generation means connects the second output terminal and the input terminal. By doing so, the first clock signal (for example, the counting clock signal S1) output from the first output terminal and the second output terminal A second clock signal (for example, a latch count signal S2) that is output and has the same period and a different phase from the first clock signal, and the random number generation circuit is generated by the clock signal generation means. At the first timing when the first clock signal changes in a predetermined manner (for example, timings T10, T12, T14,... When the counting clock signal S1 rises from the low level to the high level, etc.) Numerical data updating means (for example, counter 173) for updating value C) and second timing (for example, latch clock signal S2) at which the second clock signal generated by the clock signal generating means changes in the predetermined manner. , T11, T13, T15,... Rising from low level to high level In response to the latch signal output means (for example, latch signal output circuit 174) for outputting the latch signal and the latch signal input from the latch signal output means, the numerical data updated by the numerical data update means is disturbed. Random number storage means (for example, a random value storage circuit 175) for storing as a numerical value, and captures at least one of the reference clock signal, the first clock signal, and the second clock signal. When the clock signal divided by the frequency dividing means (for example, the frequency dividing circuit 181) and the clock signal divided by the frequency dividing means have not been input for a predetermined period or more, an abnormality has occurred in the operation state of the random number generating circuit. Abnormal signal output means for outputting an abnormal signal (for example, a reset signal) to the game control microcomputer as a signal indicating the effect For example, the random number generation circuit monitoring means (for example, the monitoring circuit 18) provided with a reset IC 182 with a watchdog, and the game control microcomputer, based on the fact that the variable display execution condition is satisfied, Random value reading means for reading the random value from the storage means (for example, the part where the CPU 103 executes the process of step S203) and the random value reading means read based on the fact that the variable display start condition is satisfied. By determining whether or not the random value matches a predetermined determination value (for example, “2001 to 2184”, “2001 to 3104”, etc.), it is determined whether or not the display result in the variable display is the specific display result. Display result determining means for determining (for example, a portion where the CPU 103 executes the process of step 216) and the abnormal signal output means An abnormal signal determining means for determining whether or not an abnormal signal has been output from the CPU (for example, the part where the CPU 103 executes the process of step S101) and the abnormal signal determining means have determined that an abnormal signal has been output. (For example, when the CPU 103 determines Yes in the process of step S101), an abnormal process execution unit that executes a predetermined abnormal process (for example, a part in which the CPU 103 executes the process of step S102 or S103) and the random value reading unit Before the random number value is read from the random value storage means, an output control signal (for example, output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the random value After the reading means obtains the random value from the random value storage means, the output of the output control signal to the random value storage means is stopped and the random value storage means And read control means for controlling the read disabled state (e.g. partial CPU103 is executing the processing in steps S202 and S205), seen including, it said random number storage means, an output control signal from said read control means is inputted And a read priority unit (for example, an AND circuit 701) that prohibits updating of the stored random number value even when a latch signal is output from the latch signal output unit .

In order to achieve the above object, a gaming machine according to claim 2 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, a winning to a normal variable winning ball device 6) is established. 4, a variable display device (for example, a special symbol) that variably displays a plurality of types of identification information (for example, special symbols and decorative symbols) that can be identified based on the fact that the previous variable display in 4 and the end of the jackpot gaming state have been established. A display device 41 and a variable display device 4), and a gaming machine (for example, a pachinko gaming machine 1) that makes a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of the identification information becomes the specific display result. And a game control microcomputer (for example, a game control microcomputer mounted on the main board 11) including a game control CPU (for example, CPU 103) for controlling the progress of the game. And a random number generation circuit (for example, random number generation circuit 37) that generates a random number (for example, random R), and the random number generation circuit has a reference clock signal (for example, reference clock signal S0) having a predetermined period. A reference clock signal output means (for example, a reference clock signal output circuit 171) that outputs a plurality of timings (for example, the reference clock signal output from the reference clock signal output means changes in a predetermined manner for each predetermined period) Numerical values for updating numerical data at a first timing (for example, timings T10, T12, T14,...) Among timings T10, T11, T12,..., When the reference clock signal S0 rises from a low level to a high level. A numerical value for outputting a data update signal (for example, count clock signal S5) Update data output means (for example, selector 178) and numerical data update means (for example, count value C) for updating numerical data (for example, count value C) in response to the numerical data update signal input from the numerical data update signal output means. A latch that outputs a latch signal (for example, a latch signal SL) at a second timing (for example, timings T11, T13, T15,...) Different from the first timing among the plurality of timings. Signal output means (for example, latch signal output circuit 174) and random number value storage means for storing the numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means (For example, a random value storage circuit 175), and the reference clock signal and the numerical data update Frequency dividing means (for example, frequency dividing circuit 181) that takes in and divides at least one clock signal of the new signal and the latch signal, and the clock signal divided by the frequency dividing means is input for a predetermined period or more. If not, an abnormal signal output means (for example, a reset IC 182 with a watchdog) outputs an abnormal signal (for example, a reset signal) to the game control microcomputer as a signal indicating that an abnormality has occurred in the operation state of the random number generation circuit. ), And the game control microcomputer receives the random number value from the random value storage means based on the fact that the variable display execution condition is satisfied. Random number reading means for reading (for example, a portion where the CPU 103 executes the process of step S203) and the variable display Based on the establishment of the start condition, it is determined whether or not the random value read by the random number reading means matches a predetermined determination value (for example, “2001 to 2184”, “2001 to 3104”, etc.). Thus, a display result determining means (for example, a portion where the CPU 103 executes the process of step 216) for determining whether or not the display result in the variable display is a specific display result, and an abnormal signal is output from the abnormal signal output means. When an abnormal signal determining means (for example, a part where the CPU 103 executes the process of step S101) for determining whether or not an abnormality signal has been output and when the abnormal signal determining means determines that an abnormal signal has been output (for example, the CPU 103) When it is determined Yes in the process of step S101), an abnormal process execution means (for example, a CPU) that executes a predetermined abnormal process 03 and partial) executing the processing in steps S102 and S103, before the random number value reading means reads a random number from the random number value storing means, the random numeric storage unit to the output control signal (e.g., the output control signal SC) To output the output control signal to the random value storage means after the random value read means obtains the random value from the random value storage means. I saw including a read control means for controlling the reading disabled state of the random numeric storage unit (e.g., the portion CPU103 is executing the processing in steps S202 and S205), the and, the random number value storing means, from said read control means Read priority means (for example, AND circuit 701) that prohibits updating of a stored random number value even when a latch signal is output from the latch signal output means when an output control signal is input Etc.) .

In order to achieve the above object, the gaming machine according to claim 3 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is satisfied. 4, a variable display device (for example, variable display device 4) that variably displays a plurality of types of identification information (for example, decorative symbols) that can be identified based on the establishment of the previous variable display and end of jackpot gaming state in FIG. A gaming machine (for example, a pachinko gaming machine 1) that has a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result, A game control microcomputer (eg, a game control microcomputer 100 mounted on the main board 11) including a game control CPU (eg, CPU 103) to be controlled; A random number generation circuit (for example, random number generation circuit 47) that generates a number (for example, random R), and the random number generation circuit outputs a reference clock signal (for example, reference clock signal S0) having a predetermined period. An output means (for example, a reference clock signal output circuit 171) and a reference clock signal output from the reference clock signal output means are delayed by a period different from an integral multiple of the predetermined period to obtain a delayed clock signal (for example, a delay). A clock signal delay means (for example, a delay circuit 179) for generating and outputting the clock signal S7), and a reference clock signal output from the reference clock signal output means is changed in a predetermined manner every predetermined period. (For example, timing T10 when the reference clock signal S0 rises from low level to high level) T11, T12,...) And the second timing at which the delayed clock signal output from the clock signal delay means changes in a predetermined manner every predetermined cycle (for example, the delayed clock signal S7 changes from low level to high level). Numerical data updating means for updating numerical data (for example, count value C) at any one timing (for example, timing T10, T11, T12,...). (For example, a counter 173) and a timing different from the timing at which the numerical data updating unit updates the numerical data among the first timing and the second timing (for example, timings T20, T21, T22,...) Latch signal for outputting a latch signal (for example, latch signal SL) An output means (for example, a latch signal output circuit 174) and a random value storage means for storing the numerical data updated by the numerical data update means as a random value in response to a latch signal inputted from the latch signal output means ( For example, a random number storage circuit 175), and the monitoring circuit takes in and divides at least one clock signal of the reference clock signal and the delayed clock signal (for example, a frequency dividing circuit 181). ) And an abnormal signal (for example, a reset signal) as a signal indicating that an abnormality has occurred in the operating state of the random number generation circuit when the clock signal divided by the frequency dividing means has not been input for a predetermined period or longer. An abnormal signal output means (for example, a reset IC 182 with a watchdog) for outputting to the game control microcomputer; The random number generation circuit monitoring means (for example, the monitoring circuit 18) and the game control microcomputer read the random value from the random value storage means based on the fact that the variable display execution condition is satisfied. Based on the fact that the variable display start condition is satisfied (for example, the part in which the CPU 103 executes the process of step S203), the random number value read by the random value reading means is a predetermined determination value (for example, “2001”). Display result determining means for determining whether or not the display result in the variable display is set as the specific display result (for example, the CPU 103 performs step). 216 for executing the process 216) and an abnormal signal judgment for judging whether or not an abnormal signal is output from the abnormal signal output means. Means (for example, the part where the CPU 103 executes the process of step S101) and when it is determined that the abnormal signal is output by the abnormal signal determination means (for example, when the CPU 103 determines Yes in the process of step S101) ), An abnormal process execution means (for example, a part where the CPU 103 executes the processing of step S102 or S103) for executing a predetermined abnormal process , and before the random value reading means reads the random value from the random value storage means, After outputting an output control signal (for example, output control signal SC) to the random value storage means to control the random value storage means to be readable, the random value read means obtains a random value from the random value storage means Read control means (for example, CPU) for stopping output of the output control signal to the random value storage means and controlling the random value storage means to an unreadable state 103 and portion) executing the processing in steps S202 and S205, only contains the random number storage means, when the output control signal from said read control means is input, a latch signal from the latch signal output means It includes a read priority unit (for example, an AND circuit 701) that prohibits updating of the stored random number value even if it is output .

  5. The gaming machine according to claim 4, wherein a start signal (for example, a start winning signal SS) is output to the game control microcomputer and the random number generation circuit based on the fact that the variable display execution condition is satisfied. The random number generation circuit further includes a start signal output means (for example, a start port switch 72), and measures the time when the start signal is input from the start signal output means, and the measured time is a predetermined time (for example, 3 ms). ), Timer means (for example, timer circuit 176) for outputting the start signal to the latch signal output means, and the latch signal output circuit latches the start signal input from the start signal output means. Output as a signal.

  6. The gaming machine according to claim 5, wherein the gaming control microcomputer executes a timer interruption process in response to an interruption request signal inputted periodically (for example, every 2 ms). Including an execution means (for example, a portion where the CPU 103 executes a game control interrupt process), and the random value reading means is configured to execute a timer interrupt process a predetermined number of times (for example, twice) by the timer interrupt process execution means. The random number value is read from the random value storage means based on the fact that the start signal is continuously input from the start signal output means while the timer means executes the timer interrupt processing. Setting means (for example, the timer circuit 176 executes two times of the timer interrupt processing). When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means. Output to.

7. The gaming machine according to claim 6 , wherein the random value storage means is incapable of receiving an output control signal output from the read control means when a latch signal is input from the latch signal output means. Output control signal reception control means (for example, an AND circuit 703).

In the gaming machine according to claim 7 , an effect device (for example, variable display device 4, speakers 8 </ b> L and 8 </ b> R, game effect lamp 9, etc.) for executing a predetermined effect, and effect control for controlling the effect operation by the effect device. And the abnormal process execution means determines that the abnormal signal is output by the abnormal signal determination means (for example, the CPU 103 performs the process of step S101). Based on the above, the effect control command (for example, error effect start command) for instructing the execution of the effect to notify that the abnormality has occurred in the random number generation circuit is transmitted to the effect control microcomputer. Including production control command transmission means (for example, a portion where the CPU 103 executes the process of step S103), The effect control microcomputer includes effect control command receiving means for receiving the effect control command transmitted by the effect control command transmitting means (for example, a portion where the CPU 200 executes command reception interrupt processing), and receiving the effect control command. Based on the fact that the means has received the effect control command (for example, that the CPU 200 has determined Yes in the process of step S311), the effect device is controlled to notify that an abnormality has occurred in the random number generation circuit. Effect control means (for example, a portion where the CPU 200 executes the process of step S313).

In the gaming machine according to claim 8, when the abnormal process execution unit determines that an abnormal signal is output by the abnormal signal determination unit (for example, the CPU 103 determines Yes in the process of step S113). ), A variable display start restricting means for restricting the start of variable display of identification information by the variable display device (for example, the CPU 103 determines Yes in the process of step S114, and restricts the execution of the processes of steps S120 to S123). Part).

In the gaming machine according to claim 9 , a payout device (for example, a payout device 50) for paying out game media, a payout control microcomputer (for example, a payout control board 15) for controlling a payout operation by the payout device, The game control microcomputer further includes a payout control command (for example, a prize ball) for instructing a game medium to be paid out when a predetermined payout condition (for example, winning to the ordinary variable winning ball apparatus 6) is established. A payout control command transmission means (for example, a portion where the CPU 103 executes the prize ball processing in step S20) for sending a payout control command to the payout control microcomputer. The payout control microcomputer includes the payout control command. Based on the payout device, payout control means (for example, payout control board 1) for paying out the game medium from the payout device Includes a portion for controlling the rotation operation of the payout motor based on the award ball number designation command and paying out the game ball from the payout device 50), and the payout control command transmitting means outputs an abnormal signal by the abnormal signal determining means. Even when it is determined that the payment has been made, when the predetermined payout condition is satisfied, the payout control command is transmitted to the payout control microcomputer, and the payout control means is based on the payout control command. The game medium is paid out from the payout device.

The inventions according to claims 1 to 9 of the present application have the following effects.

According to the configuration of the first aspect, the random number generation circuit generates the first clock signal and the second clock signal having the same period and different phases, and the first clock signal changes in a predetermined manner. The numerical data is updated at the first timing, and the latch signal is output at the second timing when the second clock signal changes in a predetermined manner. Thus, since the random number generation circuit can reliably change the update timing of the numerical data and the latch timing of the numerical data, the game control microcomputer can reliably and stably acquire the random value. It can be carried out.
When an abnormality occurs in the operation state of the random number generation circuit, an abnormality signal is output from the abnormality signal output means to the game control microcomputer. The gaming control microcomputer executes a predetermined abnormality process based on the determination that the abnormal signal has been output by the abnormal signal determination means, thereby causing an abnormality in the random number generation circuit. Thus, it is possible to prevent a situation in which the player is disadvantaged.
Furthermore, the game control microcomputer can make the random value storage means readable only when the display result determining means reads the random value, so that the random value can be acquired reliably and stably. .
And since the random number generation circuit can prevent the random number value stored in the random value storage means from being updated when the random value read means reads the random value from the random value storage means, The random value can be acquired reliably and stably.

According to the configuration of claim 2, the random number generation circuit updates the numerical data at a first timing among a plurality of timings at which the reference clock signal changes in a predetermined manner every predetermined cycle, A latch signal is output at a second timing different from the first timing. Thus, since the random number generation circuit can reliably change the update timing of the numerical data and the latch timing of the numerical data, the game control microcomputer can reliably and stably acquire the random value. It can be carried out.
When an abnormality occurs in the operation state of the random number generation circuit, an abnormality signal is output from the abnormality signal output means to the game control microcomputer. The gaming control microcomputer executes a predetermined abnormality process based on the determination that the abnormal signal has been output by the abnormal signal determination means, thereby causing an abnormality in the random number generation circuit. Thus, it is possible to prevent a situation in which the player is disadvantaged.
Furthermore, the game control microcomputer can make the random value storage means readable only when the display result determining means reads the random value, so that the random value can be acquired reliably and stably. .
And since the random number generation circuit can prevent the random number value stored in the random value storage means from being updated when the random value read means reads the random value from the random value storage means, The random value can be acquired reliably and stably.

According to the configuration of the third aspect, the random number generation circuit includes the first timing at which the reference clock signal changes in a predetermined manner every predetermined cycle and the delayed clock signal input from the delay unit at every predetermined cycle. The numerical data is updated at any one timing of the second timing that changes in a predetermined manner, and the numerical data is updated by the numerical data updating means between the first timing and the second timing. The latch signal is output at a timing different from the previous timing. Thus, since the random number generation circuit can reliably change the update timing of the numerical data and the latch timing of the numerical data, the game control microcomputer can reliably and stably acquire the random value. It can be carried out.
When an abnormality occurs in the operation state of the random number generation circuit, an abnormality signal is output from the abnormality signal output means to the game control microcomputer. The gaming control microcomputer executes a predetermined abnormality process based on the determination that the abnormal signal has been output by the abnormal signal determination means, thereby causing an abnormality in the random number generation circuit. Thus, it is possible to prevent a situation in which the player is disadvantaged.
Furthermore, the game control microcomputer can make the random value storage means readable only when the display result determining means reads the random value, so that the random value can be acquired reliably and stably. .
And since the random number generation circuit can prevent the random number value stored in the random value storage means from being updated when the random value read means reads the random value from the random value storage means, The random value can be acquired reliably and stably.

  According to the configuration of the fourth aspect, instead of directly outputting the start signal input from the start signal output means to the latch signal output means, the input time of the start signal is measured by the timer means, When the set time is reached, a start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting the latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration described in claim 5, since the timer means is set as a predetermined time that is shorter than the execution time of the predetermined number of timer interrupt processes by the timer interrupt process execution means, the random value It is possible to prevent the random number value read by the reading means from the random value storage means from being the same as the random value read last time.

According to the configuration of the sixth aspect , the random number generation circuit reads the random value from the random value storage means by the random value reading means when the random value stored in the random value storage means is updated. Therefore, the random number value can be updated reliably and stably.

According to the configuration of claim 7 , the game control microcomputer transmits an effect control command to the effect control microcomputer based on the determination that the abnormal signal is output by the abnormal signal determination means. Then, based on the reception of the effect control command, the effect control microcomputer causes the effect device to execute an effect informing that an abnormality has occurred in the random number generation circuit. In this way, by notifying the player that the random number generation circuit has an abnormality and recognizing the player, it is possible to prevent the player from continuing the game in a state where the abnormality has occurred in the random number generation circuit. Can do.

According to the configuration of claim 8 , the game control microcomputer regulates the start of variable display of the identification information by the variable display device when it is determined by the abnormal signal determination means that the abnormal signal has been output. Therefore, it is possible to prevent the game from proceeding in a state where an abnormality has occurred in the random number generation circuit.

According to the configuration of the ninth aspect , even when the gaming control microcomputer determines that the abnormal signal has been output by the abnormal signal determination means, if the predetermined payout condition is satisfied, Since the game medium is paid out from the apparatus, it is possible to prevent the player from being disadvantaged due to the occurrence of an abnormality in the random number generation circuit.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 is provided at approximately the center position of the game area so as to display a decorative symbol as variable identification information. A special symbol display 41 is provided on the upper side of the variable display device 4, and an ordinary variable winning ball device (start winning port) 6 is disposed on the lower side. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. In addition, a normal symbol display 42 is provided on the right side of the special variable winning ball apparatus 7.

  The special symbol display 41 is composed of, for example, a 7-segment LED or the like. For example, in a special symbol game in which a game ball is awarded to the ordinary variable winning ball device 6, it is composed of numbers, characters, symbols, etc. The special symbol variable display is started, and when a certain time has elapsed, the fixed symbol that is the variable symbol variable display result is stopped (displayed).

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays a symbol as identification information by a plurality of variable display units. For example, the special symbol display 41 starts variable display of the special symbol. When this is done, variable display of three display symbols (decorative symbols) composed of numbers, letters, symbols, etc. is started, and the fixed symbol is stopped and displayed as a variable symbol display result of the special symbol on the special symbol indicator 41. Sometimes, the display symbols are determined in the order of left, right, and middle. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number. Further, the starting memory number may be specified by a display (start winning memory display) provided separately from the variable display device 4. For example, it is only necessary that the start winning memory indicator is constituted by an LED, a lamp, and the like, and that the display format of the LED and the lamp is controlled on the main board 11 side so that the start winning memory number can be specified.

  The normal symbol display 42 is configured to include a light emitting diode (LED) and the like, and is turned on, blinked, colored, etc., in a normal diagram game in which a game ball starts through a passing gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 2). (Community). The winning ball that has entered the normal variable winning ball device 6 is guided to the back of the game board 2 and detected by the start port switch 72 (FIG. 2). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding memory 110 (FIG. 3) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that controls opening / closing of a winning area by a solenoid 22 (FIG. 2). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit (for example, a count switch). In response to the detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2) which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  Further, on the back of the pachinko gaming machine 1, main boards such as a power supply board 10, a main board 11, an effect control board 12, and a payout control board 15 are arranged at appropriate positions.

  FIG. 2 is a block diagram showing a system configuration example centering on the main board 11, the effect control board 12, and the payout control board 15. FIG. 2 also shows the power supply board 10, the random number generation circuit 17, the monitoring circuit 18, the payout device 50, the system clock generation circuit 60, the start port switch 72, and the like.

  The payout device 50 pays out a winning ball or a game ball based on a ball lending request, and includes a payout stepping motor (payout motor) (not shown) serving as a drive source. The rotation operation of the payout motor is controlled by a drive signal sent from the payout control board 15.

  The system clock generation circuit 60 is for supplying a predetermined system clock signal SSC to each circuit in the pachinko gaming machine 1.

  The start opening switch 72 generates a start winning signal (high level signal) SS on the main board 11 and a random number generation circuit based on detecting the winning of a game ball to the normal variable winning ball apparatus 6 which is a starting winning opening. 17 is output.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 includes a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. Further, the main board 11 is connected with wiring to the effect control board 12 and the payout control board 15 and wiring from the start port switch 72. The main board 11 is also connected to a wiring from a winning opening switch 70 for detecting a winning of a game ball to other winning openings such as a special variable winning ball apparatus 7 which is a large winning opening. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The game control microcomputer 100 is, for example, a one-chip microcomputer, and is controlled according to a ROM (Read Only Memory) 101 for storing a game control program, a RAM (Random Access Memory) 102 used as a work memory, and the program. A CPU (Central Processing Unit) 103 and an I / O (Input / Output) port 104 are included. The game control microcomputer 100 has a function of generating random numbers used in special game, a function of outputting and transmitting control commands as examples of command information to the effect control board 12 and the payout control board 15, respectively. It has a function of receiving a control command sent from the control board 15, a function of performing display control of the special symbol display 41, a function of performing on / off control of the normal symbol display 42, and the like.

  The control command transmitted from the main board 11 to the effect control board 12 is an effect control command transmitted as an electrical signal using, for example, signal lines of the effect control signals CD0 to CD7. The effect control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). As this effect control command, for example, an error effect start command for instructing the start of an error effect is prepared in advance.

  The control command transmitted from the main board 11 to the payout control board is, for example, a payout control command transmitted as an electrical signal using the signal lines of the payout control signals CD0 to CD7. The payout control command has a 2-byte configuration, like the effect control command, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). As the payout control command, for example, a prize ball number designation command for designating the number of prize balls is prepared in advance. The EXT data of the prize ball number designation command indicates the number of prize balls.

  As shown in FIG. 3, the game control microcomputer 100 includes a special figure holding memory 110, a switch timer memory 111, a jackpot determination table memory 112, and a flag memory 113.

  In the special figure holding memory 110, a condition (execution condition) for executing a variable symbol display (special symbol game) for a game ball winning the normal variable winning ball device 6 is established. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 110 includes four entries, and each entry has a holding number and a random number value R acquired from the random number generation circuit 17 in accordance with the winning order in the order of winning to the ordinary variable winning ball apparatus 6. Stored in association. Each time the special symbol variable display by the special symbol display 41 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information is established, and the top information is displayed. Based on the variable display is executed. At this time, the second and lower registration information is moved up by one place. Further, when a game ball newly wins the normal variable winning ball apparatus 6 during the variable display of the special symbol, the random value R read from the random value storage circuit 175 (FIG. 8) based on the winning is obtained. It is registered in the highest empty entry.

  The switch timer memory 111 adds or depends on whether the start winning signal SS input from the start opening switch 72 or the detection signal input from the other winning opening switch 70 is on or off. A plurality of switch timers to be cleared are stored.

  The jackpot determination table memory 112 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 112 stores a normal big hit determination table 120 shown in FIG. 4A and a probabilistic change big hit determination table 121 shown in FIG. 4B.

  The normal big hit determination table 120 shown in FIG. 4 (A) and the probability variation big hit determination table 121 shown in FIG. 4 (B) use the special symbol display result of the special symbol display 41 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 120 and 121, a random value R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 121, more random number values R are associated with the display result of “big hit” than in the normal big hit determination table 120. That is, by determining the display result of the special figure game using the probability change jackpot determination table 121, it is possible to achieve a probability improvement state in which the probability of becoming a big hit gaming state is higher than in the normal gaming state.

  In this embodiment, in the normal jackpot determination table 120 shown in FIG. 4A, among the jackpot determination random numbers R “0 to 65335” generated from the random number generation circuit 17, “2001 to 2184” is set to “big hit”. Is associated with the display result. On the other hand, in the probability variation jackpot determination table 121 shown in FIG. 4B, “2001-3104” among the jackpot determination random numbers R “0 to 65335” generated from the random number generation circuit 17 are displayed as “big hit”. Is associated.

  In the flag memory 113 shown in FIG. 3, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 113 is provided with a special symbol process flag, a normal symbol process flag, a big hit flag, an input state flag, an error flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected / executed in the special symbol process (described later) (FIG. 16). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 42 in a predetermined order.

  The big hit flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished. The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The error flag is set to an ON state based on the input of a reset signal from a reset IC with watchdog (integrated circuits) 182 (FIG. 8). The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The switch circuit 107 shown in FIG. 2 takes in the start winning signal SS from the start opening switch 72 and the detection signals from other winning opening switches 70 and transmits them to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The effect control board 12 controls the display operation in the variable display device 4, the sound output operation from the speakers 8L and 8R, the lighting operation and the extinguishing operation of the game effect lamp 9. For example, the effect control board 12 performs control to execute various effect displays by causing the variable display device 4 to perform image switching display based on the effect control command transmitted from the main board 11. The effect control board 12 is connected to wiring for transmitting control signals to the audio output circuit 13 and the lamp driver circuit 14.

  FIG. 5 is a block diagram illustrating a hardware configuration example of the effect control board 12. The effect control board 12 includes a CPU 200, a ROM 201, a RAM 202, a VDP (Video Display Processor) 203, a CGROM (Character Generator ROM) 204, a VRAM (Video RAM) 205, an audio data output circuit 206, and lamp data. And an output circuit 207.

  When receiving the effect control command transmitted from the main board 11, the CPU 200 reads control data for effect control from the ROM 201 while using a predetermined area of the RAM 202 as a work area. Based on the read control data, the CPU 200 performs display control of the variable display device 4 by sending a drawing command to the VDP 203 or outputs audio data from the audio data output circuit 206 to the audio output circuit 13. Then, sound output control is performed, and lamp lighting control is performed by causing the lamp data output circuit 207 to output lamp data to the lamp driver circuit 14.

  The VDP 203 has, for example, a display control function and a high-speed drawing function for performing image display by the variable display device 4, and executes image processing according to a drawing command from the CPU 200. Further, it has a two-dimensional address space independent of the CPU 200, and the VRAM 205 is mapped there. For example, the VDP 203 develops image data read from the CGROM 204 in a predetermined area of the VRAM 205. Then, a video signal including an R (red), G (green), B (blue) signal, a synchronization signal, and the like is output to the variable display device 4. As an example, each of the R, G, and B signals is represented by 8 bits, and the variable display device 4 synthesizes each of R, G, and B in 256 gradations according to an instruction from the VDP 203, and synthesizes them to obtain about 16.7 million colors. Color display can be performed. Note that the number of bits of the R, G, and B signals may be other than 8 bits, and the number of bits of the R, G, and B signals may be different from each other.

  The CGROM 204 is for storing various image data used for displaying an image on the variable display device 4. For example, the CGROM 204 stores character image data frequently used among images displayed on the variable display device 4, specifically, a person, an animal, a character, a figure, a symbol, or the like in advance. . In this embodiment, the CGROM 204 stores image data composed of character strings for notifying that an abnormality has occurred in the random number generation circuit 17.

  A VRAM 205 is a frame buffer memory in which image data is expanded by the VDP 203.

  The audio data output circuit 206 receives the control command from the CPU 200 and outputs audio data to the audio output circuit 13. The audio output circuit 13 generates an audio signal by performing digital / analog conversion on the audio data received from the audio data output circuit 206, for example, and supplies the audio signal to the speakers 8L and 8R to output the audio.

  The lamp data output circuit 207 receives a control command from the CPU 200 and outputs lamp data to the lamp driver circuit 14. In the lamp driver circuit 14, for example, a lamp driving signal corresponding to the lamp data received from the lamp data output circuit 207 is generated and supplied to the game effect lamp 9 to switch on / off the lamp.

  The effect control board 12 includes a reception command buffer memory 210 and a flag memory 211 as shown in FIG.

  The reception command buffer memory 210 is provided with a plurality of reception command buffers for storing effect control commands received from the main board 11. FIG. 7 is a diagram illustrating a configuration example of the reception command buffer memory 210. In the example shown in FIG. 7, twelve received command buffers are provided, and the received command buffer for storing the received command is designated by the command reception number counter. The command reception number counter takes values from “0” to “11”. Each reception command buffer is composed of, for example, 1 byte, and by using a plurality of reception command buffers as ring buffers, it is possible to store six 2-byte effect control commands.

  The flag memory 211 shown in FIG. 6 is for setting a plurality of types of flags that are set or cleared in accordance with the effect control command received from the main board 11. In the flag memory 211, for example, an effect control process flag and an error effect flag are provided. The effect control process flag indicates which process should be selected and executed in the effect control process (described later) (FIG. 20). The error effect flag is set to an on state when an error effect start command transmitted from the main board 11 is received.

  The payout control board 15 performs payout control for game balls, prize balls, and the like. For example, the payout control board 15 pays out a game ball from the payout device 50 by sending a drive signal to the payout motor based on a prize ball number designation command transmitted from the main board 11 and controlling its rotation operation. Let

  The information terminal board 16 is for outputting various game-related information to the outside.

  FIG. 8 is a block diagram showing the configuration of the random number generation circuit 17 and the monitoring circuit 18.

  As shown in FIG. 8, the random number generation circuit 17 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, a random value storage circuit 175, a timer circuit 176, , Is composed of. The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The reference clock signal output circuit 171 generates a reference clock signal S0 having a predetermined frequency (for example, 20 MHz). The reference clock signal output circuit 171 outputs the generated reference clock signal S0 to the clock signal generation circuit 172 and the timer circuit 176.

  The clock signal generation circuit 172 is configured by a D-type lip flop circuit or the like. The clock terminal CK of the clock signal generation circuit 172 is connected to the output terminal of the reference clock signal output circuit 171, and the positive phase output terminal Q is connected to the counter 173. Further, the anti-phase output terminal (inverted output terminal) Q (bar) of the clock signal generation circuit 172 is connected to the input terminal D and the clock terminal CK of the latch signal output circuit 174.

  The clock signal generation circuit 172 outputs a signal fed back from the reverse phase output terminal Q (bar) to the input terminal D at a timing when the reference clock signal S0 input from the reference clock signal output circuit 171 to the clock terminal CK rises. In synchronization, the signal is output from the positive phase output terminal Q, and the negative phase signal (inverted signal) of the signal output from the positive phase output terminal Q is output from the negative phase output terminal Q (bar). In this way, the clock signal generation circuit 172 generates two clock signals (counting clock signal S1 and latching clock signal S2) having the same cycle and different phases, and outputs the counting clock signal S1 in the positive phase. From the terminal Q, the latch clock signal S2 and the negative phase output signal S2 can be outputted from the negative phase output terminal Q (bar).

  Specifically, a count clock signal S1 having a frequency of 10 MHz is output from the positive phase output terminal Q, and a negative phase signal of the count clock signal S1, that is, a count is output from the negative phase output terminal Q (bar). Similarly to the clock signal S1, a latch clock signal S2 having a frequency of 10 MHz and having a phase different from that of the counting clock signal S1 by π (= 180 °) is output.

  The counter 173 circulates the output count value C from a predetermined initial value to a predetermined final value in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Update to

  In this embodiment, the counter 173 is a 16-bit binary counter, and counts up the count value C from “0” to “65535” by 1 each time the rising edge of the count clock signal S1 is input. Go. When the count value C is counted up to “65535”, the count value C is returned to “0” and counted up to “65535” again. That is, the count value C is cyclically updated as “0” → “1” →... → “65535” → “0” →... Each time the rising edge of the count clock signal S1 is input to the counter 173. The

  The latch signal output circuit 174 is configured by a D-type lip flop circuit or the like. The input terminal D of the latch signal output circuit 174 is connected to the output terminal of the timer circuit 176, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175.

  The latch signal output circuit 174 generates the latch signal SL by synchronizing the start winning signal SS input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK, and generates the output terminal Q. Output from.

  The random value storage circuit 175 shown in FIG. 8 is a 16-bit register, and stores a random value R that is read in a winning process in step S112 described later. The random value storage circuit 175 latches and stores the count value C input from the counter 173 as the random value R in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174. Thus, every time the start winning signal SS is input to the random number generation circuit 17, the stored random number value R is sequentially updated.

  FIG. 9 is a circuit diagram showing a configuration example of the random value storage circuit 175. As shown in FIG. 9, the random value storage circuit 175 includes two AND circuits 701 and 703, two NOT circuits 702 and 704, 16 Philip flop circuits 710 to 725, and 16 OR circuits. 730-745.

  The input terminal of the AND circuit 701 is connected to the output terminal Q of the latch signal output circuit 174 and the output terminal of the NOT circuit 704, and the output terminals are the input terminal of the NOT circuit 702 and the clock terminal CK0 of the Philip flop circuits 710 to 725. To CK15. The input terminal of the NOT circuit 702 is connected to the output terminal of the AND circuit 701, and the output terminal is connected to one input terminal of the AND circuit 703.

  The input terminal of the AND circuit 703 is connected to the output terminal of the NOT circuit 702 and the I / O port 104 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 704. The input terminal of the NOT circuit 704 is connected to the output terminal of the AND circuit 703, and the output terminal is connected to one input terminal of the AND circuit 701 and one input terminal of each of the OR circuits 730 to 745.

  The input terminals D0 to D15 of the Philip flop circuits 710 to 725 are connected to the output terminal of the counter 173. The clock terminals CK0 to CK15 of the Philip flop circuits 710 to 725 are connected to the output terminal of the AND circuit 701, and the output terminals Q0 to Q15 are connected to the other input terminal of each of the OR circuits 730 to 745.

  The input terminals of the OR circuits 730 to 745 are connected to the output terminal of the NOT circuit 704 and the output terminals of the flip-flop circuits 710 to 725, and the output terminals are connected to the I / O port 104 of the game control microcomputer 100. It is connected.

  FIG. 10 is a diagram for explaining the details of the connection between the output terminals of the OR circuits 730 to 745 and the I / O port 104 of the game control microcomputer 100. In this embodiment, the output terminals of the OR circuits 730 to 745 and the bits of the input port of the jackpot determination random number included in the I / O port 104 are interchanged and connected as shown in FIG. Yes. Thereby, the randomness of the random number input to the game control microcomputer 100 can be enhanced.

  The operation of the random value storage circuit 175 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the gaming control microcomputer 100 (when one input of the AND circuit 703 is low level), the output terminal Q of the latch signal output circuit 174 At the timing when the input latch signal SL rises from the low level to the high level (in the example shown in FIG. 11, timings T1, T2, and T7), the inputs of the AND circuit 701 are both at the high level and are output from the output terminals. The signal SA1 becomes high level. The signal SA1 output from the AND circuit 701 is input to the clock terminals CK0 to CK15 of the Philip flop circuits 710 to 725.

  The Philip flop circuits 710 to 725 respond to the rising edge of the signal SA1 input from the clock terminals CK0 to CK15, and the bit data C0 to C15 of the count value C input from the counter 173 via the input terminals D0 to D15. Are latched and stored as bit data R0 to R15 of the random number value, and the bit data R0 to R15 of the stored random number value R are output from the output terminals Q0 to Q15.

  When the output control signal SC is not input (in the example shown in FIG. 11, in the period up to the timing T3, the period after the timing T6), one of the inputs of the AND circuit 703 is at the low level, so that the output is output from the output terminal. The signal SA2 to be performed becomes a low level. The signal SA2 is inverted in the NOT circuit 704, and a high level signal is input to one input terminal of the OR circuits 730 to 745.

  Thus, since one input of the OR circuits 730 to 745 is at a high level, regardless of whether a signal input to the other input terminal is at a high level or a low level, that is, an input random value Regardless of whether the values of the R bit data R0 to R15 are “0” or “1”, the signals SO0 to SO15 output from the OR circuits 730 to 745 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 175 is always “635535 (= 1111h)”, and the random value R cannot be read from the random value storage circuit 175. That is, when the output control signal SC is not input, the random value storage circuit 175 is in a non-readable (disabled) state.

  When the output control signal SC is input from the game control microcomputer 100 when the latch signal SL input from the latch signal output circuit 174 is at the low level (in the example shown in FIG. 11, from the timing T4 to the timing T6). Since both the inputs of the AND circuit 703 are at a high level, the signal SA2 output from the output terminal thereof is at a high level. The signal SA2 is inverted in the NOT circuit 704, and a low level signal is input to one input terminal of the OR circuits 730 to 745.

  Since one input of the OR circuits 730 to 745 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the value of the bit data R0 to R15 of the random value R input to the other input terminal of the OR circuit 730 to 745 is directly from the output terminal of the OR circuit 730 to 745 (the value of the bit data R0 to R15 is “1”). "1" is output when it is "," and "0" is output when it is "0." As a result, the random value R can be read from the random value storage circuit 175. In other words, when the output control signal SC is input, the random value storage circuit 175 enters a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 174 before the output control signal SC is input from the game control microcomputer 100, one input of the AND circuit 703 becomes low level. After that, even if the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 11, the period from the timing T3 to the timing T4), the signal SA2 output from the output terminal Remains low. The signal SA2 is inverted in the NOT circuit 704, and a high-level signal is input to one input terminal of the OR circuits 730 to 745.

  Since one input of the OR circuits 730 to 745 becomes high level in this way, the output from the OR circuits 730 to 745 is output regardless of whether the signal input to the other input terminal is high level or low level. All of the signals SO0 to SO15 are at a high level, and the random value R cannot be read from the random value storage circuit 175 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 175 becomes incapable of receiving the output control signal SC.

  Further, when the output control signal SC is input from the game control microcomputer 100 before the latch signal SL input from the latch signal output circuit 174 becomes high level, one input of the AND circuit 701 is low level. Therefore, after that, even when the input latch signal SL becomes high level (in the example shown in FIG. 11, timing T5) while the output control signal SC is being input, the output is output from the output terminal. The signal SA1 to be kept remains at a low level. For this reason, the signal SA1 input to the clock terminals CK0 to CK15 of the Philip flop circuits 710 to 725 does not rise from the low level to the high level, and the bit data R0 of the random value R stored in the Philip flop circuits 710 to 725. ˜R15 are not updated even when the latch signal SL input from the latch signal output circuit 174 rises. That is, when the output control signal SC is input, the random value storage circuit 175 becomes incapable of receiving the latch signal SL.

  The timer circuit 176 shown in FIG. 8 measures the time during which the start winning signal SS is input from the start port switch 72, and latches the start winning signal SS when the measured time reaches a predetermined time (for example, 3 ms). The signal is output to the signal output circuit 174.

  In this embodiment, the timer circuit 176 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. The timer circuit 176 counts up or down a predetermined timer value in response to the rising edge of the reference clock signal S0 input from the reference clock signal output circuit 171 while the input is at a high level. . When the timer value counted up or down reaches a value corresponding to 3 ms, the timer circuit 176 determines that the input signal is the start winning signal SS, and latches the start winning signal SS as a latch signal. Output to the output circuit 174.

  FIG. 12 is a timing chart for explaining the operation of the random number generation circuit 17.

  As shown in FIG. 12A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  In response to the rising edge of the reference clock signal S0 input from the clock terminal CK, the clock signal generation circuit 172 responds to the rising clock of the reference clock signal S0 input from the clock terminal CK. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 12B, the positive-phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 12D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 12C, the counter 173 updates the count value C in response to the rising edge of the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 inputs the start winning signal SS shown in FIG. 12E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 12F is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  In this way, the random number generation circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  The monitoring circuit 18 shown in FIG. 8 includes a frequency dividing circuit 181 and a reset IC 182 with a watch dog. The monitoring circuit 18 is for monitoring the operation state of the random number generation circuit 17, more specifically the operation state of the reference clock signal output circuit 171 and the like.

  The frequency dividing circuit 181 takes in and divides the frequency of any one of the reference clock signal S0, the counting clock signal S1, and the latching clock signal S2 used when the random number generating circuit generates a random number. The divided clock signal is output to a reset IC with a watchdog. In this embodiment, the frequency dividing circuit 182 divides the count clock signal S1 output from the positive phase output terminal Q of the clock signal generation circuit 172, generates the frequency divided clock signal S3, and resets with a watchdog. Output to the IC 182.

  The reset IC 182 with a watchdog is a reset IC that incorporates a watchdog circuit (not shown). In response to the rising edge of the system clock signal SSC supplied from the system clock generation circuit 60, the watch IC with reset IC 182 counts up or down the timer value of the watchdog circuit. The reset IC 182 with watchdog initializes the timer value of the watchdog circuit in response to the rising edge of the divided clock signal S3 input from the frequency dividing circuit 181.

  Here, the time that can be measured by the watchdog circuit, that is, the time until the timer value of the watchdog circuit counts up or down from the initial value to the final value is longer than the period of the divided clock signal S3. Is set to For this reason, when the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17 are operating normally, the rising edge of the divided clock signal S3 is periodically input to the watchdog circuit. Therefore, the timer value never reaches the final value.

  On the other hand, when an abnormality occurs in the reference clock signal output circuit 171 and the clock signal generation circuit 172, and the reference clock signal S0, the count clock signal S1, and the latch clock signal S2 are not generated, the watchdog circuit Since the rising edge of the divided clock signal S3 is not input, the timer value reaches the final value.

  As described above, when the watchdog circuit times out without the frequency-divided clock signal being input from the frequency-dividing circuit 181, the reset IC 182 with watchdog has an abnormality in the reference clock signal output circuit 171 and the clock signal generation circuit 172. As a thing, a predetermined reset signal SR is output to the main board 11. In the main board 11, based on the detection of the reset signal SR by the CPU 103, predetermined error processing (FIG. 15) is executed. By executing such error processing, the pachinko gaming machine 1 can prevent a situation in which the player is disadvantaged due to the occurrence of an abnormality in the random number generation circuit 17.

  The count value is periodically counted up, and a counter that receives the reference pulse (reference clock signal) of the random number circuit and clears the count value is compared with the count value in the counter and a predetermined threshold value. A monitoring circuit including a comparator that outputs a reset signal when this threshold is reached has already been disclosed (for example, JP-A-11-313966). When this is applied to the present embodiment as it is and the random number generation circuit 17 is monitored by taking the reference clock signal S0 into the monitoring circuit 18, an abnormality caused by the malfunction of the reference clock signal output circuit 171 can be detected. However, an abnormality caused by the malfunction of the clock signal generation circuit 172 cannot be detected. That is, the reference clock signal output circuit 171 operates normally and the reference clock signal S0 is generated, but the clock signal generation circuit 172 malfunctions, and the count clock signal S1 and the latch clock signal S2 are not generated. When the random value R is not updated, the occurrence of the abnormality cannot be detected. For this reason, it is preferable that the monitoring circuit 18 monitors the random number generation circuit 17 by acquiring the count clock signal S1 or the latch clock signal S2 as in this embodiment. In this way, it is possible to detect not only the reference clock signal output circuit 171 but also the abnormality generated in the clock signal generation circuit 172, and the monitoring function of the monitoring circuit 18 is further increased.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 13 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, after interrupting is permitted (step S3), a loop process is started.

  CPU103 which performed the game control main process shown in FIG. 13 will perform the game control interruption process shown in the flowchart of FIG. 14, if the interruption request signal from CTC is received and an interruption request | requirement is received.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined switch process (step S11). In the switch process, it is determined whether or not the start winning signal SS input from the start port switch 72 via the switch circuit 107 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the switch timer memory 111. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary according to the diagnosis result (step S12). Thereafter, a determination random number update process for updating a predetermined determination random number (step S13) and a display random number update process for updating a predetermined display random number (step S14) are sequentially executed.

  Next, the CPU 103 executes special symbol process processing (step S15). In the special symbol process, the corresponding process is selected and executed according to the special symbol process flag provided in the flag memory 113 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state. Following the special symbol process, the CPU 103 executes a normal symbol process (step S16). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag provided in the flag memory 113 in order to control the normal symbol display 42 in a predetermined order.

  Further, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the effect control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S17). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in the predetermined command transmission table, and so on, for the sub-side control board such as the effect control board 12, etc. A control signal for controlling the progress of the game is transmitted. The effect control command sent from the main board 11 by this command control process is received by the CPU 200 of the effect control board 12, and display control of the variable display device 4 is performed according to the display control command.

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S18). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movable blade piece in the normal variable winning ball device 6 and open / close the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S19). Thereafter, by executing predetermined prize ball processing, the number of prize balls can be set based on the start winning signal SS input from the start port switch 72, and a payout control command can be output to the payout control board 15. (Step S20).

  FIG. 15 is a flowchart showing the error process executed in step S12. In this error processing, as shown in FIG. 15, the CPU 103 first checks an input state flag or the like provided in the flag memory 113 to determine whether the reset signal SR is input from the monitoring circuit 18 or not. It discriminate | determines (step S101). If it is determined that the reset signal SR has not been input (step S101; No), the error processing is terminated as it is.

  On the other hand, if it is determined that the reset signal SR is input (step S101; Yes), it is determined that an abnormality has occurred in the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17. The error flag provided in the flag memory 113 is set to the on state (step S102), and the error effect start command is set in the command transmission buffer for the effect control command. 12 is set to be sendable (step S103).

  16 and 17 are flowcharts showing the special symbol process executed in step S15. When the special symbol process is started, the CPU 103 first checks the timer value stored in the switch timer memory 111 to determine whether or not the game ball has won the normal variable winning ball device 6 as shown in FIG. Thus, the determination is made (step S111). In step S111, the CPU 103 loads the timer value stored in the switch timer memory 111, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). Thereby, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start port switch 72 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). can do.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S111; Yes), and a winning process is executed (step S112). clear.

  FIG. 18 is a flowchart showing the winning process in step S112. In this winning process, as shown in FIG. 18, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure holding memory 110 is the maximum value “4” (step S201). . Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S201; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S201; No), the output control signal SC is sent to the random value memory circuit 175, and the random value memory circuit 175 is controlled to be readable (enabled). (Step S202).

  Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S203), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S204), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 175 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S205). Then, the CPU 103 adds “1” to the start winning memory number (step S206), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S207).

  Thereafter, the CPU 103 determines whether or not an error flag provided in the flag memory 113 is turned on (step S113). If the error flag is on (step S113; Yes), it is determined that an abnormality has occurred in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17, and the flag is further increased. It is determined whether or not the value of the special symbol process flag provided in the memory 113 is “3” or less (step S114).

  If it is determined in step S114 that the value of the special symbol process flag is “3” or less (step S114; Yes), it is determined that no special symbol game is being played, and the special symbol process is performed as it is. The process ends. As a result, the CPU 103 can prevent the game from proceeding, such as when a special game is newly started after an abnormality occurs in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17. it can.

  On the other hand, when it is determined in step S111 that the timer value is less than the switch-on determination value “2” (step S111; No), it is determined in step S113 that the error flag is not on. If it is determined that the value of the special symbol process flag is larger than “3” in the process of step S114 (step S114; No), the CPU 103 stores the value in the flag memory 113. Based on the value of the special symbol process flag being selected, one of the nine processes of steps S120 to S128 shown in FIG. 17 is selected. Below, each process of step S120-S128 is demonstrated.

  The special symbol normal process in step S120 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0”. Here, in the special figure holding memory 110, when various data such as the random number R corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. If the number of reserved memories is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the effect control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S121 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 19, the CPU 103 first reads the random number value R stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S211). At this time, “1” is subtracted from the reserved storage number, and the random number R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is increased by one entry. (Step S212).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S213). If the probability change is not in progress (step S213; No), the CPU 103 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table 120 as shown in FIG. 4A is set (step S214). On the other hand, if the probability change is in progress (step S213; Yes), the probability change big hit determination table 121 as shown in FIG. 4B is set (step S215).

  Based on the random value R read in step S211, the CPU 103 determines whether or not the special game display result is a big hit using the big hit determination table 120 or 121 set in step S214 or S215 ( Step S216). If it is determined to be a big hit (step S216; Yes), the big hit flag provided in the flag memory 113 is set to the on state (step S217), and if it is determined to be lost (step S217) In step S216; No), the big hit flag is cleared and turned off (step S218). Thereafter, the value of the special symbol process flag is updated to “2”, which is a value corresponding to the fixed symbol determination process (step S219).

  The confirmed symbol determination process in step S122 shown in FIG. 17 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 determines whether or not the jackpot flag provided in the flag memory 113 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process in step S123 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 first determines whether or not the jackpot flag provided in the flag memory 113 is on, and determines whether or not to reach in the determined symbol determination process in step S122. And a predetermined variable display pattern table is set according to the determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in the current special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 103 updates the value of the special symbol process flag to “4” which is a value corresponding to the variable display command process.

  The variable display command process of step S124 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 103 controls the variable display device 4 to start variable display of all the decorative symbols. Specifically, the control data corresponding to the fixed symbol of the decorative design determined in the fixed symbol determination process of step S122 described above, or the control data corresponding to the variable display pattern determined in the variable display pattern setting process of step S123 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation commands can be sent to the effect control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S125 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 makes settings for sending a special symbol confirmation command from the main board 11 to the effect control board 12. Specifically, the special symbol confirmation command is set to be able to be sent to the effect control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S126 is a process executed when the value of the special symbol process flag is “6”. In this processing, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S127 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches, for example, 16, the condition for ending the specific gaming state (big hit gaming state) is established. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The big hit end process in step S128 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the effect control board 12. Further, the CPU 103 clears the big hit flag provided in the flag memory 113 and puts it in the off state. Then, the value of the special symbol process flag is updated to “0”.

  Next, the operation in the effect control board 12 will be described. FIG. 20 is a flowchart showing an effect control main process executed by the effect control CPU 200 mounted on the effect control board 12. When the production control main process is started, as shown in FIG. 20, first, a predetermined initialization process is executed to clear RAM 202, set various initial values, and determine the activation control activation interval. The second timer is initially set (step S21).

  Thereafter, the CPU 200 monitors a predetermined timer interrupt flag and executes a loop process until the timer interrupt flag is set (step S22; No). In this embodiment, a timer interrupt occurs every 33 milliseconds in the CPU 200, and when this timer interrupt occurs, a timer interrupt flag is set by executing a predetermined timer interrupt process.

  In the CPU 200, an interrupt for receiving the effect control command from the main board 11 is generated separately from the timer interrupt generated every 33 milliseconds. This interruption is an interruption that occurs when the effect control INT signal from the main board 11 is turned on. When an interruption occurs due to the turn-on of the effect control INT signal, the CPU 200 automatically sets the interrupt prohibited state. However, if a CPU that does not automatically enter the interrupt prohibited state is used, It is preferable to issue an insertion prohibition instruction (DI instruction).

  When the production control INT signal from the main board 11 is turned on, an interruption is generated in the CPU 200, whereby execution of the command reception interrupt process shown in the flowchart of FIG. 21 is started. In this command reception interrupt process, the CPU 200 first saves the value of each register in the stack (step S31). Subsequently, an effect control command is read from a predetermined input port or the like that receives a control signal that is assigned to the input of the effect control command data and transmitted from the main board 11 (step S32). And it is discriminate | determined whether it is the 1st byte of the production control commands of 2 bytes structure (step S33). Here, the first byte (MODE) and the second byte (EXT) of the effect control command are configured to be immediately distinguishable on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. When the first bit of the received command is “1”, it is determined that the valid first byte (MODE data) of the effect control command having a 2-byte configuration has been received.

  When it is determined that the MODE data is the first byte in the process of step S33 (step S33; Yes), the received command is received in the reception command buffer specified by the command reception number counter in the reception command buffer memory 210. Store (step S34). After executing the process of step S34, the process proceeds to the process of step S40. On the other hand, if it is not the first byte of the effect control command (step S33; No), it is determined whether or not the first byte of MODE data has already been received (step S35). Whether or not the first byte of MODE data has been received can be determined by checking the command data stored in the received command buffer.

  If the first byte has already been received (step S35; Yes), it is determined whether or not the first bit of the one byte received this time is “0”, and if the first bit is “0”. For example, assuming that a valid second byte is received, the received command is stored in the next reception command buffer specified by the command reception number counter (step S36). When it is determined in step S35 that the first byte of the effect control command has not been received (step S35; No), the first bit of the data received as the second byte is not “0”. The process proceeds to step S40.

  When the command data of the second byte is stored in the process of step S36, the value of the command reception number counter is incremented by 2 (step S37), and it is determined whether or not the value is “12” or more (step S38). . If it is “12” or more (step S38; Yes), the command reception number counter is cleared and its value is returned to “0” (step S39). On the other hand, when it is less than “12” (step S38; No), the process of step S39 is skipped. Thereafter, the register saved in the process of step S31 is restored (step S40), and interrupt permission is set (step S41).

  By such command reception interrupt processing, the effect control command transmitted from the main board 11 is stored in the reception command buffer provided in the reception command buffer memory 210, while the timer interrupt is performed in the processing of step S22 shown in FIG. Occurrence is confirmed. When occurrence of a timer interrupt is confirmed (step S22; Yes), a predetermined command analysis process is executed after the timer interrupt flag provided in the flag memory 211 is cleared and turned off (step S23).

  When the command analysis process is completed, the CPU 200 executes a predetermined error process to indicate that an error has occurred by the variable display device 4, the speakers 8L and 8R, the game effect lamp 9, and the like as necessary. (Step S24). Subsequently, after executing a counter update process (step S25) for updating a random value counted by a predetermined random counter, the CPU 200 executes an effect control process (step S26).

  FIG. 22 is a flowchart showing the command analysis processing in step S23 shown in FIG. In this command analysis process, as shown in FIG. 22, the CPU 200 first checks whether or not the effect control command received from the main board 11 is stored in the command reception table provided in the reception command buffer memory 210. (Step S301).

  When the reception command is stored in the command reception table (step S301; Yes), the CPU 200 reads the reception command from the command reception table (step S302), and whether or not the read reception command is an error effect start command. Is determined (step S303). When read, the read pointer value is incremented by one.

  When it is determined that the received command read in the process of step S302 is an error effect designation command (step S303; Yes), the CPU 200 sets an error effect start flag provided in the flag memory 211 to an ON state (step S303). In step S304, the process returns to step S301.

  On the other hand, when the received command read in the process of step S302 is another effect control command (step S303; No), a command reception flag corresponding to the received command is set (step S305), and the process of step S301 is performed. Return to

  On the other hand, if it is determined in step S301 that the received command is not stored in the command reception table (step S301; No), the command analysis process is terminated as it is.

  FIG. 23 is a flowchart showing details of the error processing executed in step S24 of FIG. In this error process, as shown in FIG. 23, the CPU 200 first determines whether or not the error presentation start flag provided in the flag memory 211 is turned on (step S311). If it is determined in step S311 that the error effect start flag is off (step S311; No), the error process is terminated.

  On the other hand, if it is determined in step S311 that the error effect start flag is on (step S311; Yes), the error effect start flag is cleared (step S312), and then a random number is generated from the CGROM 204. In the variable display device 4, the image data consisting of a character string for notifying that an abnormality has occurred in the circuit 17 is read out and a drawing command according to the read image data is sent to the VRAM 205. Settings are made to start an effect display for notifying that an abnormality has occurred in the random number generation circuit 17 (step S313).

  In this embodiment, a message indicating that an abnormality has occurred is displayed in an area above the area where the decorative symbol is variably displayed. For this reason, as shown in FIG. 24, even when decorative display variable display is being executed, a message indicating that an abnormality has occurred can be interrupted and displayed in the decorative display variable display. Note that a message indicating that an abnormality has occurred may be displayed on the variable display device 4 after the end of variable display of decorative symbols or after the end of the big hit gaming state.

  Further, when notifying that an abnormality has occurred, not only a display operation by the variable display device 4 but also an operation such as turning on a predetermined error lamp or generating a warning sound from the speakers 8L and 8R may be added. In addition, it may be in a mode of notifying that a payout error has occurred only by turning on an error lamp or generating a warning sound.

  As described above, according to this embodiment, the clock signal generation circuit 172 inputs the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  When a game ball wins the normal variable winning ball apparatus 6 which is a starting winning opening, the starting opening switch 72 sends a starting winning signal SS to the main board 11 and the random number generating circuit 17, and the random number generating circuit 17. The start winning signal SS sent to is input to the input terminal D of the latch signal output circuit 174 via the timer circuit 176. The latch signal output circuit 174 receives the start winning signal SS input to the input terminal D as the latch clock signal S2 input from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timing T11, T13, T15,... Rising from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  In this way, the random number generation circuit 17 can reliably change the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S0, the random number generation circuit 17 can update even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  On the other hand, on the side of the main board 11, the CPU 103 continuously inputs the start winning signal SS from the start port switch 72 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). When it is detected that a winning has been made, a winning process is executed.

  In this winning process, the CPU 103 sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a readable (enable) state, and then reads the random value R from the random value storage circuit 175. . Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 175 and controls the random value storage circuit 175 to be in a non-readable state (disabled), and then the read random value R becomes the predetermined determination value “ It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state by determining whether or not it matches with “2001 to 2184” or the like.

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 175 to the readable state only when the CPU 103 reads the random number value R. Can do. Further, since the CPU 103 reads the random value R from the random value storage circuit 175 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  The random number generation circuit 17 does not directly input the start winning signal SS output from the start port switch 72 to the latch signal output circuit 174 but temporarily inputs it to the timer circuit 176 to input the start winning signal SS. When the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 174. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 174 from erroneously outputting the latch signal SL to the random value storage circuit 175 due to the influence of noise or the like. Since the timer circuit 176 is set to “3 ms” which is shorter than “4 ms” between the executions of the two timer interrupt processes, the random number value R read out from the random value storage circuit 175 by the CPU 103 is the previous value. It is possible to prevent the same value as the random value R read at the time of winning a prize.

  In addition, when the latch signal SL is input from the latch signal output circuit 174, the random value storage circuit 175 converts the output control signal (high level signal) SC input from the game control microcomputer 100 into a low level signal. By converting to, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R from the random value storage circuit 175 when the random value R stored in the random value storage circuit 175 is updated. 1 can reliably and stably update the random value R.

  Furthermore, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 175 converts the latch signal (high level signal) SL input from the latch signal output circuit 174 into a low level signal. By converting to, the latch signal SL is controlled so as not to be received. Thereby, when the game control microcomputer 100 reads the random value R from the random value storage circuit 175, it is possible to prevent the random value R stored in the random value storage circuit 175 from being updated. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  Further, the frequency dividing circuit 181 of the monitoring circuit 18 takes in and divides the count clock signal S1 output from the clock signal generating circuit 172, and a frequency-divided clock signal S3 obtained by frequency division is provided with a watchdog. Output to the reset IC 182. In response to the rising edge of the system clock signal SSC supplied from the system clock generation circuit 60, the reset IC with watchdog 182 up-counts or down-counts the timer value of the built-in watch dog circuit, and the frequency dividing circuit 181 The timer value is initialized in response to the rising edge of the frequency-divided clock signal S3 input from.

  When the timer value of the watchdog circuit reaches the final value without receiving the frequency-divided clock signal S3, the reset IC with watchdog 182 sends the reference clock signal output circuit 171 and the clock signal generation circuit 172 to the random number generation circuit 17. A predetermined reset signal SR is output to the main board 11 as an abnormality has occurred. Then, on the main board 11 side, based on the detection of the reset signal SR by the CPU 103, the error flag provided in the flag memory 113 is set to ON, and an error effect is given to the effect control board 12. Send a start command.

  On the side of the effect control board 12, the CPU 200 starts an effect display for notifying the random number generation circuit 17 that an abnormality has occurred in the variable display device 4 based on the reception of this error effect start command.

  In this manner, by notifying the player that the abnormality has occurred in the random number generation circuit 17 and recognizing the player, it is possible to prevent the player from continuing the game while the abnormality is occurring in the random number generation circuit 17. be able to.

  Further, when the CPU 103 receives the reset signal from the monitoring circuit 18, the value of the special symbol process flag provided in the flag memory 113 is “3” or less, that is, when the special symbol game is not performed. Then, the special symbol process process is finished as it is. For this reason, the CPU 103 can prevent the game from proceeding such as when a special game is started after an abnormality occurs in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17. it can.

  On the other hand, even when the CPU 103 detects a game ball that has won the normal variable winning ball apparatus 6 even when receiving a reset signal from the monitoring circuit 18, the CPU 103 executes a winning ball process and receives a prize from the payout apparatus 50. Since the ball is paid out, it is possible to prevent the player from being disadvantaged due to the occurrence of an abnormality in the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17.

  As described above, when an abnormality occurs in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17, the pachinko gaming machine 1 notifies the player to that effect by the variable display device 4, While executing the process of restricting the start of a new special figure game, the payout of the winning ball based on winning in the ordinary variable winning ball device 6 is executed as usual. As a result, the pachinko gaming machine 1 prevents a situation in which the player is disadvantaged due to the occurrence of an abnormality in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17. Can do.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, the start opening switch 72 receives the start winning signal SS from the main board 11 and the random number generation circuit based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. The random number generation circuit 17 measures the time when the start winning signal SS is input from the start port switch 72 in the timer circuit 176, and the measured time becomes a predetermined time (for example, 3 ms). At that time, the start winning signal SS was output to the latch signal output circuit 174.

  However, the present invention is not limited to this, and the start port switch 72 outputs the start winning signal SS only to the main board 11, and the CPU 103 mounted on the main board 11 performs predetermined times (for example, twice). ) Is executed (for example, for 4 ms), the start winning signal SS for latch is latched on the basis of the fact that the start winning signal SS is continuously input from the start port switch 72. 174 may be sent.

  A gaming machine according to such a modification will be described below with reference to the drawings. FIG. 25 is a block diagram showing a configuration of a random number generation circuit 27 according to this modification. In addition, in the random number generation circuit 27, about the same structure as the random number generation circuit 17 which concerns on the said embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted as needed.

  As shown in FIG. 25, the random number generation circuit 27 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, and a random value storage circuit 175. Yes.

  The input terminal D of the latch signal output circuit 174 is connected to the I / O port 104, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175. The latch signal output circuit 174 generates and outputs a latch signal SL by synchronizing the latch start winning signal SE input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK. Output from terminal Q.

  FIG. 26 is a timing chart for explaining the operation of the random number generation circuit 27.

  As shown in FIG. 26A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  In response to the rising edge of the reference clock signal S0 input from the clock terminal CK, the clock signal generation circuit 172 responds to the rising clock of the reference clock signal S0 input from the clock terminal CK. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 26B, the positive-phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 26D, at the timing T11, T13, T15,..., The latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 26C, the counter 173 updates the count value C in response to the rising edge of the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 receives the latch start winning signal SE shown in FIG. 26E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 26 (F) is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2 input.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as a random value R, the stored random value R is updated as shown in FIG.

  Even in this case, the random number generation circuit 27 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In this modified example, the flag memory 113 shown in FIG. 3 is provided with a random value read flag in addition to the above-described flags. This random value read flag is set to the on state when the latch start winning signal SE is sent to the latch signal output circuit 174, and is cleared when the random number value R is read from the random value storage circuit 175 and is set to the off state. Become.

  FIG. 27 is a flowchart showing special symbol process processing executed in step S15 in this modification. When the special symbol process is started, the CPU 103 first determines whether or not the random number read flag provided in the flag memory 113 is on (step S1111).

  When the random number read flag is off (step S1111; No), by checking the timer value stored in the switch timer memory 111 whether or not the game ball has won the normal variable winning ball device 6, It is determined (step S1112). In step S1112, the CPU 103 loads the timer value stored in the switch timer memory 111, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). Thereby, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start port switch 72 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won (step S1112; Yes), and the winning process is executed (step S1113). clear.

  FIG. 28 is a flowchart showing the winning process in step S1113. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S1201). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S1201; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S1201; No), the latch start winning signal SE is sent to the latch signal output circuit 174 (step S1202), and the random number read flag is set to the ON state. (Step S1203).

  On the other hand, when the random number read flag is ON in the process of step S1111 (step S1111; Yes), the random value read process is executed (step S1114).

  FIG. 29 is a flowchart showing the random number value reading processing in step S1114. In this random value reading process, the CPU 103 first sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a readable (enable) state (step S1211). Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S1212), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S1213), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 175 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S1214).

  Then, the CPU 103 adds “1” to the start winning memory number (step S1215), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S1216). Thereafter, the CPU 103 clears the random number read flag and turns it off (step S1217).

  Thereafter, the CPU 103 determines whether or not an error flag provided in the flag memory 113 is turned on (step S1115). If the error flag is on (step S1115; Yes), it is determined that an abnormality has occurred in the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17, and the flag is further increased. It is determined whether or not the value of the special symbol process flag provided in the memory 113 is “3” or less (step S1116).

  If it is determined in step S1116 that the value of the special symbol process flag is “3” or less (step S1116; Yes), it is determined that no special symbol game is being played, and the special symbol process is performed as it is. End the process. As a result, the CPU 103 can prevent the game from proceeding, such as when a special game is newly started after an abnormality occurs in the reference clock signal output circuit 171 or the clock signal generation circuit 172 of the random number generation circuit 17. it can.

  On the other hand, when it is determined in step S1112 that the timer value is less than the switch-on determination value “2” (step S1112; No), it is determined in step S1115 that the error flag is not on. If it is determined that the value of the special symbol process flag is larger than “3” in the process of step S1116 (step S1116; No), the CPU 103 is stored in the flag memory 113. Based on the value of the special symbol process flag being selected, one of the nine processes of steps S120 to S128 shown in FIG. 17 is selected.

  As described above, according to this modification, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  When a game ball wins the normal variable winning ball apparatus 6 which is a starting winning opening, the starting opening switch 72 sends a starting winning signal SS only to the main board 11. The CPU 103 of the main board 11 is based on the fact that the start winning signal SS is continuously input from the start port switch 72 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Thus, it is determined that the game ball has won the normal variable winning ball apparatus 6, and a latch start winning signal SE is sent to the random number generation circuit 27.

  The latch start winning signal SE sent to the random number generation circuit 27 is inputted to the input terminal D of the latch signal output circuit 174. The latch signal output circuit 174 receives the latch start winning signal SE input to the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timings T11, T13, T15,... At which S2 rises from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  Thereafter, in the first timer interruption process, the CPU 103 reads the random value R from the random value storage circuit 175 and determines whether or not the read random value R matches a predetermined determination value “2001 to 2184” or the like. It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state.

  In this way, the random number generation circuit 27 can reliably vary the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Further, since the random number generation circuit 27 performs the updating of the count value C and the output of the latch signal SL without inverting the reference clock signal S0, the update is performed even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  Further, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the pachinko gaming machine 1 outputs the latch start winning signal SE to the latch signal output circuit 174 of the random number generation circuit 27. It is not necessary to provide a path for supplying the start winning signal SS from the start port switch 72 to the random number generation circuit 27, and the hardware configuration can be simplified.

  Further, the CPU 103 determines that the game ball has won the normal variable winning ball device 6 based on the continuous input of the start winning signal SS while the two timer interruption processes are being executed. Therefore, the pachinko gaming machine 1 can prevent the latch start winning signal SE from being erroneously output to the random number generation circuit 27 due to the influence of noise or the like.

  In addition, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 reads the random value R from the random value storage circuit 175 in the first timer interruption process. It is possible to prevent the read random value R from being the same as the previously read random value R.

  Further, the configuration of the random number generation means is not limited to the random number generation circuit 17 of the above embodiment, but the update timing of the count value C by the counter 173 and the output timing of the latch signal SL by the latch signal output circuit 174 ( (Latch timing) can be arbitrarily selected.

  For example, as shown in FIG. 30, a reference clock signal output circuit 171, a frequency divider circuit 177, a selector 178, a counter 173, a latch signal output circuit 174, a random value storage circuit 175, a timer circuit 176, It may be a random number generation circuit 37 constituted by: Note that in the random number generation circuit 37, the same components as those of the random number generation circuit 17 according to the above-described embodiment and the random number generation circuit 27 according to the modification are denoted by the same reference numerals, and description thereof is omitted as necessary. To do. In the figure, the monitoring circuit 18 is input with the count clock signal S5. However, the reference clock signal S0, the divided clock signal S4, and the latch clock signal S6 may be input. However, if it is possible to detect all abnormalities occurring in the reference clock signal output circuit 171, the frequency dividing circuit 177, and the selector 178 and enhance the monitoring function of the monitoring circuit 18, the monitoring circuit is the same as the above embodiment. 18, it is preferable to input the clock signal S5 for counting or the clock signal S6 for latching.

  The frequency dividing circuit 177 divides the reference clock signal S0 input from the reference clock signal output circuit 171 by 2, and generates a divided clock signal S4. The frequency dividing circuit 177 outputs the generated divided clock signal S4 to the selector 178.

  The selector 178 is composed of, for example, two complementary metal oxide semiconductor (CMOS) transistors forming a differential pair. The selector 178 converts the reference clock signal S1 input from the clock signal generation circuit 171 into the first and second output terminals O1 and O2 according to the level of the frequency-divided clock signal S4 input from the frequency-dividing circuit 177. Output from one of them.

  In this modification, when the frequency-divided clock signal S4 input from the frequency divider circuit 177 is at a high level, the selector 178 turns on the first output terminal O1 and turns off the second output terminal O2, and the reference clock. The reference clock signal S0 input from the signal output circuit 171 is output from the first output terminal O1. On the other hand, when the frequency-divided clock signal S4 input from the frequency divider circuit 177 is at a low level, the selector 178 turns off the first output terminal O1 and turns on the second output terminal O2, and the reference clock signal output circuit The reference clock signal S0 input from 171 is output from the second output terminal O2.

  FIG. 31 is a timing chart for explaining the operation of the random number generation circuit 37.

  As shown in FIG. 31A, the reference clock signal output circuit 171 generates a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to.

  As shown in FIG. 31 (B), the frequency dividing circuit 177 divides the inputted reference clock signal S0 by 2 and becomes high level during a period from T10 to T11, a period from T12 to T13,. A frequency-divided clock signal S4 that is at a low level in the period from T11 to T12, the period from T13 to T14,.

  The selector 178 receives an input from the reference clock signal output circuit 171 when the frequency-divided clock signal S4 input from the frequency-dividing circuit 177 is at a high level, that is, a period from T10 to T11, a period from T12 to T13,. The reference clock signal S0 is output from the first output terminal O1. Thus, as shown in FIG. 31C, the first output terminal O1 of the selector 178 outputs the count clock signal S5 that rises from the low level to the high level at the timing T10, T12,. The count clock signal S5 is supplied to the counter 173.

  The counter 173 updates and outputs the count value C in response to the rising edge of the count clock signal S1 supplied from the selector 178, as shown in FIG.

  On the other hand, the selector 178 receives the reference clock signal output circuit 171 when the frequency-divided clock signal S4 input from the frequency-dividing circuit 177 is at a low level, that is, during the period from T11 to T12, from T13 to T14,. Is output from the second output terminal O2. As a result, the latch output clock signal S6 rising from the low level to the high level is output from the second output terminal O2 of the selector 178 at the timings T11, T13,..., As shown in FIG. The latch clock signal S6 is supplied to the latch signal output circuit 174.

  The latch signal output circuit 174 synchronizes the start winning signal SS shown in FIG. 31 (F) input from the input terminal D with the rising edge of the latch clock signal S6 supplied from the selector 178 to the clock terminal CK. The latch signal SL shown in FIG. 31G is generated and output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  As described above, even when the random number generation circuit 17 is replaced with the random number generation circuit 37, the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174 are ensured. Therefore, the random number R can be acquired reliably and stably as in the above embodiment.

  Further, as shown in FIG. 32, as a random number generation circuit 47 including a reference clock signal output circuit 171, a delay circuit 179, a latch signal output circuit 174, a random value storage circuit 175, and a timer circuit 176. Also good. Note that in the random number generation circuit 47, the same components as those of the random number generation circuit 17 according to the above embodiment, the random number generation circuit 27 according to the modification, and the random number generation circuit 37 are denoted by the same reference numerals, and if necessary. The description thereof is omitted. In the figure, the reference clock signal S0 is input to the monitoring circuit 18, but a delayed clock signal S7 may be input. In this way, since it is possible to detect not only the reference clock signal output circuit 171 but also the abnormality occurring in the delay circuit 179, the monitoring function of the monitoring circuit 18 can be enhanced. It can be said that this is a preferred embodiment.

  The delay circuit 179 delays the reference clock signal S0 input from the reference clock signal output circuit 171 by a period that is different from a period that is an integral multiple of the period of the reference clock signal S0 to generate a delayed clock signal S7. The delay circuit 179 outputs the generated delayed clock signal S7 to the latch signal output circuit 174.

  FIG. 33 is a timing chart for explaining the operation of the random number generation circuit 47.

  As shown in FIG. 33A, the reference clock signal output circuit 171 supplies a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output.

  The counter 173 updates and outputs the count value C in response to the rising edge of the reference clock signal S0 input from the reference clock signal output circuit 171 as shown in FIG.

  On the other hand, the delay circuit 179 delays the reference clock signal S0 input from the reference clock signal output circuit 171 by ΔT (≠ nT: n is an integer), and as shown in FIG. , T22,..., Generate and output a delayed clock signal S7 having a period T rising from the low level to the high level.

  The latch signal output circuit 174 synchronizes the start winning signal SS shown in FIG. 33D inputted from the input terminal D with the rising edge of the delayed clock signal S7 inputted from the delay circuit 179 to the clock terminal CK. The latch signal SL shown in FIG. 33 (E) is generated and output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  As described above, even when the random number generation circuit 17 is replaced with the random number generation circuit 47, the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174 are ensured. Therefore, the random number R can be acquired reliably and stably as in the above embodiment.

  Further, in the above embodiment, when the CPU 103 receives a reset signal, the start of a new special figure game is restricted to prevent the game from progressing. However, the present invention is not limited to this, and when the CPU 103 receives a reset signal, a new random value may not be read from the random value storage circuit 175.

  In this case, in the winning process shown in FIG. 18, when it is determined in the process of step S201 that the start winning memory number is less than “4” (step S201; No), the CPU 103 sets an error flag provided in the flag memory 113. If the check box is checked and the flag is on, the winning prize process may be terminated after adding “1” to the start winning memory number without executing the processes of steps S202 to S205. In this way, it is possible to update the start winning memory number without reading a new random number value from the random value memory circuit 175.

  Furthermore, even if there is a winning, the start winning memory number may not be increased. In such a case, the special game may be executed until the starting winning memory number becomes “0”. Specifically, in the special symbol process shown in FIG. 16, after the winning process in step S112, the processes in steps S120 to S128 may be executed as they are without performing the processes in steps S113 and S114.

  Further, when the reset signal is received in the big hit gaming state, the progress of the game may be prevented by stopping the variable display of the decorative symbols on the variable display device 4 after the big hit gaming state ends.

  Furthermore, the start of a new special figure game may not be restricted. Specifically, in the special symbol process shown in FIG. 16, after the winning process in step S112, the processes in steps S120 to S128 are performed without performing the processes in steps S113 and S114. Only the process of notifying that an error has occurred may be executed. In this way, it is possible to prevent the player from feeling distrusted by stopping the progress of the game.

  In the above embodiment, the positive phase output terminal Q of the clock signal generation circuit 172 is connected to the input terminal of the counter 173, and the negative phase output terminal Q (bar) is connected to the input terminal D of the latch signal output circuit 174. Was connected. However, the present invention is not limited to this, and the positive phase output terminal Q of the clock signal generation circuit 172 is the input terminal Q of the latch signal output circuit 174, and the negative phase output terminal Q (bar) is the input terminal of the counter 173. , Each may be connected.

  Further, in the above embodiment, the counter 173 is an up counter, but the present invention is not limited to this, and may be a down counter. Further, the numerical value updating means is not limited to the counter 173, and may be a pseudo random number generation circuit. In addition, the connection between the output terminal of the bit data C0 to C15 of the count value C of the counter 173 and the input terminal of the bit data C0 to C15 of the count value C of the random value storage circuit 175 may be changed. Then, the randomness of the count value C input to the random value storage circuit 175 can be improved.

  In the above embodiment, the random value storage circuit 175 uses the logic circuits such as the AND circuits 701 and 703 and the OR circuits 730 to 745 to control the reception of the latch signal SL and the output control signal SC and output the random value R. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 175 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 104 and the latch signal output circuit 174, and the latch signal SL. In response to the input of the output control signal SC and the path to the I / O port 104 and the latch signal output circuit 174, the latch signal SL and the enable / disable control of the output control signal SC are performed. Also good.

  Further, in the above embodiment, the timer circuit 176 is activated in response to the input of the high level signal, and the reference clock signal from the reference clock signal output circuit 171 while the input is at the high level. In response to the input of S0, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, it is determined that the input signal is a high level signal. The signal is output to the latch signal output circuit 174. However, the present invention is not limited to this, and the timer circuit 176 measures the time during which the start winning signal SS is input from the start port switch 72, and when the measured time reaches a predetermined time, the start winning is received. Any signal can be used as long as it outputs the signal SS to the latch signal output circuit 174.

  In the above embodiment, the timer circuit 176 measures the signal input time using the reference clock signal S0 sequentially input from the reference clock signal output circuit 171, but the present invention is not limited to this. Instead, the timer circuit 176 may use a clock signal obtained by dividing the reference clock signal S0 or a clock signal output from a clock signal output circuit different from the reference clock signal output circuit 171. In the above embodiment, the timer circuit 176 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, and from the 4 ms that is the execution time of the two timer interrupt processes. Any time can be set as long as the time is short.

  Further, in the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 176 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  In the above embodiment, the abnormal signal output means is the reset IC 182 with a watchdog. However, the present invention is not limited to this, and the operation of the random number generation circuit 17 is based on whether or not a clock signal is input. Any device may be used as long as the state is monitored, and for example, a multivibrator including a capacitor, a resistor, a transistor element, and the like may be used. In this case, each time the rising edge of the divided clock signal is input to the multivibrator, the capacitor is charged for a predetermined period, and the capacitor continues to be discharged without the divided clock signal being input, and the voltage is set to a predetermined value. When the value falls below the threshold value, it is sufficient to output the reset signal SR to the main board 11 assuming that the operation state of the random number generation circuit 17 is abnormal.

  Furthermore, in the above-described embodiment, the gaming machine can perform the variable display start condition (for example, the previous variable display and the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball apparatus 6)). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the end of the big hit gaming state is established, This is a pachinko gaming machine that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the result is a predetermined specific display result.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 34, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 34 uses a game control means (for example, a main board) or a random number generation circuit as a start winning signal output means of the present invention based on a start lever 1011 operated by a player. A start switch (not shown) for outputting to (for example, a random number generation circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 34 functions as rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  Further, the apparatus configuration shown in FIGS. 1 and 34, the block configurations shown in FIGS. 2, 3, 5, 5, 6, 8, 10, 25, 30 and 32, FIGS. The timing chart configuration shown in FIGS. 26, 31 and 33, the circuit configuration shown in FIG. 9, the table configuration shown in FIG. 4, the memory configuration shown in FIG. 7, and the flowcharts shown in FIGS. 13-23 and 27-29. The configuration and the display example shown in FIG. 24 can be arbitrarily changed and modified without departing from the spirit of the invention.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the structural example of the table for jackpot determination. It is a block diagram which shows the hardware structural example in an effect control board. It is a block diagram which shows the structural example of an effect control board. It is a figure which shows the structural example of a reception command buffer memory. It is a block diagram which shows the structural example of a random number generation circuit. It is a circuit diagram which shows the structural example of a random value storage circuit. It is a figure for demonstrating the connection of the output terminal of the OR circuit of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random value storage circuit. 3 is a timing chart for explaining the operation of a random number generation circuit. It is a flowchart which shows the content of the game control main process. It is a flowchart which shows the content of the game control interruption process. It is a flowchart which shows the detail of the error process in FIG. It is a flowchart which shows the detail of the special symbol process process in FIG. It is a flowchart which shows the detail of the special symbol process process in FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a flowchart which shows the content of production control main processing. It is a flowchart which shows the content of a command reception interruption process. It is a flowchart which shows the detail of the command analysis process in FIG. 21 is a flowchart showing details of error processing in FIG. 20. It is a figure which shows the example of a display in a variable display apparatus. It is a block diagram which shows the modification of a random number generation circuit. 26 is a timing chart for explaining the operation of the random number generation circuit of FIG. It is a flowchart which shows the modification of the special symbol process process of FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the random value reading process in FIG. It is a block diagram which shows the modification of a random number generation circuit. FIG. 31 is a timing chart for explaining the operation of the random number generation circuit of FIG. 30. FIG. It is a block diagram which shows the modification of a random number generation circuit. FIG. 33 is a timing chart for explaining the operation of the random number generation circuit of FIG. 32. FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Variable display device
6 ... Ordinary variable winning ball device
7 ... Special variable winning ball device
8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Production control board
13 ... Audio output circuit
14… Lamp driver circuit
15 ... Dispensing control board
16 ... Information terminal board 17, 27, 37, 47 ... Random number generation circuit
21, 22 ... Solenoid
41 ... Special symbol indicator
42 ... Normal symbol display
50 ... Dispensing device
60 ... System clock generation circuit
70… Other prize opening switches
72… Start port switch
100 ... Game control microcomputer 101, 201 ... ROM
102, 202 ... RAM
103, 200 ... CPU
104 ... I / O port
107… switch circuit
108… Solenoid circuit
110… Special figure hold memory
111 ... Switch timer memory
112 ... Table memory for jackpot determination 113, 211 ... Flag memory
120 ... Normal jackpot judgment table
121… Table for jackpot determination at probability change
171... Reference clock signal output circuit
172... Clock signal generation circuit
173 ... Counter
174... Latch signal output circuit
175 ... Random value storage circuit
176 ... Timer circuit 177, 181 ... Frequency divider circuit
178 ... selector
179 ... Delay circuit
182 ... Reset IC with watchdog
203 ... VDP
204 ... CGROM
205 ... VRAM
206 ... Audio data output circuit
207 ... Ramp data output circuit
210: Receive command buffer memory 701, 703 ... AND circuit 702, 704 ... NOT circuit 710-725 ... Philip flop circuit 730-745 ... OR circuit
1000… Slot machine
1001 ... Liquid crystal display
1002. Variable display device
1011 ... Start lever

Claims (9)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
A game control microcomputer including a game control CPU for controlling the progress of the game;
A random number generator for generating random numbers;
With
The random number generation circuit includes:
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A clock signal generating means for generating a plurality of signals having the same period and different phases based on the reference clock signal;
With
The clock signal generation means includes
A clock terminal to which the reference clock signal is input from the reference clock signal output means;
An input terminal to which the first signal is input;
A first output terminal that outputs a signal in which a change state of the first signal is synchronized with a timing that changes at every predetermined period of the reference clock signal input from the clock terminal;
A second output terminal that outputs a signal having the same period and a different phase as the signal output from the first output terminal;
Including
The clock signal generation means includes
By connecting the second output terminal and the input terminal, the first clock signal output from the first output terminal and the first clock signal output from the second output terminal And a second clock signal having the same period and different phases,
The random number generation circuit includes:
Numerical data updating means for updating numerical data at a first timing when the first clock signal generated by the clock signal generating means changes in a predetermined manner;
Latch signal output means for outputting a latch signal at a second timing at which the second clock signal generated by the clock signal generation means changes in the predetermined manner;
Random value storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
Frequency dividing means for taking in and dividing at least one of the reference clock signal, the first clock signal, and the second clock signal;
When the clock signal divided by the frequency dividing means has not been input for a predetermined period or longer, an abnormal signal is output to the game control microcomputer as a signal indicating that an abnormality has occurred in the operating state of the random number generating circuit. Abnormal signal output means for
A random number generation circuit monitoring means comprising:
The game control microcomputer is:
Random value reading means for reading a random value from the random value storage means based on the execution condition of the variable display being satisfied,
By determining whether or not the random value read by the random value reading means matches a predetermined determination value based on the establishment of the variable display start condition, the display result in the variable display is obtained. A display result determining means for determining whether or not to obtain a specific display result;
An abnormal signal determining means for determining whether an abnormal signal is output from the abnormal signal output means;
An abnormality process execution means for executing a predetermined abnormality process when the abnormality signal determination means determines that an abnormality signal has been output;
Before the random value reading means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the random value reading means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
A game control microcomputer including a game control CPU for controlling the progress of the game;
A random number generator for generating random numbers;
With
The random number generation circuit includes:
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A numerical data update signal for updating numerical data is output at a first timing among a plurality of timings at which the reference clock signal output from the reference clock signal output means changes in a predetermined manner every predetermined cycle. Numerical data update signal output means;
Numerical data updating means for updating numerical data in response to a numerical data update signal input from the numerical data update signal output means;
Latch signal output means for outputting a latch signal at a second timing different from the first timing among the plurality of timings;
Random value storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
Frequency dividing means for taking in and dividing at least one clock signal of the reference clock signal, the numerical data update signal, and the latch signal;
When the clock signal divided by the frequency dividing means has not been input for a predetermined period or longer, an abnormal signal is output to the game control microcomputer as a signal indicating that an abnormality has occurred in the operating state of the random number generating circuit. Abnormal signal output means for
A random number generation circuit monitoring means comprising:
The game control microcomputer is:
Random value reading means for reading a random value from the random value storage means based on the execution condition of the variable display being satisfied,
By determining whether or not the random value read by the random value reading means matches a predetermined determination value based on the establishment of the variable display start condition, the display result in the variable display is obtained. A display result determining means for determining whether or not to obtain a specific display result;
An abnormal signal determining means for determining whether an abnormal signal is output from the abnormal signal output means;
An abnormality process execution means for executing a predetermined abnormality process when the abnormality signal determination means determines that an abnormality signal has been output;
Before the random value reading means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the random value reading means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
A game control microcomputer including a game control CPU for controlling the progress of the game;
A random number generator for generating random numbers;
With
The random number generation circuit includes:
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A clock signal delaying means for generating and outputting a delayed clock signal by delaying the reference clock signal output from the reference clock signal output means by a period different from a period that is an integral multiple of the predetermined period;
A first timing at which the reference clock signal output from the reference clock signal output means changes in a predetermined manner at each predetermined period and a delayed clock signal output from the clock signal delay means at each predetermined period. Numerical data updating means for updating numerical data at any one of the second timings that change in a predetermined manner;
A latch signal output means for outputting a latch signal at a timing different from the timing at which the numerical data update means updates the numerical data among the first timing and the second timing;
Random value storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
Frequency dividing means for taking in and dividing at least one of the reference clock signal and the delayed clock signal;
When the clock signal divided by the frequency dividing means has not been input for a predetermined period or longer, an abnormal signal is output to the game control microcomputer as a signal indicating that an abnormality has occurred in the operating state of the random number generating circuit. Abnormal signal output means for
A random number generation circuit monitoring means comprising:
The game control microcomputer is:
Random value reading means for reading a random value from the random value storage means based on the execution condition of the variable display being satisfied,
By determining whether or not the random value read by the random value reading means matches a predetermined determination value based on the establishment of the variable display start condition, the display result in the variable display is obtained. A display result determining means for determining whether or not to obtain a specific display result;
An abnormal signal determining means for determining whether an abnormal signal is output from the abnormal signal output means;
An abnormality process execution means for executing a predetermined abnormality process when the abnormality signal determination means determines that an abnormality signal has been output;
Before the random value reading means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the random value reading means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. Further comprising start signal output means for outputting a start signal to the game control microcomputer and the random number generation circuit based on the execution condition of the variable display being satisfied,
The random number generation circuit includes:
A timer means for measuring the time when the start signal is input from the start signal output means, and outputting the start signal to the latch signal output means when the measured time reaches a predetermined time;
The latch signal output circuit includes:
Outputting a start signal input from the start signal output means as the latch signal;
The gaming machine according to claim 1, 2, or 3. The game control microcomputer is:
In response to an interrupt request signal periodically input, includes timer interrupt processing execution means for executing timer interrupt processing,
The random value reading means includes:
While the timer interrupt process is executed by the timer interrupt process execution unit a predetermined number of times, the start signal is continuously input from the start signal output unit. Read
The timer means includes
Setting means for setting, as the predetermined time, a time shorter than a time when a predetermined number of timer interrupt processes are executed by the timer interrupt process executing means;
When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.
The gaming machine according to claim 4, wherein: The random value storage means includes
Including an output control signal reception control means for controlling the output control signal output from the read control means to an unreceivable state when a latch signal is input from the latch signal output means;
The gaming machine according to any one of claims 1 to 5 , characterized in that: An effect device that performs a predetermined effect;
An effect control microcomputer for controlling the effect operation by the effect device;
Further comprising
The abnormal process execution means includes:
Based on the determination that the abnormal signal has been output by the abnormal signal determination means, an effect control command for instructing execution of an effect to notify that an abnormality has occurred in the random number generation circuit is sent to the effect control micro Including production control command transmission means for transmission to a computer,
The production control microcomputer is:
Effect control command receiving means for receiving the effect control command transmitted by the effect control command transmitting means;
An effect control means for controlling the effect device based on the fact that the effect control command receiving means has received the effect control command, and causing the effect to notify that an abnormality has occurred in the random number generation circuit,
including,
The gaming machine according to any one of claims 1 to 6 , wherein the gaming machine is characterized by that. The abnormal process execution means includes:
Including variable display start restricting means for restricting start of variable display of identification information by the variable display device when it is determined that an abnormal signal is output by the abnormal signal determining means;
The gaming machine according to any one of claims 1 to 7 , wherein the gaming machine is characterized in that: A payout device for paying out game media;
A payout control microcomputer for controlling a payout operation by the payout device;
Further comprising
The game control microcomputer is:
A payout control command transmitting means for sending a payout control command for instructing payout of the game medium to the payout control microcomputer based on the establishment of a predetermined payout condition;
The dispensing control microcomputer is:
A payout control means for paying out game media from the payout device based on the payout control command;
The payout control command transmission means includes:
Even when it is determined that an abnormal signal is output by the abnormal signal determination means, when the predetermined payout condition is satisfied, the payout control command is transmitted to the payout control microcomputer,
The payout control means causes the game medium to be paid out from the payout device based on the payout control command;
The gaming machine according to any one of claims 1 to 8 , wherein the gaming machine is characterized by that.

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