JP4562441B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

Currently, in a gaming machine, a random number used for determining whether or not to make a “big hit” (a big hit determination random number) is generated by a microprocessor executing a predetermined application program. (For example, refer to Patent Document 1).
JP 2002-282457 A

  However, in the technique disclosed in Patent Document 1, since a random number is generated by a program, the processing load on the microprocessor is large. In particular, since random number update processing is performed during execution of timer interrupt processing for game control, it is necessary to develop a program similar to that for game control, and within a limited interrupt processing time. There was a problem that processing for generating a random number had to be started and ended, increasing the processing load on the microprocessor.

To solve this problem, a random number circuit is used to generate a big hit determination random number, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. A gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 2).
JP-A-7-124296 (page 3-4, FIG. 1).

  However, in the gaming machine described in Patent Literature 2, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that random number acquisition may not be performed stably.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a gaming machine capable of reducing the processing load on a microprocessor and obtaining a stable random value.

In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (e.g., a pachinko gaming machine 1) that has a particular gaming state (e.g., a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result. Power supply means for supplying power (for example, power supply board 10), random number circuit (for example, random number circuit 17) for generating random numbers (for example, random R), and game control C for controlling the progress of the game U (for example, CPU 103) and a game control microprocessor (for example, the game control microprocessor 100 mounted on the main board 11) that operates using power supplied from the power supply means, and the execution condition And a start signal output means (for example, a start winning port switch 70) for outputting a start signal to the random number circuit and the game control CPU based on the establishment of the random number circuit, the random number circuit comprising a reference clock having a predetermined cycle Reference clock signal output means (for example, clock circuit 106, first selector 71, external oscillation circuit, etc.) for outputting a signal (for example, reference clock signal S0), and a reference clock signal input from the reference clock signal output means Changes in a plurality of modes that repeat every predetermined period (for example, a low-frequency signal that the reference clock signal S0 repeats every period) A numerical value for updating numerical data (for example, count value C) in response to a change (for example, a rising edge) in the first aspect of the rising from the bell to the high level and the falling from the high level to the low level. A data update means (for example, a counter 73) and a start signal input from the start signal output means in a second mode different from the change in the first mode among the changes in the plurality of modes. A latch signal output means (for example, latch signal output circuit 78) that outputs a latch signal (for example, latch signal SL) in synchronization with a change (for example, a falling edge), and responds to a latch signal input from the latch signal output means. A random value storage means (for example, a random value storage circuit 79) for storing the numerical data updated by the numerical data update means as a random value; The game control CPU includes the random number after starting the supply of power by the power supply means and before setting the interrupt process to be executed periodically (for example, before the CPU 103 executes the process of step S11). The random number circuit setting means (for example, the part where the CPU 103 executes the process of step S10) for setting the circuit to generate the random number and the start signal input from the start signal output means The variable display is performed by reading a random number value from the numerical value storage means and then determining whether the read random number value matches predetermined determination value data based on the fact that the start condition is satisfied. Display result determining means for determining whether or not the display result in the display is the specific display result (for example, the CPU 103 receives the winning process in step S102 and step S1 A portion) that performs one of jackpot determination process, before the display result determining means reads a random number from the random number value storing means, the turbulent numeric storage unit and outputs an output control signal to the random numeric storage unit After the display result determination means reads the random value from the random value storage means, the output control signal is stopped from being output to the random value storage means and the random value storage means cannot be read. seen including a read control means for controlling the state of said random number storage means when said latch signal from the latch signal output means is input, even unreadable is output the output control signal from said read control means Output control signal reception control means for maintaining the state is included .

In order to achieve the above object, a gaming machine according to claim 2 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, a winning to a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (e.g., a pachinko gaming machine 1) that has a particular gaming state (e.g., a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result. Power supply means for supplying power (for example, power supply board 10), random number circuit (for example, random number circuit 17) for generating random numbers (for example, random R), and game control C for controlling the progress of the game U (for example, CPU 103) and a game control microprocessor (for example, the game control microprocessor 100 mounted on the main board 11) that operates using power supplied from the power supply means, and the execution condition And a start signal output means (for example, a start prize opening switch 70) for outputting a start signal to the game control CPU based on the establishment of the game control CPU, the game control CPU receives a start signal from the start signal output means. Trigger signal output means for outputting a predetermined trigger signal (for example, a count value fetch signal) to the random number circuit based on the input (for example, a portion where the CPU 103 executes the process of step S222), and in the variable display Display result determination means (for example, the CPU 103 determines whether or not the display result is the specific display result) The random number circuit includes a reference clock signal output means (for example, a clock) that outputs a reference clock signal (for example, the reference clock signal S0) having a predetermined cycle. The reference clock signal input from the circuit 106, the first selector 71, an external oscillation circuit, and the like and the reference clock signal output means are changed in a plurality of modes (for example, the reference clock signal S0, for example) that repeats every predetermined period. In response to a change (for example, a rising edge) in the first aspect of the rising from the low level to the high level and the falling from the high level to the low level that repeats every cycle. C) a numerical data update means (for example, a counter 73) for updating the random number by the random number update instruction means Based on the update instruction, the trigger signal output by the trigger signal output means is changed to a second mode (for example, a falling edge) different from the change in the first mode among the changes in the plurality of modes. In response to a latch signal output means (eg, latch signal output circuit 78) that outputs as a latch signal (eg, latch signal SL) in synchronization with the change in the Random number storage means (for example, random value storage circuit 79) for storing numerical data updated by the numerical data update means as a random value, and the display result determination means receives a start signal from the start signal output means. Based on the input, the random number value is read from the random value storage means (for example, the CPU 103 executes the random value reading process in step S204), Thereafter, based on the fact that the condition of the start condition is satisfied, by determining whether or not the read random number value matches predetermined determination value data, the display result in the variable display is set as the specific display result. (For example, the CPU 103 executes the jackpot determination process in step S111), and the game control CPU sets an interrupt process that is periodically executed after the power supply by the power supply means is started. Before (for example, before the CPU 103 executes the process of step S11), random number circuit setting means for setting the random number circuit to generate the random number (for example, the part where the CPU 103 executes the random number circuit setting process of step S10) ) and, before the display result determining means reads a random number from the random number value storing means, random number and outputs an output control signal to the random numeric storage unit The storage means is controlled to be readable, and after the display result determining means reads the random value from the random value storage means, the output of the output control signal to the random value storage means is stopped and the random value storage means see containing and a read control means for controlling the reading disabled state of said random number storage means when said latch signal is inputted from the latch signal output means, the output control signal is outputted from the read control means Includes an output control signal reception control means for maintaining the unreadable state .

4. The gaming machine according to claim 3, wherein the random number circuit setting means includes two types of clock signals (for example, a system clock signal) after the start of power supply by the power supply means and before interrupt processing that is periodically executed. And a divided clock signal) are selected by the reference clock signal selecting means (for example, the portion where the CPU 103 executes the process of step S24) and the reference clock signal selecting means. Including signal designation data setting means (for example, a portion where the CPU 103 executes the processing of steps S25 and S26) for setting signal designation data for designating a signal (for example, reference clock signal designation data) in the random number circuit, A selector (for example, a first selector) that sets the signal designation data by the signal designation data setting means. It includes a selector 71) of said selector outputs a signal indicating the set signal data specified by the signal specifying data setting means as the reference clock signal.

  5. The gaming machine according to claim 4, wherein the numerical data updating unit cyclically updates the numerical data from a predetermined initial value to a predetermined final value (for example, “65535”), and the random number circuit setting unit includes: A predetermined value (for example, “1”) and an identification number (for example, an ID number) unique to the gaming control microprocessor are set after the start of power supply by the power supply means and before the setting of interrupt processing to be executed periodically. And an initial value setting unit (for example, a portion where the CPU 103 executes the processing of steps S22 and S23) that sets the value selected from among the values indicated by the numerical value data updating unit as the predetermined initial value.

  6. The gaming machine according to claim 5, wherein the numerical data string changing means (for example, the CPU 103 in step S56) requests the change of the permutation, which is the update order of the numerical data supplied from the numerical data updating means to the random value storage means. The random number circuit has an update sequence different from that when the change of the numeric data sequence is not requested when the change of the numeric data sequence is requested by the numeric data sequence changing means. Numerical value permutation changing means (for example, a count value sequence changing circuit 74) to be changed is included.

  7. The gaming machine according to claim 6, wherein the game control microprocessor includes a plurality of the random number circuits, and the game control means includes a plurality of random number circuits included in the game control microprocessor. A random number generated from any one random number circuit is used for determining the display result by the display result determining means, and random numbers generated from other random number circuits are used for determination different from the determination of the display result.

  The inventions according to claims 1 to 6 of the present application have the following effects.

  According to the configuration of the first aspect, since the random number circuit is built in the game control microprocessor together with the game control CPU, a board space can be secured. In addition, by incorporating the random number circuit in the game control microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit from the outside due to the installation of an illegal board or the like. Prevention can be achieved. Further, since the game control microprocessor can control the update operation of the random number value stored in the random value storage means according to the setting made by the random number circuit setting means, for example, it differs for each gaming machine. By performing the setting, it is possible to improve the randomness of the random numbers read from the random value storage means and used for determining whether or not the display result in the variable display is the specific display result. Further, since it is determined whether or not the display result in the variable display is set as the specific display result using the random number generated from the random number circuit, the processing load on the game control CPU can be reduced. In addition, the random number circuit updates the numerical data in response to the change in the first mode among the changes in the plurality of modes in which the reference clock signal repeats every predetermined period, and The start signal input from the start signal output means is output as a latch signal in synchronization with the change in the second mode different from the change in the first mode among the changes in the plurality of modes. . In this way, the random number circuit can reliably make the update timing of the numerical data different from the latch timing of the numerical data. As a result, the display result determining means can stably acquire the random value. Further, according to this configuration, since the display result determination unit reads the random value from the random value storage unit based on the input of the start signal, useless processing can be omitted.

  According to the configuration of the second aspect, since the random number circuit is built in the game control microprocessor together with the game control CPU, a board space can be secured. In addition, by incorporating the random number circuit in the game control microprocessor, it becomes difficult to rewrite the numerical data indicating the random number value generated by the random number circuit from the outside due to the installation of an illegal board or the like. Prevention can be achieved. Further, since the game control microprocessor can control the update operation of the random number value stored in the random value storage means according to the setting made by the random number circuit setting means, for example, it differs for each gaming machine. By performing the setting, it is possible to improve the randomness of the random numbers read from the random value storage means and used for determining whether or not the display result in the variable display is the specific display result. In addition, the random number circuit updates the numerical data in response to the change in the first mode among the changes in the plurality of modes in which the reference clock signal repeats every predetermined period, and The trigger signal generated by the trigger signal generation means is output as a latch signal in synchronization with the change in the second mode different from the change in the first mode among the changes in the plurality of modes. . In this way, the random number circuit can reliably make the update timing of the numerical data different from the latch timing of the numerical data. As a result, the display result determining means can stably acquire the random value. Further, according to this configuration, since the display result determination unit reads the random value from the random value storage unit based on the input of the trigger signal, useless processing can be omitted. Further, the trigger output means outputs a trigger signal to the latch signal output means based on the input of the start signal from the start signal output means, so that the start signal output means sends the trigger signal to the random number circuit. There is no need to provide a path for supplying the start signal, and as a result, the hardware configuration of the gaming machine can be simplified.

  According to the configuration of claim 3, in order to output any one of the third clock signal and the fourth clock signal as the reference clock signal, the random value storage means The randomness of the random number that is read and used to determine whether or not the display result in the variable display is the specific display result can be improved.

  According to the configuration of the fourth aspect, the numerical data updating unit uses a value selected from a predetermined value and a value indicated by an identification number unique to the game control microprocessor as the predetermined initial value. By setting to, randomness of random numbers read out from the random value storage means and used to determine whether or not the display result in the variable display is the specific display result can be enhanced.

  According to the configuration of claim 5, when the change of the numerical data string is requested by the numerical data string changing means, the change is made to a permutation of an update order different from that when the change of the numerical data string is not requested. be able to. For this reason, by giving randomness to the timing for requesting the change of the numerical data string, it is read out from the random value storage means to determine whether or not the display result in the variable display is set as the specific display result. The randomness of the random numbers used can be improved.

  According to the configuration of claim 6, a plurality of the random number circuits are built in the game control microprocessor, and random numbers generated from the plurality of random number circuits are used for various decisions relating to the game, thereby enabling the game control. The processing burden on the CPU can be further reduced.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is disposed. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. Also, a normal symbol display 40 is provided on the right side of the variable winning ball apparatus 7.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information in a plurality of display areas. For example, a game ball may win a normal variable winning ball device 6. In the special figure game that is the execution condition, variable display of three display symbols (special symbols) composed of numbers, letters, symbols, etc. is started, and after a certain period of time, the symbols are displayed in the order of left, right, and middle. Confirm. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. Here, in the special figure game by the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, The pachinko gaming machine 1 enters a special game state (probability improvement state) following the end of the big hit game state, and thereafter, the probability that the display result in the special figure game becomes a big hit combination is increased until a predetermined condition is satisfied. In the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 is configured to include a light emitting diode (LED) or the like, and is lit, flashed, or flashed in a normal game where a game ball passes through a predetermined passing gate provided in the game area. Color development is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normally variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 3). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding memory 110 (FIG. 22) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 3). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2), which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10 that functions as power supply means, a main board 11, a display control board 12, a voice control board 13, a lamp control board 14, and a payout control board 15. And an information terminal board 16 are disposed at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  The control command transmitted from the main board 11 to the display control board 12 is a display control command. FIG. 3 is a block diagram showing a circuit configuration of the main board 11 and signal lines of display control commands transmitted from the main board 11 to the display control board 12.

  The main board 11 is connected to a wiring from the start winning a prize opening switch 70. The main board 11 is also connected with wiring from a special variable winning ball apparatus 7 which is a big winning opening and various switches for detecting winning of a game ball to other winning openings. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The main board 11 is configured by mounting a game control microprocessor 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microprocessor 100 is, for example, a one-chip microprocessor, and includes a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a control operation. A CPU (Central Processing Unit) 103, an I / O (Input / Output) port 104, a CTC (Counter Timer Circuit) 105 that sends an interrupt request signal to the CPU, a clock circuit 106, a random number circuit 17, and a reset controller 109 Built-in.

  The clock circuit 106 generates a system clock signal and sends it to the CPU 103, the random number circuit 17, etc., and sends a divided clock signal generated by dividing the system clock signal to each circuit. When a low level signal is input for a certain period, the reset controller 109 sends a predetermined initialization signal to the CPU 103, the random number circuit 17 and the like to reset the game control microprocessor 100 as a system.

  FIG. 4 is a block diagram illustrating a configuration example of the random number circuit 17. As shown in FIG. 4, the random number circuit 17 includes a first selector 71, a counter 73, a count value sequence changing circuit 74, a count value fetching circuit 75, a timer circuit 76, and a second selector 77. , A latch signal output circuit 78, a random value storage circuit 79, and an operation start circuit 80. The random number circuit 17 generates, for example, a random R that is a random number for determining a big hit that generates a big hit and determines whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The first selector 71 designates a reference clock signal for storing reference clock signal designation data for designating a signal selected as the reference clock signal S0 from the system clock signal and the divided clock signal output from the clock circuit 106. A register (RTS) 71a is provided. The divided clock signal input to the first selector 71 may be generated by dividing the system clock signal, or may be generated from a clock signal other than the system clock signal, for example, an external oscillation circuit. May be generated by dividing the clock signal.

  FIG. 5A is a diagram illustrating a configuration example of the reference clock signal designation register 71a. As shown in FIG. 5A, the reference clock signal designation register 71a is an 8-bit register, and its initial value is set to “00h”. The reference clock signal designating register 71a is configured so that bits 0 to 1 can be written and read, and bits 2 to 7 cannot be written and read. Therefore, even if a value is written in bits 2 to 7 of the reference clock signal designation register 71a, the value is invalid, and all values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 5B is an explanatory diagram of an example of reference clock signal designation data written to the reference clock signal designation register 71a. As shown in FIG. 5B, the reference clock signal specifying data is composed of 2-bit data, “01b” is data specifying the system clock signal, and “10b” is the divided clock signal. The data to be specified.

  Therefore, when the reference clock signal designation data “01b” is written in the reference clock signal designation register 71a, the first selector 71 shown in FIG. 4 outputs the counter 73 and the latch signal with the system clock signal as the reference clock signal S0. On the other hand, when “10b” is written, the divided clock signal is supplied to the counter 73 and the latch signal output circuit 74 as the reference clock signal S0. When the reference clock signal designation data “00b” or “11b” is written in the reference clock signal designation register 71a, the random number circuit 17 cannot be activated.

  The counter 73 stores a counter initial value setting register (RSV) 73a that stores counter initial value setting data for specifying an initial value of the count value C. In response to the rising edge of the count clock signal S1 input from the first selector 71, the counter 73 sets the count value C to be output from the counter initial value set in the counter initial value setting register 73a to a predetermined value. It is updated cyclically up to the counter final value.

  In this embodiment, the counter 73 is a 16-bit binary counter, and the count value C is set to the counter initial value setting register 73 every time the rising edge of the count clock signal S1 is input. The value is incremented by 1 from the value to the counter final value “65535”. When the count value C is counted up to “65535”, the counter is reset to the initial value, and again counted up to “65535”.

  When the count value C is updated to the counter final value “65535”, the counter 73 sends a count value round notification signal to the CPU 103 to notify that the count value has been rounded.

  FIG. 6 is a diagram illustrating a configuration example of the counter initial value setting register 73a. As shown in FIG. 6, the counter initial value setting register 73a is a readable / writable 16-bit register, and its initial value is set to “1 (= 0001h)”. In this embodiment, the counter initial value setting register 73a is set with counter initial value setting data indicating a predetermined value (for example, “1”) or an ID number unique to the game control microprocessor 100.

  The count value sequence change circuit 74 includes a count value sequence change register (RSC) 74a for storing count value permutation change data “01h” for requesting change of the permutation, which is the update order of count count values, and a bit scramble pattern selection circuit 74b. And a bit scramble circuit 74c. The count value sequence changing circuit 74 changes the order of the count value sequence supplied from the counter 73 to the random value storage circuit 79 by replacing or transposing the bits of the count value C output from the counter 73.

  FIG. 7 is a diagram illustrating a configuration example of the count value string change register 74a. As shown in FIG. 7, the count value sequence change register 74a is a readable 8-bit register, and its initial value is set to “0 (= 00h)”. The count value sequence change register 74a is configured so that only bit 0 is writable and writable. Therefore, even if a value is written to bit 1 to bit 7, the value is invalid, and bit 1 to bit 7 are written. All the values read from “0” are “0 (= 0000000b)”.

  In response to the count value sequence change circuit 74 accepting the change in the order of the count value sequence, the CPU 103 initializes the count value sequence change register 74a in which the count value sequence change data “01h” is written. The stored value is returned to the initial value “0 (= 00h)”.

  The bit scramble pattern selection circuit 74b shown in FIG. 4 includes a bit scramble pattern determination table 74d that stores a plurality of bit replacement patterns of the count value C, and the count value string change data “01h” is stored in the count value string change register 74a. In response to the writing, the bit scramble pattern is selected and determined from the bit scramble pattern determination table 74d based on the value of a predetermined auxiliary random number.

  FIG. 8 is a diagram illustrating a configuration example of a bit scramble pattern determination table. As shown in FIG. 8, the bit scramble pattern determination table 74d stores a predetermined auxiliary random number value input to the bit scramble pattern selection circuit 74b and a bit scramble pattern in association with each other.

  In this embodiment, corresponding to the data length of the count value C being 16 bits, the bit scramble pattern determination table 74d stores 65536 bit scramble patterns including the original arrangement. .

  The bit scramble circuit 74c shown in FIG. 4 arranges and changes the bits of the count value C according to the bit scramble pattern selected and determined by the bit scramble pattern selection circuit 74b, and the count value C obtained by arranging and changing the bits. Is output to the random value storage circuit 79.

  In this way, the count value sequence changing circuit 74 changes the order of the count value sequence supplied from the counter 73 to the random value storage circuit 79.

  The count value fetching circuit 75 shown in FIG. 4 includes a count value fetching register (RLT) 75a for storing count value fetching data “01h” for requesting the count value fetching into the random value storage circuit 79. The count value fetch circuit 75 outputs a count value fetch signal in response to the count value fetch data “01h” being written in the count value fetch register 75a.

  FIG. 9 is a diagram illustrating a configuration example of the count value fetch register 75a. As shown in FIG. 9, the count value fetch register 75a is an 8-bit register that cannot be read. Only the bit 0 is writable, and even if a value is written to the bits 1 to 7, the value is invalid. It is.

  The timer circuit 76 shown in FIG. 4 measures the time during which the start winning signal SS is input from the start winning opening switch 70. When the measured time reaches a predetermined time (for example, 3 ms), the timer winning signal SS is displayed. Output to the second selector 77.

  In this embodiment, the timer circuit 76 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. While the input is at a high level, the timer circuit 76 counts up or down a predetermined timer value every time the reference clock signal S0 is input from the first selector 71. When the timer value counted up or down reaches a value corresponding to 3 ms, the timer circuit 76 determines that the input signal is the start winning signal SS and sets the start winning signal SS to the second winning signal SS. Is output to the selector 77.

  Second selector 77 designates a signal selected as a latch signal from start winning signal SS input from timer circuit 76 and count value acquisition signal input from count value acquisition circuit 75. A latch signal specifying register (RTS) 77a for storing latch signal specifying data to be stored. The configuration of the latch signal designation register (RTS) 77a is the same as that of the reference clock signal designation register 71a shown in FIG.

  FIG. 10 is an explanatory diagram of an example of latch signal designation data written to the latch signal designation register 77a. As shown in FIG. 10, the latch signal designating data is composed of 2-bit data, like the reference clock signal designating data, “01b” is data designating the start winning signal SS, and “10b” is This data specifies the count value fetch signal.

  Therefore, when the latch signal designation data “01b” is written in the latch signal designation register 77a, the second selector 77 shown in FIG. 4 outputs the start winning signal SS to the latch signal output circuit 78, while , “10b” is written, a count value fetch signal is output to the latch signal output circuit 78. When the latch signal designation data “00b” or “11b” is written in the latch signal designation register 77a, the random number circuit 17 cannot be activated.

  In this embodiment, since the start winning signal SS input from the start winning port switch 70 is used as the latch signal SL, “01b” is set in the latch signal designation register 77a.

  The latch signal output circuit 78 is configured by a D-type lip flop circuit or the like. The input terminal D of the latch signal output circuit 78 is connected to the output terminal of the second selector 77, and the clock terminal CK is connected to the output terminal of the first selector 71. The output terminal Q of the latch signal output circuit 78 is connected to the random value storage circuit 79.

  The latch signal output circuit 78 synchronizes the start winning signal SS or the count value capture signal input from the input terminal D with the falling edge of the reference clock signal S0 input from the clock terminal CK, and outputs the latch signal SL. And output from the output terminal Q.

  The random value storage circuit 79 is a 16-bit register, and stores a random value R that is read in a winning process in step S102 described later. The random value storage circuit 79 latches and stores the count value C input from the counter 73 as the random value R in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 78. Thus, every time the start winning signal SS is inputted to the random number circuit 17 or every time the count value fetch data “01h” is written to the count value fetch register 75a, the stored random number R is sequentially updated. .

  FIG. 11 is a circuit diagram showing a configuration example of the random value storage circuit 79. As shown in FIG. 7, the random value storage circuit 79 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 Philip flop circuits 210 to 225, and 16 OR circuits. 230-245.

  The input terminal of the AND circuit 201 is connected to the output terminal Q of the latch signal output circuit 78 and the output terminal of the NOT circuit 204, and the output terminal is the input terminal of the NOT circuit 202 and the clock terminal CK0 of the Philip flop circuits 210 to 225. To CK15. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the I / O port 104 of the game control microprocessor 100, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 230 to 245.

  Input terminals D0 to D15 of the Philip flop circuits 210 to 225 are connected to an output terminal of the counter 73. The clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 are connected to the output terminal of the AND circuit 201, and the output terminals Q0 to Q15 are connected to the other input terminals of the OR circuits 230 to 245, respectively.

  The input terminals of the OR circuits 230 to 245 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 210 to 225, respectively, and the output terminals are connected to the I / O port 104 of the game control microprocessor 100. It is connected.

  FIG. 12 is a diagram for explaining the details of the connection between the output terminals of the OR circuits 230 to 245 and the I / O port 104 of the game control microprocessor 100. In this embodiment, the output terminals of the OR circuits 230 to 245 and the bits of the jackpot random number input port included in the I / O port 104 are interchanged and connected as shown in FIG. Yes. Thereby, the randomness of the random number input to the game control microprocessor 100 can be improved.

  The operation of the random value storage circuit 79 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the gaming control microprocessor 100 (when one input of the AND circuit 203 is low level), the output terminal Q of the latch signal output circuit 78 At the timing when the input latch signal SL rises from low level to high level (in the example shown in FIG. 13, timings T1, T2, T7), the inputs of the AND circuit 201 both become high level and are output from the output terminals. The signal SR becomes high level. The signal SR output from the AND circuit 201 is input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225.

  The Philip flop circuits 210 to 225 respond to the rising edge of the signal SR input from the clock terminals CK0 to CK15, and receive bit data C0 to C15 of the count value C input from the counter 73 via the input terminals D0 to D15. Are latched and stored as bit data R0 to R15 of the random number value, and the bit data R0 to R15 of the stored random number value R are output from the output terminals Q0 to Q15.

  When the output control signal SC is not input (in the example shown in FIG. 13, the period up to the timing T3 and the period after the timing T6), one of the inputs of the AND circuit 203 is at the low level, so that the output is output from the output terminal. The signal SG to be output becomes a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Thus, since one input of the OR circuits 230 to 245 is at the high level, regardless of whether the signal input to the other input terminal is at the high level or the low level, that is, the input random number value. Regardless of whether the values of the R bit data R0 to R15 are “0” or “1”, the signals SO0 to SO15 output from the OR circuits 230 to 245 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 79 is always “635535 (= FFFFh)”, and the random value R cannot be read from the random value storage circuit 79. That is, when the output control signal SC is not input, the random value storage circuit 79 is in an unreadable (disabled) state.

  Then, when the output control signal SC is input from the gaming control microprocessor 100 when the latch signal SL input from the latch signal output circuit 78 is at the low level (in the example shown in FIG. 13, from the timing T4 to the timing T6). Since the inputs of the AND circuit 203 are both at a high level, the signal SG output from the output terminal is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminal of each of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the value of the bit data R0 to R15 of the random value R input to the other input terminals of the OR circuits 230 to 245 is directly from the output terminal of the OR circuits 230 to 245 (the value of the bit data R0 to R15 is “1”). "1" is output when it is "," and "0" is output when it is "0." As a result, the random value R can be read from the random value storage circuit 79. That is, when the output control signal SC is input, the random value storage circuit 79 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 78 before the output control signal SC is input from the gaming control microprocessor 100, one input of the AND circuit 203 becomes low level. After that, even when the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 13, it is output from the output terminal). The signal SG remains at a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 becomes high level in this way, the output from the OR circuits 230 to 245 is performed regardless of whether the signal input to the other input terminal is high level or low level. All of the signals SO0 to SO15 are at a high level, and the random number value R cannot be read from the random value storage circuit 79 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 79 becomes incapable of receiving the output control signal SC.

  When the output control signal SC is input from the gaming microcomputer 100 before the latch signal SL input from the latch signal output circuit 78 becomes high level, one input of the AND circuit 201 becomes low level. Therefore, after that, even if the input latch signal SL becomes high level (in the example shown in FIG. 13, timing T5) while the output control signal SC is being input, it is output from its output terminal. The signal SR remains at a low level. For this reason, the signal SR input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 does not rise from the low level to the high level, and the bit data R0 of the random value R stored in the Philip flop circuits 210 to 225. ˜R15 are not updated even when the latch signal SL input from the latch signal output circuit 78 rises. That is, when the output control signal SC is input, the random value storage circuit 79 becomes incapable of receiving the latch signal SL.

  The operation start circuit 80 illustrated in FIG. 4 includes an operation start register (RST) 80 a that stores operation start data “80h” for requesting activation of the random number circuit 17. In response to the operation start data “80h” being written in the operation start register 80a, the operation start circuit 80 outputs a predetermined operation start signal, turns on the counter 73, and updates the count value by the counter 73. Start operation.

  FIG. 14 is a block diagram illustrating a configuration example of the operation start register 80a. As shown in FIG. 14, the operation start register 80a is an 8-bit register, and its initial value is set to “00h”. The operation start register 80a is configured such that only bit 7 is readable and readable, and even if a value is written in bits 0 to 6, the value is invalid, and all the values read from bit 0 to bit 6 are “0”. (= 0000b) ".

  FIG. 15 is a timing chart for explaining the operation (action) of the random number circuit 17 having the above configuration.

  As shown in FIG. 15A, the first selector 71 outputs a reference clock signal S0 that rises from a low level to a high level at, for example, timings T10, T12, T14,. To do.

  As shown in FIG. 15B, the counter 73 updates the count value C every time the rising edge of the reference clock signal S0 input from the first selector 71 is input, and stores it in the random value storage circuit 79. Output. The latch signal output circuit 78 synchronizes the start winning signal SS shown in FIG. 15C inputted from the input terminal D with the falling edge of the reference clock signal S0 inputted from the first selector 71, and FIG. The latch signal SL shown in (D) is output.

  As a result, the random number circuit 17 rises at the rising timing T10, T12, T14,... Among the rising timing from the low level to the high level and the falling timing from the high level to the low level, which the reference clock signal S0 periodically repeats. , The count value C is updated, and the latch signal SL can be output at the falling timings T11, T13, T15.

  Then, the random value storage circuit 79 uses the count value C input from the counter 73 to the input terminal D as the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 78 to the clock terminal CK. In response, the random number value R is latched and stored, thereby updating the stored random number value R as shown in FIG.

  In this way, the random number circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  FIG. 16 is a diagram showing an example of an address map in the gaming control microprocessor 100 shown in FIG. As shown in FIG. 16, the area from 0000h to 1FFFh is allocated to the ROM 101, the area from 7E00h to 7FFFh is allocated to the RAM 102, and the area from FD00h to FE00h is the counter initial value setting register 73a. Etc. are assigned to built-in registers.

  A program (user program) created in advance by the user is stored in the user program area in the area from 0000h to 1F7Fh in the ROM 101, and the CPU 103 is a user program in the user program management area in the area from 1F80h to 1FFFh. The data (user program execution data) necessary for executing is stored. Further, the area of addresses 7E00h to 7EFFh in the RAM 102 is not used, and addresses 7EFFh to 7FFFh are used as work areas.

  FIG. 17 is a diagram showing an example of an address map in the user program management area shown in FIG. As shown in FIG. 17, in the area of address 1F96h, reference clock signal selection data indicating an output signal selected by the user as reference clock signal S0 from the system clock signal and the divided clock signal is stored, and address 1F97h is stored. In this area, latch signal selection data indicating an output signal selected by the user from the start winning signal SS and the count value fetch signal is stored.

  In the area of address 1F98h, a counter initial value indicating a value selected by the user as a count initial value from a predetermined value (for example, “1”) and a value indicated by an ID number unique to the gaming control microprocessor 100 is displayed. The selection data is stored, and in the area of address 1F99h, the count value indicating the count value sequence change method selected by the user from the first and second count value sequence change selection methods, which are methods for changing the counter value sequence Column change method selection data is stored.

  FIG. 18 is an explanatory diagram of an example of reference clock signal selection data. As shown in FIG. 18, the reference clock selection data is composed of 8-bit data, “01h” is data indicating that the system clock signal is selected as the reference clock signal S0, and “02h” is Data indicating that the divided clock signal is selected as the reference clock signal.

  FIG. 19 is an explanatory diagram of an example of latch signal selection data. As shown in FIG. 19, the latch signal selection data is composed of 8-bit data, “01h” is data indicating that the start winning signal SS is selected as a latch signal, and “02h” is latched. This is data indicating that the count value capture signal is selected as the signal. In this embodiment, “01h” which is data indicating the start winning signal SS is selected.

  FIG. 20 is an explanatory diagram of an example of counter initial value selection data. As shown in FIG. 20, the initial value selection data is composed of 8-bit data, “00h” is data indicating that the predetermined value “1” is selected as the counter initial value, and “01h” is , Data indicating that the ID number value is selected as the counter initial value.

  FIG. 21 is an explanatory diagram of an example of count value string change method selection data. As shown in FIG. 21, the count value sequence changing method selection data is composed of 8-bit data, “00h” is data indicating that the count value sequence is not changed, and “01h” is the first value. This is data indicating that the count value sequence changing method has been selected, and “02h” is data indicating that the second count value sequence changing method has been selected.

  Further, as shown in FIG. 22, the gaming control microprocessor 100 shown in FIG. 3 includes a special figure holding memory 110, a random counter 111, a jackpot determination table memory 112, a flag memory 113, and a start winning mouth switch. Timer memory 114.

  In the special figure holding memory 110, a condition (execution condition) for executing a variable symbol display (special symbol game) for a game ball winning the normal variable winning ball device 6 is established, but the previous variable symbol display is performed. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 110 includes four entries, and each entry has a holding number and a random number value R read from the random value storage circuit 79 in accordance with the winning order in the winning order to the normal variable winning ball apparatus 6. Are stored in association with each other. Each time the special symbol confirmation command is sent from the main board 11 to the display control board 12 and the special symbol variable display is finished once or the big hit gaming state is finished, the variable display based on the highest level information is performed. The start condition is satisfied, and variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball newly wins the normal variable winning ball apparatus 6 while the special symbol is variably displayed, the random value R read from the random value storage circuit 79 based on the winning is the highest empty. Registered in the entry.

  The random counter 111 counts determination random numbers and display random numbers used for game control. FIG. 23 is an explanatory diagram showing random numbers counted by the random counter 111. As shown in FIG. 23, the random counter 111 counts a random R200. Random R200 is a determination random number for determining whether or not to change the order of the count value sequence, and takes a value in the range of “0” to “1530”.

  The jackpot determination table memory 112 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 112 stores a normal big hit determination table 121 shown in FIG. 24A and a probability change big hit determination table 122 shown in FIG.

  Whether the normal big hit determination table 121 shown in FIG. 24 (A) and the probability variation big hit determination table 122 shown in FIG. 24 (B) use the display result of the special figure game by the variable display device 4 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 121 and 122, a random value R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 122, more random numbers R are associated with the display result of “big hit” than in the normal big hit determination table 121. That is, by determining the display result of the special figure game using the probability change big hit determination table 122, it is possible to achieve a probability improvement state in which the probability of being in the big hit gaming state is higher than in the normal gaming state.

  In this embodiment, in the normal big hit determination table 121 shown in FIG. 24A, among the big hit determination random numbers R “0 to 65535” generated from the random number circuit 17, “2001 to 2184” is “big hit”. Is associated with the display result. On the other hand, in the probability variation jackpot determination table 122 shown in FIG. 24B, among the jackpot determination random numbers R “0 to 65535” generated from the random number circuit 17, “2001 to 3104” is displayed as a “big hit” display result. It is associated.

  In the flag memory 113 shown in FIG. 22, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 113 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a count value round notification flag, a random value read flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (described later) (FIG. 29). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The count value round flag is set to the on state in response to the count value round notification signal being input from the random number circuit 17, and is cleared to the off state when the count value string changing process is executed.
The random value read flag is set to the on state when the count value fetch data “01h” is written in the count value fetch register 75a, and is cleared and turned off when the random value R is read from the random value memory circuit 79. It becomes a state.

  The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The start winning port switch timer memory 114 stores a timer value that is added or cleared in accordance with the start winning signal SS input from the start winning port switch 70.

  The switch circuit 107 shown in FIG. 3 takes in the start winning signal SS from the start winning port switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The start winning opening switch 70 sends a start winning signal (high level signal) SS via the switch circuit 107 based on detecting the winning of a game ball to the normal variable winning ball apparatus 6 which is the starting winning opening. To the CPU 103 and the random number circuit 17.

  The display control board 12 is for performing effect control according to the control command received from the main board 11. Specifically, the display control board 12 performs display control of the variable display device 4 and lighting control of the game effect lamp 9 and the normal symbol display 40.

  The audio control board 13 and the lamp control board 14 are sub-side control boards that execute audio output control and lamp output control independently of the main board 11 based on control commands transmitted from the main board 11. is there. The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  Next, the operation (action) of the pachinko gaming machine 1 in the present embodiment will be described. FIG. 25 is a flowchart showing a game control main process executed by the game control microprocessor 100 mounted on the main board 11. In the main board 11, when power from the power supply board 10 is supplied, the game control microprocessor 100 is activated, and the CPU 103 first executes a game control main process shown in the flowchart of FIG. When the game control main process is started, first, the CPU 103 sets the interrupt prohibition (step S1), and then sets the interrupt mode to mode 2 (step S2).

  Thereafter, the CPU 103 sets a stack pointer designation address in the stack pointer (step S3). Then, register settings such as CTC 105 which is a built-in device of the game control microprocessor 100 are performed (step S4). For example, an interrupt vector is set for the CTC 105.

  Subsequent to the processing in step S4, the CPU 103 checks the backup flag area provided in the RAM 102 (step S5), for example, and backs up all or part of the RAM 102 by a predetermined data protection process when the power is last turned off. It is determined whether or not has been made (step S6). In the pachinko gaming machine 1, when an unexpected power failure occurs, a data protection process for protecting all or a part of the data stored in the RAM 102 is performed. If such data protection processing has been performed, it is determined that there is a backup.

  When it is determined that there is a backup in the process of step S6 (step S6; Yes), the CPU 103 performs a parity check as a check of backup data, and determines whether the check result is normal (step S7). If the check result is normal (step S7; Yes), the internal state of the main board 11 and the control boards on the sub side (display control board 12, voice control board 13, lamp control board 14, and payout control board 15). A game state restoration process for returning the control state to the state at the time of power-off is executed (step S8). Thereafter, the process proceeds to step S10.

  When it is determined that there is no backup in the process of step S7 (step S6; No), or when the check result is not normal in the process of step S7 (step S7; No), the CPU 103 clears the RAM 102 or performs predetermined processing. An initialization process such as initial setting for the work area is performed (step S9).

  Subsequently, the CPU 103 performs a random number circuit setting process (step S10). In this random number circuit setting process, setting is performed for causing the random number circuit 17 to update the value of the random R.

  FIG. 26 is a flowchart showing the random number circuit setting process in step S10. In this random number circuit setting process, the CPU 103 first reads the counter initial value selection data stored in the area 1F98h of the user program execution data area, and based on the read counter initial value selection data, the counter initial value Whether a predetermined value “1” is selected or a value indicating an ID number is selected (step S21).

  When it is determined in step S21 that the predetermined value “1” is selected as the counter initial value (step S21; Yes), the counter initial value setting data “0001h” is written to the counter initial value setting register 73a. Thus, the predetermined value “1” is set in the random number circuit 17 as the counter initial value (step S22). On the other hand, if it is determined that the value indicating the ID number has been selected (step S21; No), the counter initial value setting data indicating the ID number value is written in the counter initial value setting register 73a, thereby obtaining the ID number. Is set in the random number circuit 17 as a counter initial value (step S23).

  Next, the CPU 103 reads the reference clock signal selection data stored in the area 1F96h of the user program execution data area, and based on the read reference clock signal selection data, the system clock signal is obtained as the reference clock signal S0. It is determined whether or not a divided clock signal is selected (step S24).

  If it is determined in step S24 that the system clock signal is selected as the reference clock signal S0 (step S24; Yes), the reference clock signal designation data “01b” is written to the reference clock signal designation register 71a. Thus, the system clock signal is set to be output (step S25). On the other hand, when it is determined that the divided clock signal is selected (step S24; No), the divided clock signal is output by writing the reference clock signal designation data “10b” to the reference clock signal designation register 71a. (Step S26).

  Subsequently, the CPU 103 reads the latch signal selection data stored in the area 1F97h in the user program execution data area, and the start winning signal SS is selected as the latch signal SL based on the read latch signal selection data. Or whether the count value capture signal is selected (step S27).

  When it is determined in step S27 that the start winning signal SS is selected as the latch signal SL (step S27; Yes), the latch signal designation data “01b” is written into the latch signal designation register 77a. Setting is made so that the start winning signal SS is output (step S28). On the other hand, when it is determined that the count value capture signal is selected (step S27; No), the latch signal designation data “10b” is written to the latch signal designation register 77a, thereby outputting the count value capture signal. (Step S29).

  In this embodiment, since the latch signal selection data “01h” is stored in the area 1F97h in the user program execution data area, the latch signal designation data “01b” is stored in the latch signal designation register 77a. "Is written.

  Thereafter, the CPU 103 writes the operation start data “80h” into the operation start register 80a, and starts the operation of the random number circuit 17 (step S30).

  Following the random number circuit setting processing in step S10 shown in FIG. 25, the CPU 103 performs setting for timer interruption by the CTC 105 (step S11). Specifically, the timer mode is set by giving interrupt permission to one of the plurality of channels included in the CTC 105 (specifically, the third channel from the 0th channel to the third channel). And specify the initial count value for the channel. Thereby, thereafter, an interrupt request signal is sent from the CTC 105 to the CPU 103 every predetermined time (for example, 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process.

  Thereafter, the CPU 103 shifts to a loop process for monitoring whether or not a timer interrupt has occurred due to an interrupt request signal from the CTC 105. In this loop process, after setting the interrupt prohibition (step S12), the display random number update process (step S13) is executed, and when the display random number update process is completed, the interrupt permission is set (step S14).

  CPU103 which performed the game control main process shown in FIG. 25 will start execution of the game control interruption process shown in FIG. 27, if the interruption request signal from CTC105 is received and an interruption request | requirement is received.

  When the game control interrupt process is started, the CPU 103 executes a predetermined power-off process, thereby making it possible to execute a predetermined data protection process or the like when the power supplied from the power supply board 10 is reduced (step) S31). Subsequently, the state of the detection signal input from each winning port switch such as the starting winning port switch 70 is determined by executing predetermined switch processing (step S32). In the switch process, it is determined whether or not the start winning signal SS input from the start winning port switch 70 via the switch circuit 107 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the start winning port switch timer memory 114. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Next, the CPU 103 sequentially executes a determination random number update process (step S33) for updating a determination random number such as a random R200 and a display random number update process (step S34) for updating a predetermined display random number. .

  Subsequently, the CPU 103 executes a count value string changing process (step S35).

  FIG. 28 is a flowchart showing the count value string changing process in step S35. In this count value sequence changing process, the CPU 103 first checks the count value round-trip flag provided in the flag memory 113, and so on, to determine whether or not the count value C has been counted up to the counter final value “65535”. Is determined (step S51). When the count value round-trip flag is in the off state (step S51; No), it is determined that the count value C has not been counted up to the final value, and the count value string changing process is ended as it is.

  On the other hand, when the count value round-trip flag is in the ON state (step S51; Yes), the count value C is counted up to the counter final value, and it is determined that the round is complete, and the 1F99h address in the user program execution data area is determined. Read count value sequence change method selection data stored in the area. The CPU 103 determines whether or not to change the count value sequence based on the read count value sequence change method selection data, and when changing the count value sequence, changes according to the first count value change method, Alternatively, it is determined whether to change according to the second count value changing method (steps S52 and S55).

  When the first count value sequence change method selection data “01b” is stored (step S52; Yes), the CPU 103 extracts the random R200 from the random counter 111 (step S53), and sets the extracted random R200 to the value. Based on this, it is determined whether or not to change the order of the count value string (step S54).

  If it is determined in step S54 that the order of the count value sequence is to be changed (step S54; Yes), the process proceeds to step S56. On the other hand, when it is determined that the order of the count value sequence is not changed (step S54; No), the process proceeds to step S57.

  When the second count value sequence change method selection data “10b” is stored (step S55; Yes), the count value sequence change data “01h” is written to the count value sequence change register 74a, and the order of the count value sequence Is changed (step S56).

  On the other hand, if it is determined No in the processes of steps S52 and S55, the CPU 103 determines that the count value sequence change method selection data stored in the area of the program execution data area at address 1F99h is “00b”. Then, the process proceeds to step S57 as it is without changing the order of the count value string.

  Thereafter, the CPU 103 clears the count value round flag to turn it off (step S57), and ends the count value string changing process.

  After the initial value changing process is completed in this way, the CPU 103 executes a special symbol process process (step S36). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 103 executes normal symbol process processing (step S37). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the normal symbol display 40 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the special symbol command control process (step S38) and the normal symbol command control process (step S39) are sequentially executed. Thus, the CPU 103 sends a display control command from the main board 11 to the display control board 12 to instruct display control of the variable display device 4 and lighting control of the normal symbol display 40.

  Subsequently, the CPU 103 executes predetermined information output processing to output various output data to each output port included in the I / O port 104 (step S40). In this information output process, a command for outputting jackpot information, starting information, probability variable information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  In addition, the CPU 103 executes predetermined prize ball processing to set the number of prize balls based on the detection signal input from each prize opening switch such as the start prize opening switch 70 and the like, and to the payout control board 15 The payout control command can be output (step S41). Further, the CPU 103 performs predetermined solenoid output processing to open and close the movable blade piece in the normal variable winning ball device 6 and the opening / closing plate in the special variable winning ball device 7 when a predetermined condition is satisfied ( Step S42).

  FIG. 29 is a flowchart showing the special symbol process executed in step S36. When the special symbol process is started, the CPU 103 first checks whether or not the game ball has won the normal variable winning ball device 6 by checking the timer value stored in the start winning port switch timer memory 114. It discriminate | determines (step S101). In the process of step S101, the CPU 103 loads the timer value stored in the start winning a prize opening switch timer memory 114, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). As a result, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is performed a predetermined number of times (for example, twice) (for example, 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S101; Yes), the winning process is executed (step S102), and the timer value is set. clear. On the other hand, when the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S103; No), and the winning process is skipped.

  FIG. 30 is a flowchart showing the winning process in step S103. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S121). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S121; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memorization number is less than “4” (step S121; No), the output control signal SC is sent to the random value memory circuit 79, and the random value memory circuit 79 is controlled to be readable (enabled). (Step S122).

  Subsequently, the CPU 103 reads the random value R from the random value storage circuit 79 (step S123), stores the read random value R in a predetermined buffer area provided in the RAM 102, for example (step S124), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 79 is stopped, and the random number value storage circuit 79 is controlled to be unreadable (disabled) (step S125). Then, the CPU 103 adds “1” to the starting winning memory number (step S126), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S127).

  Subsequently, based on the value of the special symbol process flag stored in the flag memory 113, the CPU 103 selects one of nine processes of steps S110 to S118 shown in FIG. Below, each process of step S110-S118 is demonstrated.

  The special symbol normal process of step S110 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0”. Here, in the special figure holding memory 110, when various data such as the random number R corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S111 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 31, the CPU 103 first reads the random number value R stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S141). At this time, “1” is subtracted from the reserved storage number, and the random number R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is increased by one entry. (Step S142).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S143). If the probability change is not in progress (step S143; No), the CPU 103 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal time big hit determination table 121 as shown in FIG. 24A is set (step S144). On the other hand, if the probability change is in progress (step S143; Yes), the probability change big hit determination table 122 as shown in FIG. 24B is set (step S145).

  Based on the random number value R read out in step S141, the CPU 103 determines whether or not to display the special game display result as a big hit using the big hit determination table 121 or 122 set in step S144 or S145. (Step S146). If it is determined to be a big hit (step S146; Yes), the big hit state flag provided in the flag memory 113 is set to the on state (step S147), and if it is determined to be lost. (Step S146; No), the big hit state flag is cleared and turned off (Step S148). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S149).

  The confirmed symbol determination process in step S112 shown in FIG. 29 is a process executed when the value of the special symbol process flag is “2”. In this processing, the CPU 103 determines whether or not the big hit state flag provided in the flag memory 113 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S113 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 first determines whether or not the big hit state flag provided in the flag memory 113 is turned on, and whether or not it is determined to reach in the determined symbol determination process in step S112. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in the current special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 103 updates the value of the special symbol process flag to “4” which is a value corresponding to the variable display command process.

  The variable display command process of step S114 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 103 controls the variable display device 4 to start variable display for all the special symbols. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S112 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S113 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S115 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 makes settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be able to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S116 is a process executed when the value of the special symbol process flag is “6”. In this processing, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S117 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S118 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the display control board 12. Further, the CPU 103 clears the big hit state flag provided in the flag memory 113 and sets it to the off state. Then, the value of the special symbol process flag is updated to “0”.

  As described above, according to this embodiment, the counter 73 counts at the timings T10, T12, T14,... In response to the rising edge of the reference clock signal S0 input from the first selector 71. The value C is updated, and the latch signal output circuit 78 synchronizes the start winning signal SS input from the start winning port switch 70 with the falling edge of the reference clock signal S0 at timings T11, T13, T15,. The latch signal SL is output to the random value storage circuit 79. The random value storage circuit 79 stores the updated count value C as the random value R in response to the rising edge of the latch signal SL.

  Therefore, the random number circuit 17 can reliably change the update timing of the count value C by the counter 73 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 78. As a result, the pachinko machine The gaming machine 1 can reliably and stably acquire a random value.

  Further, the CPU 103 performs the random number circuit setting process after the power is supplied to the pachinko gaming machine 1 and the game control main process is started and before the execution of the timer interrupt process is permitted and the process proceeds to the loop process. It is not necessary to start and end the process for generating random numbers within a limited interrupt processing time (for example, 2 milliseconds), and an increase in the processing load on the game control microprocessor 100 can be prevented. Further, since the random number circuit 17 is built in the game control microprocessor 100 together with the CPU 103, a space for the main board 11 can be secured, and counterfeiting such as installation of an unauthorized board can be made difficult.

  Preferably, the random number circuit setting process permits the timer interrupt process to be executed after the game state restoration process is executed or after initialization processing such as clearing the RAM 102 or initial setting for a predetermined work area. It is desirable to be executed before the loop process is entered.

  Further, since the CPU 103 determines whether or not the display result in the special game is a big hit using the random R value generated by the random number circuit 17, the capacity of the program stored in the ROM 101 or the like can be reduced. .

  Furthermore, since the value of the random R is updated by the random number circuit 17, the capacity of the program stored in the ROM 101 or the like can be reduced as compared with that updated by software.

  In addition, since the value of the random R stored in the random value storage circuit 79 can be updated according to the setting made by the random number circuit setting process, the random value can be changed by performing different settings for each pachinko gaming machine 1. The randomness of the random number value read from the storage circuit 79 and used to determine whether or not the display result in the special figure game is a big hit can be improved.

  More specifically, the CPU 103 sets the counter initial value appropriately selected by the user for each pachinko gaming machine 1 and the clock signal used as the reference clock signal S0 in the random number circuit 17, and then starts the operation of the random number circuit 17. Thereby, the random number circuit 17 updates the value of the random R stored in the random value storage circuit 79 based on the counter initial value set by the CPU 103 and the clock signal set as the reference clock signal S0. The randomness of the random number value read from the random value storage circuit 79 and used for determining whether or not the display result in the special figure game is a big hit can be improved.

  Furthermore, by changing the order of the count value sequence, the randomness of the count value input to the random value storage circuit 79 is increased. As a result, the random number value storage circuit 79 reads out the display result in the special game. It is possible to improve the randomness of the random number value used for determining whether or not to win.

  In response to the count value sequence change circuit 74 receiving a request to change the order of the count value sequence from the CPU 103, the CPU 103 counts the count value sequence change register in which the count value sequence change data “01h” is written. Since 74a is initialized, it is possible to prevent a problem that the count value sequence supplied from the count value sequence change circuit 74 to the random value storage circuit 79 is continuously changed.

  Further, after the count value sequence change register 74a is initialized, the CPU 103 rewrites the count value sequence change data “01h” in the count value sequence change register 74a to further change the order of the changed count value sequence. be able to.

  Further, until the system is reset by the reset controller 109, the CPU 103 cannot write the reference clock signal specifying register 71a in which the clock signal setting data is written and the counter initial value setting register 73a in which the counter initial value setting data is written. Thus, the counter initial value set in the random number circuit 17 and the clock signal used as the reference clock signal S0 are made unchangeable. As a result, the malicious player can freely set the timing at which the initial value of the counter or the random R value read from the random value storage circuit 79 by changing the reference clock signal S0 and the jackpot determination value coincide with each other. It is possible to prevent illegal acts such as frequent occurrences.

  Further, the CPU 103 sets the counter initial value in the random number circuit 17, designates the clock signal and the latch signal, and then starts the random number circuit 17, so that after the power supply is started, the counter initial value and the reference clock signal S0 are set. It is possible to prevent a problem that a random number is generated from the random number circuit 17 before setting a clock signal to be used.

  Further, when the system is reset by the reset controller 109, the random number circuit 17 can be activated again by writing the operation start data “80h” in the operation start register 80a.

  When the CPU 103 detects that the start winning signal SS is continuously input from the start winning port switch 70 for a predetermined number of times (for example, twice) (for example, 4 ms), the winning combination signal SS is detected. Execute the process.

  In this winning process, the CPU 103 sends an output control signal SC to the random value storage circuit 79 to control the random value storage circuit 79 to a readable state (enable), and then reads the random value R from the random value storage circuit 79. . Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 79 and controls the random value storage circuit 79 to the unreadable (disabled) state, and then the read random value R becomes the predetermined determination value “ It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state by determining whether or not it matches with “2001 to 2184” or the like.

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 79 to the readable state only when the CPU 103 reads the random number value R. Can do. Further, since the CPU 103 reads the random value R from the random value storage circuit 79 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  The random number circuit 17 does not directly input the start prize signal SS output from the start prize port switch 70 to the latch signal output circuit 78 but temporarily inputs it to the timer circuit 76 to input the start prize signal SS. When the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 78. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 78 from erroneously outputting the latch signal SL to the random value storage circuit 79 due to the influence of noise or the like. Since the timer circuit 76 is set to “3 ms” shorter than “4 ms” between the executions of the two timer interrupt processes, the random number value R read from the random number value storage circuit 79 by the CPU 103 is the previous value. It is possible to prevent the same value as the random value R read at the time of winning a prize.

  When the latch signal SL is input from the latch signal output circuit 78, the random value storage circuit 79 converts the output control signal (high level signal) SC input from the game control microcomputer 100 to a low level signal. By converting to, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R from the random value storage circuit 79 when the random value R stored in the random value storage circuit 79 is updated. 1 can reliably and stably update the random value R.

  Further, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 79 converts the latch signal (high level signal) SL input from the latch signal output circuit 78 to a low level signal. By converting to, the latch signal SL is controlled so as not to be received. This prevents the random number value R stored in the random value storage circuit 79 from being updated when the game control microcomputer 100 reads the random value R from the random value storage circuit 79. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above-described embodiment, the start winning port switch 70 detects the winning of a game ball or the like to the ordinary variable winning ball apparatus 6 that is the start winning port, and the start winning signal SS and the random number circuit. The random number circuit 17 measures the time when the start winning signal SS is input from the start winning port switch 70 in the timer circuit 76, and the measured time is set to a predetermined time (for example, 3 ms). At this time, the start winning signal SS was output to the latch signal output circuit 78.

  However, the present invention is not limited to this, and the start winning port switch 70 may output the start winning signal SS only to the main board 11. In this case, the latch signal selection data “02h” is stored in the area 1F97h in the user program execution data area, and the latch signal designation data “10b” is written in the latch signal designation register 77a. The CPU 103 mounted on the main board 11 continues the start winning signal SS from the start winning port switch 70 while the timer interrupt process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). The count value take-in data “01h” is written in the count value take-in register 75a.

  A gaming machine according to such a modification will be described below with reference to the drawings. FIG. 32 is a timing chart for explaining the operation (action) of the random number circuit 17 according to the modification.

  As shown in FIG. 32A, the first selector 71 outputs, for example, a reference clock signal S0 that rises from a low level to a high level at timings T10, T12, T14,. To do.

  As shown in FIG. 32B, the counter 73 updates the count value C each time the rising edge of the reference clock signal S0 input from the first selector 71 is input, and stores it in the random value storage circuit 79. Output. The latch signal output circuit 78 synchronizes the count value fetch signal shown in FIG. 32C input from the input terminal D with the falling edge of the reference clock signal S0 input from the first selector 71. The latch signal SL shown in 32 (D) is output.

  As a result, the random number circuit 17 rises at the rising timing T10, T12, T14,... Among the rising timing from the low level to the high level and the falling timing from the high level to the low level, which the reference clock signal S0 periodically repeats. , The count value C is updated, and the latch signal SL can be output at the falling timings T11, T13, T15.

  Then, the random value storage circuit 79 uses the count value C input from the counter 73 to the input terminal D as the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 78 to the clock terminal CK. In response, the random number value R is latched and stored, thereby updating the stored random number value R as shown in FIG.

  In this way, the random number circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In this modified example, the flag memory 113 shown in FIG. 22 is provided with a random value read flag in addition to the above-described flags. This random number read flag is set to ON when the count value fetch data “01h” is written to the count value fetch register 75a, and is cleared when the random value R is read from the random value storage circuit 79. Turns off.

  FIG. 33 is a flowchart showing the special symbol process executed in step S36 in this modification. When the special symbol process is started, the CPU 103 first determines whether or not the random number read flag provided in the flag memory 113 is on (step S201).

  When the random number read flag is off (step S201; No), the timer value stored in the start winning opening switch timer memory 114 is checked to determine whether or not the game ball has won the normal variable winning ball device 6. Thus, the determination is made (step S202). In the process of step S202, the CPU 103 loads the timer value stored in the starting winning a prize opening switch timer memory 114, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). Thereby, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won (step S202; Yes), and a winning process is executed (step S203). clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S202; No), and the winning process is skipped.

  FIG. 34 is a flowchart showing the winning process in step S203. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S221). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S221; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memorized number is less than “4” (step S221; No), the count value fetch data “01h” is written into the count value fetch register 75a and the count value fetch circuit 75 takes the count value fetch. The output signal is output (step S222). Thereafter, the CPU 103 sets the random number read flag to the on state (step S223).

  If the random value read flag is on in the process of step S201 (step S201; Yes), the random value read process is executed (step S204).

  FIG. 35 is a flowchart showing the random number value reading process in step S204. In this random value reading process, the CPU 103 first sends an output control signal SC to the random value storage circuit 79 to control the random value storage circuit 79 to a readable (enable) state (step S231). Subsequently, the CPU 103 reads the random value R from the random value storage circuit 79 (step S232), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S233), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 79 is stopped, and the random number value storage circuit 79 is controlled to an unreadable (disabled) state (step S234).

  Then, the CPU 103 adds “1” to the starting winning memory number (step S235), and sets the random number value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S236). Thereafter, the CPU 103 clears the random number read flag and turns it off (step S237).

  As described above, according to this modification, the counter 73 counts at the timings T10, T12, T14,... At which the reference clock signal S0 input from the first selector 71 rises from the low level to the high level. The value C is updated sequentially.

  Then, when a game ball wins the normal variable winning ball apparatus 6 which is a starting winning port, the starting winning port switch 70 sends a starting winning signal SS only to the main board 11. The CPU 103 of the main board 11 continuously inputs the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Based on this, it is determined that the game ball has won the normal variable winning ball apparatus 6, and the count value fetching data “01h” is written into the count value fetching register 75a. To send a signal.

  The count value acquisition signal output from the count value acquisition circuit 75 is input to the input terminal D of the latch signal output circuit 78. The latch signal output circuit 78 uses the count value fetch signal input to the input terminal D as the reference clock signal S0 input from the first selector 71 to the clock terminal CK falls from the high level to the low level. At timings T11, T13, T15,..., The latch signal SL is output from the output terminal Q.

  The random value storage circuit 79 responds to the count value C input from the counter 73 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 78 to the clock terminal CK. And latched and stored as a random value R.

  Thereafter, in the first timer interruption process, the CPU 103 reads the random value R from the random value storage circuit 79, and whether or not the read random number R matches a predetermined determination value “2001 to 2184” or the like. It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state.

  In this way, the random number circuit 17 can reliably change the update timing of the count value C by the counter 73 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 78. As a result, The pachinko gaming machine 1 can reliably and stably acquire the random value R.

  When the CPU 103 determines that the game ball has won the normal variable winning ball device 6, the CPU 103 writes the count value take-in data “01h” in the count value take-in register 75a, so that the pachinko gaming machine 1 It is not necessary to provide a path for supplying the start winning signal SS from the mouth switch 70 to the random number circuit 17, and the hardware configuration can be simplified.

  Further, the CPU 103 determines that the game ball has won the normal variable winning ball device 6 based on the continuous input of the start winning signal SS while the two timer interruption processes are being executed. Therefore, the pachinko gaming machine 1 can prevent the count value fetch data “01h” from being erroneously written in the count value fetch register 75a due to the influence of noise or the like.

  In addition, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 reads the random value R from the random value storage circuit 79 in the first timer interruption process. It is possible to prevent the read random value R from being the same as the previously read random value R.

  Further, in the configuration in which the random number circuit 17 and the start winning port switch 70 are connected as in the above embodiment, the start winning signal SS input from the start winning port switch 70 to the random number circuit 17 is used as the latch clock. A latch signal SL is output in synchronization with the signal S2. On the other hand, in the configuration in which the random number circuit 17 and the start prize opening switch 70 are not connected as in the above modification, the count value fetch data “01h” is written in the count value fetch register 75a, and the count value fetch circuit A count value take-in signal is output from 75, and the count value take-in signal is synchronized with the latch clock signal S2 to output a latch signal SL.

  In this way, depending on the configuration of the pachinko gaming machine 1, the user outputs the latch signal SL in synchronization with the start winning signal SS in synchronization with the latch clock signal S2, or the count value fetch signal is used as the latch clock. Whether to output the latch signal SL in synchronization with the signal S2 can be selected. For this reason, it can respond to the game machine of various structures.

  In the above embodiment, the random R value read from the random value storage circuit 79 is used as a big hit determination random number for determining whether or not the pachinko gaming machine 1 is put into the big hit gaming state by generating a big hit. It was described as being used. However, the present invention is not limited to this, and the read random R value is arbitrarily used, and reach determination random numbers, special symbols, and decorations for determining whether or not to reach when lost. Random number for display to determine the variable display pattern used for variable display of the symbol, Random number for display to determine the fixed symbol of the special symbol at the time of big hit, To determine the fixed symbol of the special symbol at the time of loss Random numbers for display, random numbers for probability variation determination for determining whether or not a high probability state (special game state) in which the probability of generating a big hit is improved, and display results in a normal diagram game by the normal symbol display 40 It may be used as a random number for determining per normal drawing for determining whether or not to win.

  Further, a plurality of random number circuits 17 are incorporated in the game control microprocessor 100, and a random number generated from one of the plurality of random number circuits 17 is used, for example, for determining the jackpot of a special figure game and generated from the other random number circuits 17. The random number to be used may be used for hit determination of the normal game. In this way, it is possible to reduce the processing burden on the gaming control microprocessor 100 or higher in the above embodiment.

  Conversely, it is not necessary to update all of the random numbers listed here using the random number circuit 17, and some random numbers may be updated without using the random number circuit 17. For example, a part of these random numbers may be updated by executing a predetermined program during the game control interrupt process, or a random number update method using a refresh register may be used in combination. Good. Furthermore, the value of the random R read from the random value storage circuit 79, the value of the random number updated by executing a predetermined program during the game control interrupt process, and / or the value of the random number updated using the refresh register, , May be used as a random number for determining jackpot, reach, variable pattern, etc.

  In the above embodiment, in the game control main process, the CPU 103 uses the random number circuit after setting the timer interrupt by the CTC 105 in step S11 after the game state restoration process in step S8 or the initialization process in S9. Although the setting process has been executed, the present invention is not limited to this, and is optional as long as the power supply is started and before the transition to the loop process. For example, the interrupt is prohibited in step S1. It may be performed immediately after setting, or may be performed immediately after setting the interrupt mode to mode 2 in step S2. Further, immediately after setting the stack pointer designation address to the stack pointer in step S3, immediately after setting a register such as CTC 105 in step S4, or immediately after setting for timer interrupt in step S11. Good.

  In the above embodiment, the counter 73 updates the count value C in response to the rising edge of the reference clock signal S0 input from the first selector 71, and the latch signal output circuit 78 has the start winning a prize opening switch 70. Is received as a latch signal SL in synchronization with the falling edge of the reference clock signal S0. However, the present invention is not limited to this, and the counter 73 updates the count value C in response to the falling edge of the reference clock signal S0, and the latch signal output circuit 78 detects the start winning signal SS. May be output as the latch signal SL in synchronization with the falling edge of the reference clock signal S0.

  Furthermore, in the above-described embodiment, the counter 73 is an up counter, but the present invention is not limited to this, and may be a down counter. Further, the numerical value updating means is not limited to the counter 73, and may be a pseudo random number generation circuit. In addition, the connection between the output terminal of the bit data C0 to C15 of the count value C of the counter 73 and the input terminal of the bit data C0 to C15 of the count value C of the random number storage circuit 79 may be changed. Then, the randomness of the count value C input to the random value storage circuit 79 can be improved.

  In the above embodiment, the random value storage circuit 79 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 230 to 245 to control the reception of the latch signal SL and the output control signal SC and to output the random value R. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 79 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 104 and the latch signal output circuit 78, and the latch signal SL. In response to the input of the output control signal SC, the path to the I / O port 104 and the latch signal output circuit 78 is turned on and off to enable / disable the latch signal SL and the output control signal SC. Also good.

  Further, in the above embodiment, the timer circuit 76 is activated in response to the input of the high level signal, and the reference clock signal S0 from the first selector 71 while the input is at the high level. In response to the input, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, the input signal is determined to be a high level signal and latched. The signal is output to the signal output circuit 78. However, the present invention is not limited to this, and the timer circuit 76 measures the time during which the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. Any signal may be used as long as it outputs the winning signal SS to the latch signal output circuit 78.

  In the above embodiment, the timer circuit 76 measures the signal input time using the reference clock signal S0. However, the present invention is not limited to this, and the timer circuit 76 uses the reference clock signal S0. Or a clock signal output from a clock signal output circuit different from the first selector 71 may be used. In the above embodiment, the timer circuit 76 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, but from the 4 ms which is the execution time of the two timer interrupt processes. Any time can be set as long as the time is short.

  Further, in the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 76 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  Further, in the above-described embodiment, the gaming machine can perform the variable display start condition (for example, the previous variable display and the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball device 6)). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the end of the big hit gaming state is established, This is a pachinko gaming machine that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the result is a predetermined specific display result.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, a big prize opening) from a disadvantageous state (for example, a closed state) to a player (for example, a closed state) Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 36, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 36 serves as a start winning signal output means of the present invention by sending a predetermined start signal based on the operation of the start lever 1011 by the player, a game control CPU (for example, main board) or a random number circuit. A start switch (not shown) for outputting to (for example, a random number circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 36 functions as rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  1, 2, and 36, the block configuration shown in FIGS. 3, 4, and 22, the register configuration shown in FIGS. 5 to 7, 9, and 14, and FIG. 6, FIG. 10 and FIG. 18 to FIG. 21 data structure, FIG. 8 and FIG. 24 table structure, FIG. 13, FIG. 15 and FIG. 32 timing chart structure, and FIG. The flowchart configurations shown in FIGS. 33 to 35 can be arbitrarily changed and modified without departing from the spirit of the invention.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Further, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. FIG. 4 is a block diagram illustrating a configuration example of a random number circuit illustrated in FIG. 3. (A) is a figure which shows the structural example of a reference | standard clock signal designation | designated register, (B) is explanatory drawing of reference | standard clock signal designation | designated data. FIG. 5 is a diagram illustrating a configuration example of a counter initial value setting register illustrated in FIG. 4. FIG. 5 is a diagram illustrating a configuration example of a count value string change register illustrated in FIG. 4. It is a figure which shows the structural example of the table for bit scramble pattern determination. FIG. 5 is a diagram illustrating a configuration example of a count value fetch register illustrated in FIG. 4. It is explanatory drawing of latch signal designation | designated data. FIG. 5 is a circuit diagram illustrating a configuration example of a random value storage circuit illustrated in FIG. 4. It is a figure for demonstrating the connection of the output terminal of the OR circuit of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random value storage circuit. FIG. 5 is a diagram illustrating a configuration example of an operation start register illustrated in FIG. 4. It is a timing chart for demonstrating operation | movement of a random number circuit. It is a figure which shows an example of the address map in the microprocessor for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing of reference clock signal selection data. It is explanatory drawing of latch signal selection data. It is explanatory drawing of counter initial value selection data. It is explanatory drawing of count value sequence change system selection data. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the counter value sequence change determination random number counted by a random counter. It is a figure which shows the structural example of the table for jackpot determination. It is a flowchart which shows a game control main process. It is a flowchart which shows the random number circuit setting process in FIG. It is a flowchart which shows a game control interruption process. It is a flowchart which shows the count value sequence change process in FIG. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a timing chart for demonstrating operation | movement of the random number circuit in a modification. It is a flowchart which shows the modification of the special symbol process process shown in FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the random value reading process in FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Variable display device
6 ... Ordinary variable winning ball device
7 ... Special variable winning ball device 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board
17 ... Random number circuit 21, 22 ... Solenoid
40 ... Normal symbol display
70… Start prize opening switch
71 ... 1st selector
71a ... Reference clock signal designation register
73 ... Counter
73a ... Counter initial value setting register
74 ... Count value string changing circuit
74a ... Count value string change register
74b ... Bit scramble pattern selection circuit
74c ... Bit scramble circuit
74d ... Bit scramble pattern determination table
75 ... Count value acquisition circuit
75a ... Count value capture register
76… Timer circuit
77 ... Second selector
77a ... Latch signal designation register
78 ... Latch signal output circuit
79 ... Random value storage circuit
80 ... Operation start circuit
80a ... Operation start register 100 ... Game control microprocessor 101 ... ROM
102 ... RAM
103 ... CPU
104 ... I / O port 105 ... CTC
106 ... Clock circuit 107 ... Switch circuit 108 ... Solenoid circuit 109 ... Reset controller 110 ... Special figure holding memory 111 ... Random counter 112 ... Big hit judgment table memory 113 ... Flag memory 114 ... Start winning prize switch timer memory 121 ... Normal big hit Judgment table 122 ... jackpot judgment table 201, 203 ... AND circuit 202, 204 ... NOT circuit 210-225 ... Philip flop circuit 230-245 ... OR circuit 1000 ... slot machine 1001 ... liquid crystal display 1002 ... variable display device 1011 ... Start lever

Claims (6)

A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A game control microprocessor incorporating a random number circuit for generating random numbers and a game control CPU for controlling the progress of the game, and operating using the power supplied from the power supply means;
Start signal output means for outputting a start signal to the random number circuit and the game control CPU based on the establishment of the execution condition;
With
The random number circuit includes:
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
Numerical data update for updating numerical data in response to a change in the first aspect among the changes in a plurality of aspects in which the reference clock signal input from the reference clock signal output means repeats every predetermined period Means,
The start signal input from the start signal output means is output as a latch signal in synchronization with the change in the second mode different from the change in the first mode among the changes in the plurality of modes. Latch signal output means,
Random value storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
The game control CPU is:
Random number circuit setting means for setting the random number circuit to generate the random number before setting interrupt processing to be executed periodically after the start of power supply by the power supply means;
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and then the read random number value is determined based on the establishment of the start condition. Display result determination means for determining whether or not the display result in the variable display is a specific display result by determining whether or not the value data matches.
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random value storage means includes output control signal reception control means for maintaining an unreadable state even when an output control signal is outputted from the read control means when a latch signal is inputted from the latch signal output means,
A gaming machine characterized by that. A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A game control microprocessor incorporating a random number circuit for generating random numbers and a game control CPU for controlling the progress of the game, and operating using the power supplied from the power supply means;
Start signal output means for outputting a start signal to the game control CPU based on the establishment of the execution condition;
With
The game control CPU is:
Trigger signal output means for outputting a predetermined trigger signal to the random number circuit based on the input of the start signal from the start signal output means;
Display result determining means for determining whether or not the display result in the variable display is a specific display result;
Including
The random number circuit includes:
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
Numerical data update for updating numerical data in response to a change in the first aspect among the changes in a plurality of aspects in which the reference clock signal input from the reference clock signal output means repeats every predetermined period Means,
The trigger signal output by the trigger signal output means is output as a latch signal in synchronization with the change in the second mode different from the change in the first mode among the changes in the plurality of modes. Latch signal output means,
Random value storage means for storing numerical data updated by the numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
The display result determining means reads a random value from the random value storage means based on the input of a start signal from the start signal output means, and then reads the random number value based on the start condition being satisfied. Determining whether or not the random number value matches the predetermined determination value data, thereby determining whether or not the display result in the variable display is the specific display result,
The game control CPU after starting supply of power by said power supply means, before setting the interrupt process performed periodically, a random number circuit setting means for setting for generating the random number to the random number circuit ,
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means, and then stops the output of the output control signal to the random value storage means and controls the random value storage means to the unreadable state;
Only including,
The random value storage means includes output control signal reception control means for maintaining an unreadable state even when an output control signal is outputted from the read control means when a latch signal is inputted from the latch signal output means,
A gaming machine characterized by that. The random number circuit setting means is a reference for selecting any one of two types of clock signals as the reference clock signal after the start of power supply by the power supply means and before interrupt processing periodically executed. A clock signal selection means;
Signal designation data setting means for setting signal designation data for designating the signal selected by the reference clock signal selection means in the random number circuit;
The random number circuit includes a selector that sets the signal designation data by the signal designation data setting means,
The selector outputs a signal indicated by the signal designation data set by the signal designation data setting means as the reference clock signal;
The gaming machine according to claim 1 or 2, characterized in that. The numerical data updating means cyclically updates the numerical data from a predetermined initial value to a predetermined final value,
The random number circuit setting means includes a predetermined value and a value indicated by an identification number unique to the game control microprocessor before the setting of interrupt processing to be executed periodically after the power supply means starts supplying power. Including an initial value setting means for setting the value selected from among the numerical data updating means as the predetermined initial value,
The gaming machine according to claim 1, 2, or 3. Numeric data string change means for requesting change of the permutation, which is the update order of the numerical data supplied from the numerical data update means to the random value storage means,
The random number circuit includes a numerical permutation changing unit that, when requested to change the numerical data sequence by the numerical data sequence changing unit, changes to a permutation having an update order different from that when the change of the numerical data sequence is not requested.
The gaming machine according to any one of claims 1 to 4, characterized in that: The gaming control microprocessor includes a plurality of the random number circuits,
The game control CPU uses a random number generated from any one of a plurality of random number circuits built in the game control microprocessor for determining the display result by the display result determining means. The random number generated from the other random number circuit is used for determination different from the determination of the display result.
The gaming machine according to any one of claims 1 to 5, characterized in that:

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