JP4056495B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  Currently, in game machines, a random number used to determine whether or not to make a “big hit” (a big hit determination random number) is generated by the CPU executing a predetermined application program. However, such a random number generation method has a problem that the processing load on the CPU at the time of generation increases.

To solve this problem, a random number circuit is used to generate a big hit determination random number, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. A gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 1).
JP-A-7-124296 (page 3-4, FIG. 1).

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). A gaming machine that stores random numbers is also disclosed (for example, see Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2).

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  In the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gradual, the rising edge of the inverted clock pulse also becomes gradual. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse is output. There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reliably and stably obtaining a random value.

In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (for example, a pachinko gaming machine 1) that has a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result, Game control means for controlling (for example, a game control microcomputer 100 mounted on the main board 11) and random number generating means for generating random numbers (for example, random R) (for example, random number generation) And a starting signal output means (for example, a start winning switch 70) for outputting a starting signal (for example, a starting winning signal SS) to the game control means and the random number generating means on the basis of the execution condition being satisfied. The random number generating means includes a reference clock signal output means (for example, a reference clock signal output circuit 171) for outputting a reference clock signal (for example, a reference clock signal S0) having a predetermined period, and the reference clock signal. And a clock signal generating means (for example, a clock signal generating circuit 172) for generating a first clock signal (for example, a counting clock signal S1) and a second clock signal (for example, a counting signal S2 for latch ), said clock signal generating means, as said first clock signal, the reference clock signal is the predetermined cycle-to-cycle (Timing T10 e.g. the reference clock signal S0 rises from the low level to the high level, T11, T12, ..., etc.) timing changes in synchronization with a first output terminal (for example, a clock for outputting a signal signal state changes a positive-phase output terminal Q) of the signal generating circuit 172, the second as a clock signal, the first of the second output terminal (for example, a clock signal the clock signal and the period for outputting a phase difference of 180 degrees signal at the same And the random number generating means has a first timing (for example, a clock signal for counting) at which the signal state in the first clock signal changes in a predetermined manner. Numerical data output at a timing T10, T12, T14, etc. at which S1 rises from a low level to a high level Numerical data updating means for updating the value (e.g., counter 173), from said second second timing (e.g., latch clock signal S2 is at a low level of the signal state at the clock signal varies in the predetermined manner the same manner Latch signal output means (for example, a latch signal output circuit) that outputs a start signal input from the start signal output means as a latch signal (for example, latch signal SL) at the timing T11, T13, T15,. 174) and a random value storage means (for example, a random value storage circuit) that stores the output value of the numerical data updated by the numerical data update means as a random value in response to the latch signal input from the latch signal output means 175), and the game control means receives a start signal from the start signal output means. Based on the input, the random number value is read from the random number value storage means, and whether the read random number value matches predetermined determination value data (for example, “2001 to 2184”, “2001 to 3104”, etc.) Display result determining means for determining whether or not the display result in the variable display is to be a specific display result by determining whether or not (for example, the part in which the CPU 103 executes a winning process in step S102 and a jackpot determining process in step S111) ), And before the display result determining means reads the random value from the random value storage means, an output control signal (for example, the output control signal SC) can be output to the random value storage means to read the random value storage means. After the display result determining means reads the random value from the random value storage means, the output of the output control signal to the random value storage means is stopped. Read control means for controlling the random number value storage means to be in an unreadable state (for example, the portion where the CPU 103 executes the processing of steps S122 and S125 and the processing of steps S231 and S234), and the random value storage means includes the latch signal It further includes latch priority means (for example, an AND circuit 203) that maintains an unreadable state even when an output control signal is outputted from the read control means when a latch signal is inputted from the output means .

The gaming machine according to claim 2, the variable display execution condition (e.g., common variable winning ball device prize to 6) of the variable display of the variable display and the jackpot gaming start condition (e.g. the last in the variable display device 4 after the establishment of A variable display device (for example, variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of (end of state). A gaming machine (for example, a pachinko gaming machine 1) having a specific gaming state (for example, a big hit gaming state) advantageous to the player when a specific display result is obtained, and a game control means (for example, a main board) for controlling the progress of the game 11, a game control microcomputer 100), random number generation means (for example, random number generation circuit 17) for generating a random number (for example, random R), and the execution condition And a starting signal output means (for example, a starting winning switch 70) for outputting a starting signal (for example, a starting winning signal SS) to the game control means and the random number generating means based on the establishment, the random number generating means Includes a reference clock signal output means (for example, a reference clock signal output circuit 171) for outputting a reference clock signal (for example, a reference clock signal S0) having a predetermined period, and a first clock signal (for example, a count) based on the reference clock signal. Clock signal generation means (for example, clock signal generation circuit 172) that generates a second clock signal (for example, a latch count signal S2), and the clock signal generation means includes the first clock signal S1) and the second clock signal (for example, the latch count signal S2). As the clock signal, the timing at which the reference clock signal changes at every predetermined period (for example, the base clock signal) A first output terminal (for example, a positive signal of the clock signal generation circuit 172) that outputs a signal whose signal state changes in synchronization with timings T10, T11, T12,..., When the clock signal S0 rises from a low level to a high level. Phase output terminal Q) and a second output terminal (for example, a reverse phase of the clock signal generation circuit 172) that outputs a signal having the same cycle as that of the first clock signal and a phase different by 180 degrees as the second clock signal. Output terminal Q (bar)), and the random number generating means has a first timing at which the signal state of the first clock signal changes in a predetermined manner (for example, the count clock signal S1 is changed from low level to high level). Numerical data update means for updating the output value of numerical data at the timing T10, T12, T14,. (For example, the counter 173) and the second timing when the signal state in the second clock signal changes in the same manner as the predetermined mode (for example, the timing T11 when the latch clock signal S2 rises from the low level to the high level) T13, T15,...) And the like, latch signal output means (for example, latch signal output circuit 174) that outputs the start signal input from the start signal output means as a latch signal (for example, latch signal SL), and the latch signal output Random number storage means (for example, random value storage circuit 175) for storing an output value of the numerical data updated by the numerical data update means as a random value in response to a latch signal input from the means, The game control means, based on the input of the start signal from the start signal output means, The random number value is read from the numerical value storage means, and it is determined whether the read random number value matches predetermined determination value data (for example, “2001 to 2184”, “2001 to 3104”, etc.). Display result determining means for determining whether or not the display result in the display is a specific display result (for example, a portion where the CPU 103 executes a winning process in step S102 and a jackpot determining process in step S111), and the display result determining means Before reading a random value from the random value storage means, an output control signal (for example, an output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Reads out the random number value from the random value storage means and then stops outputting the output control signal to the random value storage means and makes the random value storage means unreadable. Read control means for controlling (for example, the part where the CPU 103 executes the processes of steps S122 and S125 and the processes of steps S231 and S234), and the random value storage means receives an output control signal from the read control means Read priority means (for example, an AND circuit 201) that prohibits updating of the stored random number value even when a latch signal is output from the latch signal output means .

4. The gaming machine according to claim 3 , wherein the clock signal generation means is connected to a clock terminal (for example, a clock terminal CK of the clock signal generation circuit 172) to which the reference clock signal is input and the second output terminal. Input terminals (for example, the input of the clock signal generation circuit 172)
Power terminal D).

5. The gaming machine according to claim 4 , wherein the random number generation unit measures a time during which a start signal is input from the start signal output unit, and the measured time includes the first clock signal and the second clock signal. Timer means (for example, a timer circuit 176) is provided for outputting the start signal to the latch signal output means when a predetermined time (for example, 3 ms) longer than the cycle of the clock signal is reached .

6. The gaming machine according to claim 5 , wherein the game control means executes a timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal input periodically (for example, every 2 ms). For example, the CPU 103 includes a part where the game control interrupt process is executed), and the display result determination unit is executing the timer interrupt process a predetermined number of times (for example, twice) by the timer interrupt process executing unit ( For example, for 4 ms), based on the fact that the start signal is continuously input from the start signal output means, the random number value is read from the random value storage means, and the timer means is executed by the timer interrupt processing execution means. Setting means for setting, as the predetermined time, a time shorter than the time at which a predetermined number of timer interruption processes are executed (for example, the timer circuit 176 is the execution time of two timer interruption processes 4 When the measured time reaches the time set as the predetermined time by the setting means, the start signal is output to the latch signal output means. To do.

The inventions according to claims 1 to 5 of the present application have the following effects.

According to the configuration of claim 1, the random number generation unit does not invert the reference clock signal output from the reference clock signal output unit, and the first clock signal has the same period and a phase difference of 180 degrees . And the second clock signal are generated, the output value of the numerical data is updated at the first timing when the first clock signal changes in a predetermined manner, and the second clock signal is in a predetermined manner. A latch signal is output at a second timing that changes in the same manner as in FIG. Thus, the random number generation means can reliably change the update timing of the output value of the numerical data and the latch timing of the output value of the numerical data , so that the game control means Numerical values can be acquired reliably and stably. Further, according to this configuration, the game control means reads the random value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing. Furthermore, since the game control means can make the random value storage means readable only when the display result determination means reads the random value, the random number value can be obtained reliably and stably. Can do. When the stored random number value is updated by inputting a latch signal from the latch signal output means, the random number value storage means is in an unreadable state by the latch priority means even if an output control signal is output. Since the random number value can be prevented from being read out from the random value storage unit by the display result determining unit by being maintained, the random number value can be updated reliably and stably.

According to the configuration of claim 2, the random number generation unit does not invert the reference clock signal output from the reference clock signal output unit, and the first clock signal has the same period and a phase difference of 180 degrees. And the second clock signal are generated, the output value of the numerical data is updated at the first timing when the first clock signal changes in a predetermined manner, and the second clock signal is in a predetermined manner. A latch signal is output at a second timing that changes in the same manner as in FIG. Thus, the random number generation means can reliably change the update timing of the output value of the numerical data and the latch timing of the output value of the numerical data, so that the game control means Numerical values can be acquired reliably and stably. Further, according to this configuration, the game control means reads the random value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing. Furthermore, since the game control means can make the random value storage means readable only when the display result determination means reads the random value, the random number value can be obtained reliably and stably. Can do. The random value storage means stores the output even when a latch signal is output when a random number value is read from the random value storage means by the display result determination means when an output control signal is input from the read control means. Since the update of the random number value is prohibited by the read priority unit, the random number value can be acquired reliably and stably.

According to the configuration of claim 3, the clock signal generation unit includes a clock terminal to which the reference clock signal is input and an input terminal connected to the second output terminal. The first clock signal and the second clock signal having the same period and different phases by 180 degrees are generated without inverting the signal, the update timing of the output value of the numerical data, and the output value of the numerical data Therefore, the random number can be acquired reliably and stably.

According to the configuration of claim 4, the random number generation unit does not directly output the start signal input from the start signal output unit to the latch signal output unit, but the input time of the start signal is Measurement is performed by the timer means, and when the measurement time reaches a predetermined time longer than the period of the first clock signal or the second clock signal, the start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting a latch signal to the random value storage means due to the influence of noise or the like.

According to the configuration of claim 5, the timer means is set as the predetermined time that is shorter than the execution time of a predetermined number of timer interrupt processes by the timer interrupt process execution means. The random number value read by the display result determining means from the random value storage means can be prevented from becoming the same value as the previously read random number value.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is arranged. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. Also, a normal symbol display 40 is provided on the right side of the variable winning ball apparatus 7.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information by a plurality of variable display units. For example, a game ball wins a normal variable winning ball device 6. In the special figure game where is the execution condition, the variable display of three display symbols (special symbols) composed of numbers, letters, symbols, etc. is started, and after a certain period of time, they are displayed in the order of left, right, and middle Confirm the design. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. In addition, in the special game with the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, the pachinko The gaming machine 1 enters a special gaming state (probability improvement state) following the end of the jackpot gaming state, and thereafter, the probability that the display result in the special figure game becomes a jackpot combination is increased until a predetermined condition is satisfied. Further, in the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. It becomes an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 is configured with a light emitting diode (LED) or the like, and is lit, flashing, colored, etc. in a normal diagram game where the starting condition is that a game ball passes through a pass gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normally variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 3). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding memory 110 (FIG. 4) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 3). This opening / closing plate is normally closed, and when the special display game is performed by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is activated when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to the detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2) which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10, a main board 11, a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and an information terminal board 16. And are arranged at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  FIG. 3 is a block diagram showing a circuit configuration and the like in the main board 11. As shown in FIG. 3, wiring is connected to the main board 11 from the display control board 12 and the random number generation circuit 17.

  The start winning opening switch 70 generates a start winning signal (high level signal) SS with the main board 11 and a random number based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. This is output to the circuit 17.

  The main board 11 is also connected with wiring from a special variable winning ball apparatus 7 which is a big winning opening and a predetermined winning opening switch for detecting a winning of a game ball to other winning openings. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball device 6 and opening / closing control in the special variable winning ball device 7. .

  The main board 11 is configured by mounting a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a control. A CPU (Central Processing Unit) 103 that performs the operation and an I / O (Input / Output) port 104 are incorporated.

  As shown in FIG. 4, the game control microcomputer 100 includes a special figure holding memory 110, a jackpot determination table memory 111, a flag memory 112, and a start winning opening switch timer memory 113. .

  In the special figure holding memory 110, a condition (execution condition) for executing a variable symbol display (special symbol game) for a game ball winning the normal variable winning ball device 6 is established. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 110 includes four entries, and each entry has a holding number and a random number value R read from the random value storage circuit 175 in accordance with the winning order in the order of winning to the ordinary variable winning ball device 6. Are stored in association with each other. Each time the special symbol confirmation command is sent from the main board 11 to the display control board 12 and the special symbol variable display is finished once or the big hit gaming state is finished, the variable display based on the highest level information is performed. The start condition is satisfied, and variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. Further, when a game ball newly wins the normal variable winning ball apparatus 6 during variable display of a special symbol or the like, the random number value R read from the random value storage circuit 175 based on the winning is the highest empty. Registered in the entry.

  The jackpot determination table memory 111 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 111 stores a normal big hit determination table 121 shown in FIG. 5A and a probability change big hit determination table 122 shown in FIG. 5B.

  Whether the normal big hit determination table 121 shown in FIG. 5 (A) and the probability variation big hit determination table 122 shown in FIG. 5 (B) use the display result of the special figure game by the variable display device 4 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 121 and 122, a random value R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 122, more random numbers R are associated with the display result of “big hit” than in the normal big hit determination table 121. That is, by determining the display result of the special figure game using the probability change big hit determination table 122, it is possible to achieve a probability improvement state in which the probability of being in the big hit gaming state is higher than in the normal gaming state.

  In this embodiment, in the normal jackpot determination table 121 shown in FIG. 5A, among the jackpot determination random numbers R “0 to 65335” generated from the random number generation circuit 17, “2001 to 2184” is set to “big hit”. Is associated with the display result. On the other hand, in the probability variation jackpot determination table 121 shown in FIG. 5B, among the jackpot determination random numbers R “0 to 65335” generated from the random number generation circuit 17, “2001 to 3104” is a display result of “big hit”. Is associated.

  In the flag memory 112 shown in FIG. 4, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 112 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (described later) (FIG. 13). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

  The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The start winning port switch timer memory 113 is for storing a timer value that is added or cleared in accordance with the start winning signal SS input from the start winning port switch 70.

  The switch circuit 107 shown in FIG. 3 takes in the start winning signal SS from the start winning port switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The display control board 12 performs display control for image processing in the variable display game independently of the main board 11. Based on the display control command output from the main board 11, the display control board 12 displays an image used for the variable display game on the variable display device 4, and controls turning on / off the normal symbol display 40. . In other words, the display control board 12 controls the display operation of the variable display device 4 based on the control command from the main board 11, thereby controlling the effect by the image display related to the progress of the game.

  The audio control board 13 and the lamp control board 14 are sub-side controls that execute the audio output control and the lamp output control independently of the main board 11 based on the control command transmitted from the main board 11. It is a substrate. That is, the sound control board 13 controls the sound output operation by the speakers 8L and 8R based on the control command from the main board 11, thereby controlling the effect by the sound related to the progress of the game. In addition, the lamp control board 14 controls the lighting / flashing operation of the game effect lamp 9 based on the control command from the main board 11, thereby controlling the effect of lighting, blinking or extinguishing of the lamp related to the progress of the game. . The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  FIG. 6 is a block diagram showing a configuration of the random number generation circuit 17. As shown in FIG. 6, the random number generation circuit 17 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, a random value storage circuit 175, and a timer circuit 176. , Is composed of. The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The reference clock signal output circuit 171 generates a reference clock signal S0 having a predetermined frequency (for example, 20 MHz), and outputs the generated reference clock signal S0 to the clock signal generation circuit 172 and the timer circuit 176.

  The clock signal generation circuit 172 is configured by a D-type lip flop circuit or the like. The clock terminal CK of the clock signal generation circuit 172 is connected to the output terminal of the reference clock signal output circuit 171, and the positive phase output terminal Q is connected to the counter 173. Further, the anti-phase output terminal (inverted output terminal) Q (bar) of the clock signal generation circuit 172 is connected to the input terminal D and the clock terminal CK of the latch signal output circuit 174.

  The clock signal generation circuit 172 outputs a signal fed back from the reverse phase output terminal Q (bar) to the input terminal D at a timing when the reference clock signal S0 input from the reference clock signal output circuit 171 to the clock terminal CK rises. In synchronization, the signal is output from the positive phase output terminal Q, and the negative phase signal (inverted signal) of the signal output from the positive phase output terminal Q is output from the negative phase output terminal Q (bar). In this manner, the clock signal generation circuit 172 generates two clock signals (counting clock signal S1 and latching clock signal S2) having the same period and different phases, and counting clocks from the positive phase output terminal Q. Each of the signals S1 and the latch clock signal S2 can be output from the negative phase output terminal Q (bar).

  Specifically, a count clock signal S1 having a frequency of 10 MHz is output from the positive phase output terminal Q, and a negative phase signal of the count clock signal S1, that is, a count is output from the negative phase output terminal Q (bar). Similarly to the clock signal S1, a latch clock signal S2 having a frequency of 10 MHz and having a phase different from that of the counting clock signal S1 by π (= 180 °) is output.

  The counter 173 circulates the output count value C from a predetermined initial value to a predetermined final value in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 171. Update to

  In this embodiment, the counter 173 is a 16-bit binary counter, and counts up the count value C from “0” to “65535” by 1 each time the rising edge of the count clock signal S1 is input. Go. When the count value C is counted up to “65535”, the count value C is returned to “0” and counted up to “65535” again. That is, the count value C is cyclically updated as “0” → “1” →... → “65535” → “0” →... Each time the rising edge of the count clock signal S1 is input to the counter 173. The

  The latch signal output circuit 174 is configured by a D-type lip flop circuit or the like. The input terminal D of the latch signal output circuit 174 is connected to the output terminal of the timer circuit 176, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175.

  The latch signal output circuit 174 generates the latch signal SL by synchronizing the start winning signal SS input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK, and generates the output terminal Q. Output from.

  The random value storage circuit 175 shown in FIG. 6 is a 16-bit register, and stores a random value R that is read in a winning process in step S102 described later. The random value storage circuit 175 latches and stores the count value C input from the counter 173 as the random value R in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174. Thus, every time the start winning signal SS is input to the random number generation circuit 17, the stored random number value R is sequentially updated.

  FIG. 7 is a circuit diagram showing a configuration example of the random value storage circuit 175. As shown in FIG. 7, the random value storage circuit 175 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 Philip flop circuits 210 to 225, and 16 OR circuits. 230-245.

  The input terminal of the AND circuit 201 is connected to the output terminal Q of the latch signal output circuit 174 and the output terminal of the NOT circuit 204, and the output terminal is the input terminal of the NOT circuit 202 and the clock terminal CK0 of the Philip flop circuits 210 to 225. To CK15. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the I / O port 104 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 230 to 245.

  The input terminals D0 to D15 of the Philip flop circuits 210 to 225 are connected to the output terminal of the counter 173. The clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 are connected to the output terminal of the AND circuit 201, and the output terminals Q0 to Q15 are connected to the other input terminals of the OR circuits 230 to 245, respectively.

  The input terminals of the OR circuits 230 to 245 are connected to the output terminal of the NOT circuit 204 and each of the output terminals of the flip-flop circuits 210 to 225, and the output terminals are connected to the I / O port 104 of the game control microcomputer 100. It is connected.

  FIG. 8 is a diagram for explaining the details of the connection between the output terminals of the OR circuits 230 to 245 and the I / O port 104 of the game control microcomputer 100. In this embodiment, the output terminals of the OR circuits 230 to 245 and the bits of the jackpot random number input port included in the I / O port 104 are interchanged and connected as shown in FIG. Yes. Thereby, the randomness of the random number input to the game control microcomputer 100 can be enhanced.

  The operation of the random value storage circuit 175 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the gaming control microcomputer 100 (when one input of the AND circuit 203 is low level), the output terminal Q of the latch signal output circuit 174 At the timing when the input latch signal SL rises from the low level to the high level (in the example shown in FIG. 9, timings T1, T2, and T7), the inputs of the AND circuit 201 both become the high level and are output from the output terminals. The signal SR becomes high level. The signal SR output from the AND circuit 201 is input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225.

  The Philip flop circuits 210 to 225 respond to the rising edge of the signal SR input from the clock terminals CK0 to CK15, and receive bit data C0 to C15 of the count value C input from the counter 173 via the input terminals D0 to D15. Are latched and stored as bit data R0 to R15 of the random number value, and the bit data R0 to R15 of the stored random number value R are output from the output terminals Q0 to Q15.

  When the output control signal SC is not input (in the example shown in FIG. 9, the period up to the timing T3 and the period after the timing T6), one input of the AND circuit 203 is at a low level, so that the output is output from the output terminal. The signal SG to be output becomes a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Thus, since one input of the OR circuits 230 to 245 is at the high level, regardless of whether the signal input to the other input terminal is at the high level or the low level, that is, the input random number value. Regardless of whether the values of the R bit data R0 to R15 are “0” or “1”, the signals SO0 to SO15 output from the OR circuits 230 to 245 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 175 is always “635535 (= 1111h)”, and the random value R cannot be read from the random value storage circuit 175. That is, when the output control signal SC is not input, the random value storage circuit 175 is in a non-readable (disabled) state.

  When the output control signal SC is input from the gaming control microcomputer 100 when the latch signal SL input from the latch signal output circuit 174 is at a low level (in the example shown in FIG. 9, from the timing T4 to the timing T6). Since the inputs of the AND circuit 203 are both at a high level, the signal SG output from the output terminal is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminal of each of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the value of the bit data R0 to R15 of the random value R input to the other input terminals of the OR circuits 230 to 245 is directly from the output terminal of the OR circuits 230 to 245 (the value of the bit data R0 to R15 is “1”). "1" is output when it is "," and "0" is output when it is "0." As a result, the random value R can be read from the random value storage circuit 175. In other words, when the output control signal SC is input, the random value storage circuit 175 enters a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 174 before the output control signal SC is input from the game control microcomputer 100, one input of the AND circuit 203 becomes low level. After that, even when the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 9, it is output from the output terminal). The signal SG remains at a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 becomes high level in this way, the output from the OR circuits 230 to 245 is performed regardless of whether the signal input to the other input terminal is high level or low level. All of the signals SO0 to SO15 are at a high level, and the random value R cannot be read from the random value storage circuit 175 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 175 becomes incapable of receiving the output control signal SC.

  When the output control signal SC is input from the gaming microcomputer 100 before the latch signal SL input from the latch signal output circuit 174 becomes high level, one input of the AND circuit 201 becomes low level. Therefore, after that, even if the input latch signal SL becomes high level (in the example shown in FIG. 9, timing T5) while the output control signal SC is being input, it is output from the output terminal. The signal SR remains at a low level. For this reason, the signal SR input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 does not rise from the low level to the high level, and the bit data R0 of the random value R stored in the Philip flop circuits 210 to 225. ˜R15 are not updated even when the latch signal SL input from the latch signal output circuit 174 rises. That is, when the output control signal SC is input, the random value storage circuit 175 becomes incapable of receiving the latch signal SL.

  The timer circuit 176 shown in FIG. 6 measures the time during which the start winning signal SS is input from the start winning port switch 70, and when the measured time reaches a predetermined time (for example, 3 ms), the timer winning signal SS is displayed. The data is output to the latch signal output circuit 174.

  In this embodiment, the timer circuit 176 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. While the input is at a high level, the timer circuit 176 counts up or down a predetermined timer value every time the reference clock signal S0 is input from the reference clock signal output circuit 171. When the timer value counted up or down reaches a value corresponding to 3 ms, the timer circuit 176 determines that the input signal is the start winning signal SS, and latches the start winning signal SS as a latch signal. Output to the output circuit 174.

  FIG. 10 is a timing chart for explaining the operation of the random number generation circuit 17.

  As shown in FIG. 10A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  The clock signal generation circuit 172 responds to the rising edge of the reference clock signal S0 input from the clock terminal CK with the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 10B, the positive-phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 10D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 10C, the counter 173 updates the count value C in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 inputs the start winning signal SS shown in FIG. 10E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 10F is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2.

  The random value storage circuit 175 responds the count value C input from the counter 173 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  In this way, the random number generation circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 11 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, after interrupting is permitted (step S3), a loop process is started.

  CPU103 which performed the game control main process shown in FIG. 11 will perform the game control interruption process shown in the flowchart of FIG. 12, if the interruption request signal from CTC is received and an interruption request | requirement is received.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined switch process (step S11). In the switch process, it is determined whether or not the start winning signal SS input from the start winning port switch 70 via the switch circuit 107 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the start winning port switch timer memory 113. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary according to the diagnosis result (step S12). Thereafter, a determination random number update process for updating a predetermined determination random number (step S13) and a display random number update process for updating a predetermined display random number (step S14) are sequentially executed.

  Next, the CPU 103 executes special symbol process processing (step S15). In the special symbol process, the corresponding process is selected and executed according to the special symbol process flag provided in the flag memory 112 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state. Following the special symbol process, the CPU 103 executes a normal symbol process (step S16). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag provided in the flag memory 112 in order to control the normal symbol display 40 in a predetermined order.

  Furthermore, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the display control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S17). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in a predetermined command transmission table, and so on, for the sub-side control board such as the display control board 12. A control signal for controlling the progress of the game is transmitted. The display control command sent from the main board 11 by the command control process is received by the CPU of the display control board 12, and the display control of the variable display device 4 and the lighting control of the normal symbol display 40 are performed according to the display control command. .

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S18). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movable blade piece in the normal variable winning ball device 6 and open / close the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S19). Thereafter, by executing predetermined prize ball processing, the number of prize balls is set based on the start winning signal SS input from the start winning opening switch 70, and a payout control command is output to the payout control board 15. It is possible (step S20).

  FIG. 13 is a flowchart showing the special symbol process performed in step S15. When the special symbol process is started, the CPU 103 first checks whether or not the game ball has won the normal variable winning ball device 6 by checking the timer value stored in the starting winning port switch timer memory 113. A determination is made (step S101). In step S101, the CPU 103 loads the timer value stored in the starting winning a prize opening switch timer memory 113, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). As a result, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is performed a predetermined number of times (for example, twice) (for example, 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S101; Yes), the winning process is executed (step S102), and the timer value is set. clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S101; No), and the winning process is skipped.

  FIG. 14 is a flowchart showing the winning process in step S102. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S121). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S121; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S121; No), an output control signal SC is sent to the random value memory circuit 175, and the random value memory circuit 175 is controlled to be readable (enabled). (Step S122).

  Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S123), and stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S124). The transmission of the output control signal SC to the numerical value storage circuit 175 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S125). Then, the CPU 103 adds “1” to the starting winning memory number (step S126), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S127).

  Thereafter, the CPU 103 selects one of the nine processes of steps S110 to S118 shown in FIG. 13 based on the value of the special symbol process flag stored in the flag memory 112. Below, each process of step S110-S118 is demonstrated.

  The special symbol normal process of step S110 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0”. Here, in the special figure holding memory 110, when various data such as the random number R corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S111 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 15, the CPU 103 first reads the random number value R stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S141). At this time, “1” is subtracted from the reserved storage number, and the random number R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is increased by one entry. (Step S142).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S143). If the probability change is not in progress (step S143; No), the CPU 103 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table 121 as shown in FIG. 5A is set (step S144). On the other hand, if the probability change is in progress (step S143; Yes), the probability change big hit determination table 122 as shown in FIG. 5B is set (step S145).

  Based on the random value R read in step S141, the CPU 103 determines whether or not the special game display result is a big hit using the big hit determination table 121 or 122 set in step S144 or S145 ( Step S146). If it is determined to be a big hit (step S146; Yes), the big hit state flag provided in the flag memory 112 is set to the on state (step S147), and if it is determined to be lost. (Step S146; No), the big hit state flag is cleared and turned off (Step S148). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S149).

  The confirmed symbol determination process in step S112 shown in FIG. 13 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 determines whether or not the big hit state flag provided in the flag memory 112 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S113 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 first determines whether or not the big hit state flag provided in the flag memory 112 is turned on, and whether or not it is determined to reach in the determined symbol determination process in step S112. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in the current special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 103 updates the value of the special symbol process flag to “4” which is a value corresponding to the variable display command process.

  The variable display command process of step S114 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 103 controls the variable display device 4 to start variable display for all the special symbols. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S112 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S113 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S115 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 performs settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S116 is a process executed when the value of the special symbol process flag is “6”. In this process, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S117 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S118 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the display control board 12. In addition, the CPU 103 clears the big hit state flag provided in the flag memory 112 and turns it off. Then, the value of the special symbol process flag is updated to “0”.

  As described above, according to this embodiment, the clock signal generation circuit 172 inputs the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0, and is output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  When a game ball wins the normal variable winning ball apparatus 6 which is a starting winning opening, the starting winning opening switch 70 sends a starting winning signal SS to the main board 11 and the random number generating circuit 17, and the random number generating circuit. The start winning signal SS sent to 17 is input to the input terminal D of the latch signal output circuit 174 via the timer circuit 176. The latch signal output circuit 174 receives the start winning signal SS input to the input terminal D as the latch clock signal S2 input from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timing T11, T13, T15,... Rising from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds the count value C input from the counter 173 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  In this way, the random number generation circuit 17 can reliably change the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S0, the random number generation circuit 17 can update even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  On the other hand, on the main board 11 side, the CPU 103 continues the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). When it is detected that the input has been made, a winning process is executed.

  In this winning process, the CPU 103 sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a readable (enable) state, and then reads the random value R from the random value storage circuit 175. . Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 175 and controls the random value storage circuit 175 to be in a non-readable state (disabled), and then the read random value R becomes the predetermined determination value “ It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state by determining whether or not it matches with “2001 to 2184” or the like.

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 175 to the readable state only when the CPU 103 reads the random number value R. Can do. Further, since the CPU 103 reads the random value R from the random value storage circuit 175 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  The random number generation circuit 17 does not directly input the start winning signal SS output from the start winning port switch 70 to the latch signal output circuit 174, but once inputs it to the timer circuit 176 to input the start winning signal SS. Time is measured, and when the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 174. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 174 from erroneously outputting the latch signal SL to the random value storage circuit 175 due to the influence of noise or the like. Since the timer circuit 175 is set to “3 ms” which is shorter than “4 ms” between executions of the two timer interrupt processes, the random number value R read out from the random value storage circuit 175 by the CPU 103 is the previous value. It is possible to prevent the same value as the random value R read at the time of winning a prize.

  In addition, when the latch signal SL is input from the latch signal output circuit 174, the random value storage circuit 175 converts the output control signal (high level signal) SC input from the game control microcomputer 100 into a low level signal. By converting to, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R from the random value storage circuit 175 when the random value R stored in the random value storage circuit 175 is updated. 1 can reliably and stably update the random value R.

  Furthermore, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 175 converts the latch signal (high level signal) SL input from the latch signal output circuit 174 into a low level signal. By converting to, the latch signal SL is controlled so as not to be received. Thereby, when the game control microcomputer 100 reads the random value R from the random value storage circuit 175, it is possible to prevent the random value R stored in the random value storage circuit 175 from being updated. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above-described embodiment, the start winning port switch 70 generates a random number for the start winning signal SS and the main board 11 based on detecting the winning of a game ball to the ordinary variable winning ball device 6 which is the starting winning port. The random number generation circuit 17 measures the time during which the start winning signal SS is input from the start winning port switch 70 in the timer circuit 176, and the measured time is a predetermined time (for example, 3 ms). ), The start winning signal SS is output to the latch signal output circuit 174.

  However, the present invention is not limited to this, and the start winning opening switch 70 outputs the start winning signal SS only to the main board 11, and the CPU 103 mounted on the main board 11 is set a predetermined number of times (for example, 2 ) Timer interruption process is being executed (for example, for 4 ms), the start winning signal SN for latch is latched based on the fact that the start winning signal SS is continuously input from the start winning opening switch 70. You may send to the output circuit 174.

  A gaming machine according to such a modification will be described below with reference to the drawings. FIG. 16 is a block diagram showing a circuit configuration and the like in the main board 11 according to this modification, and FIG. 17 is a block diagram showing a configuration of a random number generation circuit 27 according to this modification. In addition, in the random number generation circuit 27, about the same structure as the random number generation circuit 17 which concerns on the said embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted as needed.

  As shown in FIG. 17, the random number generation circuit 27 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, and a random value storage circuit 175. Yes.

  The input terminal D of the latch signal output circuit 174 is connected to the I / O port 104, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175. The latch signal output circuit 174 generates and outputs a latch signal SL by synchronizing the latch start winning signal SN input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK. Output from terminal Q.

  FIG. 18 is a timing chart for explaining the operation of the random number generation circuit 27.

  As shown in FIG. 18A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  The clock signal generation circuit 172 responds to the rising edge of the reference clock signal S0 input from the clock terminal CK with the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 18B, the positive phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 18D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 18C, the counter 173 updates the count value C in response to the rising edge of the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 receives the latch start winning signal SN shown in FIG. 18E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 18 (F) is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2 input.

  The random value storage circuit 175 responds the count value C input from the counter 173 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  In this way, the random number generation circuit 27 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In this modified example, the flag memory 112 shown in FIG. 4 is provided with a random value read flag in addition to the above-described flags. This random number read flag is set to the on state when the latch start winning signal SN is sent to the latch signal output circuit 174, and is cleared when the random number value R is read from the random value storage circuit 175 to be in the off state. Become.

  FIG. 19 is a flowchart showing the special symbol process performed in step S15 in this modification. When the special symbol process is started, the CPU 103 first determines whether or not the random number read flag provided in the flag memory 112 is on (step S201).

  When the random number read flag is off (step S201; No), the timer value stored in the start winning mouth switch timer memory 113 is checked to determine whether or not the game ball has won the normal variable winning ball device 6. Thus, the determination is made (step S202). In step S202, the CPU 103 loads the timer value stored in the start winning a prize opening switch timer memory 113, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). Thereby, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won (step S202; Yes), and a winning process is executed (step S203). clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S202; No), and the winning process is skipped.

  FIG. 20 is a flowchart showing the winning process in step S203. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S221). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S221; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S221; No), the latch start winning signal SN is sent to the latch signal output circuit 174 (step S222), and the random number read flag is set to the on state. (Step S223).

  If the random number read flag is on in step S201 (step S201; Yes), random number read processing is executed (step S224).

  FIG. 21 is a flowchart showing the random value reading process in step S224. In this random value reading process, the CPU 103 first sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a readable (enable) state (step S231). Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S232), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S233), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 174 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S234).

  Then, the CPU 103 adds “1” to the starting winning memory number (step S235), and sets the random number value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S236). Thereafter, the CPU 103 clears the random number read flag and turns it off (step S237).

  As described above, according to this modification, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  Then, when a game ball wins the normal variable winning ball apparatus 6 which is a starting winning port, the starting winning port switch 70 sends a starting winning signal SS only to the main board 11. The CPU 103 of the main board 11 continuously inputs the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Based on this, it is determined that the game ball has won the normal variable winning ball apparatus 6, and a latch start winning signal SN is sent to the random number generation circuit 27.

  The latch start winning signal SN sent to the random number generation circuit 27 is inputted to the input terminal D of the latch signal output circuit 174. The latch signal output circuit 174 receives the latch start winning signal SN input to the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timings T11, T13, T15,... At which S2 rises from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds the count value C input from the counter 173 to the input terminal D to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  Thereafter, in the first timer interruption process, the CPU 103 reads the random value R from the random value storage circuit 175 and determines whether or not the read random value R matches a predetermined determination value “2001 to 2184” or the like. It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state.

  In this way, the random number generation circuit 27 can reliably vary the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Further, since the random number generation circuit 27 performs the updating of the count value C and the output of the latch signal SL without inverting the reference clock signal S0, the update is performed even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  Further, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 outputs the latch start winning signal SN to the latch signal output circuit 174 of the random number generation circuit 27, so the pachinko gaming machine 1 It is not necessary to provide a path for supplying the start winning signal SS from the start winning port switch 70 to the random number generation circuit 27, and the hardware configuration can be simplified.

  Further, the CPU 103 determines that the game ball has won the normal variable winning ball device 6 based on the continuous input of the start winning signal SS while the two timer interruption processes are being executed. Therefore, the pachinko gaming machine 1 can prevent the latch start winning signal SN from being erroneously output to the random number generation circuit 27 due to the influence of noise or the like.

  In addition, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 reads the random value R from the random value storage circuit 175 in the first timer interruption process. It is possible to prevent the read random value R from being the same as the previously read random value R.

  In the above embodiment, the positive phase output terminal Q of the clock signal generation circuit 172 is connected to the input terminal of the counter 173, and the negative phase output terminal Q (bar) is connected to the input terminal D of the latch signal output circuit 174. Was connected. However, the present invention is not limited to this, and the positive phase output terminal Q of the clock signal generation circuit 172 is the input terminal Q of the latch signal output circuit 174, and the negative phase output terminal Q (bar) is the input terminal of the counter 173. , Each may be connected.

  Further, in the above embodiment, the counter 173 is an up counter, but the present invention is not limited to this, and may be a down counter. Further, the numerical value updating means is not limited to the counter 173, and may be a pseudo random number generation circuit. In addition, the connection between the output terminal of the bit data C0 to C15 of the count value C of the counter 173 and the input terminal of the bit data C0 to C15 of the count value C of the random value storage circuit 175 may be changed. Then, the randomness of the count value C input to the random value storage circuit 175 can be improved.

  In the above embodiment, the random value storage circuit 175 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 230 to 245 to control the reception of the latch signal SL and the output control signal SC and output the random value R. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 175 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 104 and the latch signal output circuit 174, and the latch signal SL. In response to the input of the output control signal SC and the path to the I / O port 104 and the latch signal output circuit 174, the latch signal SL and the enable / disable control of the output control signal SC are performed. Also good.

  Further, in the above embodiment, the timer circuit 176 is activated in response to the input of the high level signal, and the reference clock signal from the reference clock signal output circuit 171 while the input is at the high level. In response to the input of S0, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, it is determined that the input signal is a high level signal. The signal is output to the latch signal output circuit 174. However, the present invention is not limited to this, and the timer circuit 176 measures the time during which the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. Any signal may be used as long as it outputs the winning signal SS to the latch signal output circuit 174.

  In the above embodiment, the timer circuit 176 measures the signal input time using the reference clock signal S0 sequentially input from the reference clock signal output circuit 171, but the present invention is not limited to this. Instead, the timer circuit 176 may use a clock signal obtained by dividing the reference clock signal S0 or a clock signal output from a clock signal output circuit different from the reference clock signal output circuit 171. In the above embodiment, the timer circuit 176 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, and from the 4 ms that is the execution time of the two timer interrupt processes. Any time can be set as long as the time is short.

  Further, in the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 176 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  Further, in the above-described embodiment, the gaming machine can perform the variable display start condition (for example, the previous variable display and the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball device 6)). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the end of the big hit gaming state is established, This is a pachinko gaming machine that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the result is a predetermined specific display result.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 22, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 22 uses a game control means (for example, main board) or random number generation means as a start winning signal output means of the present invention based on a start lever 1011 operated by a player. A start switch (not shown) for outputting to (for example, a random number generation circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 22 functions as rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. That is, any form of game machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  1, 2, and 22, the block configurations shown in FIGS. 3, 4, 6, 8, 16, and 17, and the timing charts shown in FIGS. 9, 10, and 18. The circuit configuration shown in FIG. 7, the table configuration shown in FIG. 5, and the flowchart configurations shown in FIGS. 11 to 15 and 19 to 21 can be arbitrarily changed and modified without departing from the spirit of the invention. is there.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of a winning ball, but encloses a game ball and gives a score in response to detection of the winning ball It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the structural example of the table for jackpot determination. It is a block diagram which shows the structural example of a random number generation circuit. It is a circuit diagram which shows the structural example of a random value storage circuit. It is a figure for demonstrating the connection of the output terminal of the OR circuit of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random value storage circuit. 3 is a timing chart for explaining the operation of a random number generation circuit. It is a flowchart which shows a game control main process. It is a flowchart which shows a game control interruption process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a block diagram which shows the modification of circuit configurations etc. in the main board | substrate shown in FIG. FIG. 7 is a block diagram showing a modification of the configuration of the random number generation circuit shown in FIG. 6. 18 is a timing chart for explaining the operation of the random number generation circuit shown in FIG. It is a flowchart which shows the modification of the special symbol process process shown in FIG. It is a flowchart which shows the detail of the winning process in FIG. FIG. 20 is a flowchart showing details of random value reading processing in FIG. 19. FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Variable display device
6 ... Ordinary variable winning ball device
7 ... Special variable winning ball device 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board 17, 27 ... Random number generation circuit 21, 22 ... Solenoid
40 ... Normal symbol display
70 ... Start prize opening switch 100 ... Microcomputer for game control 101 ... ROM
102 ... RAM
103 ... CPU
104 ... I / O port 107 ... Switch circuit 108 ... Solenoid circuit 110 ... Special figure holding memory 111 ... Table game for jackpot judgment 112 ... Flag memory 113 ... Start winning port switch timer memory 121 ... Table for jackpot judgment at normal time 122 ... Certain change Big hit determination table 171... Reference clock signal output circuit 172... Clock signal generation circuit 173... Counter 174... Latch signal output circuit 175... Random value storage circuit 176 ... Timer circuits 201 and 203. ... 225 ... Philip flop circuits 230 to 245 ... OR circuit 1000 ... Slot machine 1001 ... Liquid crystal display 1002 ... Variable display device 1011 ... Start lever

Claims (5)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
With
The random number generating means includes
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
Clock signal generating means for generating a first clock signal and a second clock signal based on the reference clock signal;
Including
The clock signal generation means includes
As the first clock signal, in synchronization with the timing of the reference clock signal is changed for each of the predetermined period, a first output terminal for outputting a signal signal state changes,
A second output terminal for outputting a signal having the same period as the first clock signal and a phase different by 180 degrees as the second clock signal ;
Including
The random number generating means includes
Numerical data updating means for updating an output value of numerical data at a first timing at which a signal state of the first clock signal changes in a predetermined manner;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing when the signal state in the second clock signal changes in the same manner as the predetermined manner;
In response to a latch signal input from the latch signal output means, random number storage means for storing the output value of the numerical data updated by the numerical data update means as a random value;
Including
The game control means includes
Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determination means for determining whether or not the display result in the variable display is a specific display result ;
Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Read out the random number value from the random number storage means, and after stopping the output of the output control signal to the random value storage means, the read control means for controlling the random value storage means in an unreadable state,
The random value storage means includes latch priority means for maintaining an unreadable state even when an output control signal is output from the read control means when a latch signal is input from the latch signal output means,
A gaming machine characterized by that.   Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
  Game control means for controlling the progress of the game;
  Random number generating means for generating a random number;
  A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
With
  The random number generating means includes
  Reference clock signal output means for outputting a reference clock signal of a predetermined period;
  Clock signal generating means for generating a first clock signal and a second clock signal based on the reference clock signal;
Including
  The clock signal generation means includes
  A first output terminal that outputs, as the first clock signal, a signal whose signal state changes in synchronization with a timing at which the reference clock signal changes every predetermined period;
  A second output terminal for outputting a signal having the same period as the first clock signal and a phase different by 180 degrees as the second clock signal;
Including
  The random number generating means includes
  Numerical data updating means for updating an output value of numerical data at a first timing at which a signal state of the first clock signal changes in a predetermined manner;
  Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing when the signal state in the second clock signal changes in the same manner as the predetermined manner;
  In response to a latch signal input from the latch signal output means, random number storage means for storing the output value of the numerical data updated by the numerical data update means as a random value;
Including
  The game control means includes
  Based on the input of the start signal from the start signal output means, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determination means for determining whether or not the display result in the variable display is a specific display result;
  Before the display result determining means reads the random value from the random value storage means, an output control signal is output to the random value storage means to control the random value storage means to be readable, and the display result determination means Read out the random number value from the random number storage means, and after stopping the output of the output control signal to the random value storage means, the read control means for controlling the random value storage means in an unreadable state,
  The random number storage means is a read priority means for prohibiting updating of the stored random number value even when a latch signal is outputted from the latch signal output means when an output control signal is inputted from the read control means. Including,
A gaming machine characterized by that. The clock signal generation means includes
A clock terminal to which the reference clock signal is input;
An input terminal connected to the second output terminal;
The gaming machine according to claim 1 or 2, characterized in that. The random number generating means includes
The time when the start signal is input from the start signal output means is measured, and when the measured time becomes a predetermined time longer than the cycle of the first clock signal and the second clock signal, the start Timer means for outputting a signal to the latch signal output means,
The gaming machine according to claim 1, 2, or 3. The game control means includes
In response to an interrupt request signal periodically input, includes timer interrupt processing execution means for executing timer interrupt processing,
The display result determining means includes
While the timer interrupt process is executed by the timer interrupt process execution unit a predetermined number of times, the start signal is continuously input from the start signal output unit. Read
The timer means includes
Including setting means for setting, as the predetermined time, a time shorter than a time during which the timer interruption processing is executed by the timer interruption processing execution means;
When the measured time reaches the time set as the predetermined time by the setting means, the start signal is output to the latch signal output means,
The gaming machine according to claim 4, wherein:

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