JP4328607B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  Currently, in game machines, a random number used to determine whether or not to make a “big hit” (a big hit determination random number) is generated by the CPU executing a predetermined application program. However, such a random number generation method has a problem that the processing load on the CPU at the time of generation increases.

To solve this problem, a random number circuit is used to generate a big hit determination random number, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. A gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 1).
JP-A-7-124296 (page 3-4, FIG. 1).

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). A gaming machine that stores random numbers is also disclosed (for example, see Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2).

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  In the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gradual, the rising edge of the inverted clock pulse also becomes gradual. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse is output. There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reliably and stably obtaining a random value.

In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (for example, a pachinko gaming machine 1) that has a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result, Game control means for controlling (for example, the game control microcomputer 100 mounted on the main board 11), random number generating means for generating random numbers (for example, the random number generating circuit 17), Start signal output means (for example, a start winning port switch 70) for outputting a start signal (for example, a start winning signal SS) to the game control means and the random number generating means based on the execution condition being satisfied, The random number generator includes a clock signal generator (for example, a clock signal generation circuit 171) that generates and outputs a reference clock signal (for example, a reference clock signal S1) having a predetermined period, and a reference that is output from the clock signal generator. A first timing among a plurality of timings at which the clock signal rises from a low level to a high level every predetermined cycle (for example, timings T11, T21,... At which the reference clock signal S1 rises from a low level to a high level). (For example, timing T11, T12,...), Numerical data (for example, count) C) is input from the start signal output means at a numerical update means (for example, a counter 174) for updating C and a second timing (for example, timing T22) different from the first timing among the plurality of timings. A latch signal output means (for example, a latch signal output circuit 175) for outputting a starting signal as a latch signal (for example, a latch signal SL), and the numerical value updating means in response to the latch signal input from the latch signal output means. Random number storage means (for example, random value storage circuit 176) that stores the updated numerical data as random number values (for example, random value R), and the game control means receives a start signal from the start signal output means. Based on the input (for example, that the CPU 103 has determined Yes in step 101), A random number value is read from the random number value storage means, and the display result in the variable display is specified by determining whether or not the read random number value matches predetermined determination value data (for example, “3” or the like). Display result determining means for determining whether or not to obtain a result (for example, a portion where the CPU 103 executes a winning process in step S102 and a jackpot determining process in step S111), and the random number generating means is input from the clock signal generating means Frequency dividing means (for example, a frequency dividing circuit 172) for generating a divided clock signal (for example, a divided clock signal S2) by dividing the reference clock signal to be generated, and outputting the generated divided clock signal; When the frequency-divided clock signal input from the dividing means is at one of the high level and low level (for example, high level), The first clock that rises from the low level to the high level at the first timing by outputting the reference clock signal input from the clock signal generation means from the first output terminal (for example, the first output terminal O1). A signal (for example, the first clock signal S3) is supplied to the numerical value updating means, and the reference clock signal is output to the first output when the frequency-divided clock signal input from the frequency-dividing means is high level or low level. A reference clock signal input from the clock signal generating means is output from a second output terminal (for example, the second output terminal O2) when the level is different from that output from the terminal (for example, a low level). Thus, the second clock signal (for example, the second clock signal) rises from the low level to the high level at the second timing. Clock signal supply means (for example, selector 173) for supplying the signal S4) to the latch signal output means, wherein the numerical value update means is a rising edge (1) of the first clock signal supplied from the clock signal supply means ( For example, by responding to the rising edge of the first output clock signal S3), the numerical data is updated at the first timing, and the latch signal output means receives the start signal input from the start signal output means. The latch signal is output at the second timing by synchronizing with the rising edge of the second clock signal supplied from the clock signal supply means (for example, the rising edge of the second output clock signal S4), and the game The control means before the display result determination means reads the random value from the random value storage means In addition, an output control signal (for example, output control signal SC) is output to the random value storage means to control the random value storage means to be readable, and the display result determination means receives the random value from the random value storage means. After reading, the read control means for stopping the output of the output control signal to the random number value storage means and controlling the random number value storage means to the unreadable state (for example, the part where the CPU 103 executes the processing of step S122 and step S125) When the latch signal is input from the latch signal output means, the random value storage means receives an output control signal that maintains an unreadable state even if an output control signal is output from the read control means It includes control means (for example, an AND circuit 203) .

  In the gaming machine according to claim 2, the random number generation unit measures a time during which a start signal is input from the start signal output unit, and the measured time becomes a predetermined time (for example, 3 ms). A timer means (eg, a timer circuit 177) for outputting the start signal to the latch signal output means.

  4. The gaming machine according to claim 3, wherein the game control means executes a timer interruption process in response to an interruption request signal inputted periodically (for example, every 2 ms). (For example, a portion where the CPU 103 executes game control interrupt processing), and the display result determination means is executing the timer interrupt processing a predetermined number of times (for example, twice) by the timer interrupt processing execution means. (For example, for 4 ms), based on the fact that the start signal is continuously input from the start signal output means, the random number value is read from the random value storage means, and the timer means is read by the timer interrupt processing execution means. Setting means for setting, as the predetermined time, a time shorter than the time for which a predetermined number of timer interruption processes are executed (for example, 4 m which is the execution time of the timer interruption process for the timer circuit 177 twice) Shorter than includes a portion or the like) for setting a 3 ms, when the time measured reaches a time set as the predetermined time by the setting unit, and outputs the start signal to the latch signal output means.

5. The gaming machine according to claim 4 , wherein when the output control signal is input from the read control means, the random value storage means cannot receive a latch signal output from the latch signal output means. Latch signal reception control means (for example, an AND circuit 201).

The invention according to claims 1 to 4 of the present application has the following effects.

According to the configuration of claim 1, the random number generation unit does not invert the reference clock signal output from the clock signal generation unit, and the reference clock signal is changed from a low level to a high level every predetermined period. The numerical data is updated at a first timing among a plurality of timings rising to the input, and input from the start signal output means at a second timing different from the first timing among the plurality of timings The start signal generated can be output as a latch signal. For this reason, acquisition of the random number value can be performed reliably and stably. Further, according to this configuration, since the random value is read from the random value storage means only when the execution condition is satisfied, useless processing can be omitted. Further, the clock signal supply means has a reference input from the clock signal generation means when the frequency-divided clock signal input from the frequency dividing means is at one of a high level and a low level. A clock signal is output from a first output terminal, and a first clock signal that rises from a low level to a high level at the first timing is supplied to the numerical value updating means. Among the low levels, when the reference clock signal is at a level different from that output from the first output terminal, the reference clock signal is output from the second output terminal, and at the second timing, A second clock signal rising from a low level to a high level is supplied to the latch signal output means. For this reason, the update timing of the numerical data by the numerical value update means and the output timing (latch timing) of the latch signal by the latch signal output means can be made different.
Furthermore, the game control means can make the random value storage means readable only when the display result determination means reads the random value, so that the random value can be acquired reliably and stably. it can.
The random number generation unit prevents the random number value stored in the random number value storage unit from being read from the random value storage unit by the display result determination unit. Therefore, the random number value can be updated reliably and stably.

  According to the configuration of claim 2, the random number generation unit does not directly output the start signal input from the start signal output unit to the latch signal output unit, but the input time of the start signal is Measurement is performed by the timer means, and when the measurement time reaches a preset time, the start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting a latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration of claim 3, the timer means is set with the time shorter than the execution time of a predetermined number of timer interrupt processes by the timer interrupt process execution means as the predetermined time. The random number value read by the display result determining means from the random value storage means can be prevented from becoming the same value as the previously read random number value.

According to the configuration of claim 4 , the random number generation means stores the random value stored in the random value storage means when the display result determination means reads the random value from the random value storage means. Therefore, it is possible to reliably and stably acquire a random value.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being aligned. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is disposed. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. In addition, a normal symbol display 40 is provided above the variable display device 4.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information by a plurality of variable display units. For example, a game ball wins a normal variable winning ball device 6. In the special figure game where is the execution condition, the variable display of three display symbols (special symbols) composed of numbers, letters, symbols, etc. is started, and after a certain period of time, they are displayed in the order of left, right, and middle Confirm the design. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. In addition, in the special game with the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, the pachinko The gaming machine 1 enters a special gaming state (probability improvement state) following the end of the jackpot gaming state, and thereafter, the probability that the display result in the special figure game becomes a jackpot combination is increased until a predetermined condition is satisfied. In the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 includes a light emitting diode (LED) or the like, and lights up, flashes, colors, etc. in a normal diagram game where a game ball passes through a pass gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normally variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 3). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding memory 110 (FIG. 8) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 3). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to the detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2) which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10, a main board 11, a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and an information terminal board 16. And are arranged at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  FIG. 3 is a block diagram showing a circuit configuration and the like in the main board 11. As shown in FIG. 3, wiring is connected to the main board 11 from the display control board 12, the random number generation circuit 17, and the start winning port switch 70.

  The main board 11 is also connected with wiring from a special variable winning ball apparatus 7 which is a big winning opening and a predetermined winning opening switch for detecting a winning of a game ball to other winning openings. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The start winning opening switch 70 generates a start winning signal (high level signal) SS with the main board 11 and a random number based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. Output to the circuit 17.

  FIG. 4 is a block diagram showing a configuration of the random number generation circuit 17. As shown in FIG. 4, the random number generation circuit 17 includes a clock signal generation circuit 171, a frequency division circuit 172, a selector 173, a counter 174, a latch signal output circuit 175, a random value storage circuit 176, and a timer circuit. 177. The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The clock signal generation circuit 171 generates a reference clock signal S1 having a predetermined period, and outputs the generated reference clock signal to the frequency dividing circuit 172 and the selector 173.

  The frequency dividing circuit 172 divides the reference clock signal S1 input from the clock signal generation circuit 171 by 2, and generates a divided clock signal S2. The frequency dividing circuit 172 outputs the generated divided clock signal S2 to the selector 173.

  The selector 173 includes, for example, two CMOS (Complementary Metal Oxide Semiconductor) transistors that form a differential pair. The selector 173 converts the reference clock signal S1 input from the clock signal generation circuit 171 into the first and second output terminals O1 and O2 in accordance with the level of the frequency-divided clock signal S2 input from the frequency divider 172. Output from one of them.

  In this embodiment, when the divided clock signal S2 input from the frequency dividing circuit 172 is at a high level, the selector 173 turns on the first output terminal O1 and turns off the second output terminal O2, and the clock The reference clock signal S1 input from the signal generation circuit 171 is output from the first output terminal O1. On the other hand, when the divided clock signal S2 input from the frequency dividing circuit 172 is at the low level, the selector 173 turns off the first output terminal O1 and turns on the second output terminal O2, and the clock signal generation circuit 171. The reference clock signal S1 input from is output from the second output terminal O2.

  The counter 174 cyclically updates the count value C from a predetermined initial value to a predetermined final value in response to the rising edge of the first output clock signal S3 output from the first output terminal O1 of the selector 173. To do.

  In this embodiment, the counter 174 is an up counter, and counts up the count value C from “0” to “249” by 1 each time the rising edge of the first output clock signal S3 is input. go. When the counter 174 counts up the count value C to “249”, it returns to “0” and counts up again to “249”. That is, the count value C is cyclically changed from “0” → “1” →... → “249” → “0” →... Each time the rising edge of the first output clock signal S3 is input to the counter 174. Updated.

  The latch signal output circuit 175 is configured by a flip-flop circuit or the like, and the input terminal D is connected to the output terminal of the timer circuit 177 and the clock terminal Clk is connected to the second output terminal O2 of the selector 173. The latch signal output circuit 175 synchronizes the start winning signal SS input from the input terminal D with the rising edge of the second output clock signal S4 input from the clock terminal Clk, and latch signal (high level signal) SL. As output from the output terminal Q.

  FIG. 5 is a timing chart for explaining the operation of the random number generation circuit 17.

  The clock signal generation circuit 171 outputs the reference clock signal S1 shown in FIG. 5A, which rises from a low level to a high level at timings T11, T21,..., To the frequency dividing circuit 172 and the selector 173.

  The frequency dividing circuit 172 divides the inputted reference clock signal S1 by two and becomes high level during a period from T11 to T21, a period from T12 to T22,..., A period from T21 to T12, and from T22 to T13. The frequency-divided clock signal S2 shown in FIG.

  The selector 173 is input from the clock signal generation circuit 171 when the frequency-divided clock signal S2 input from the frequency-dividing circuit 172 is at a high level, that is, the period from T11 to T21, the period from T12 to T22,. The reference clock signal S1 is output from the first output terminal O1. As a result, the first output terminal O1 of the selector 173 outputs the first output clock signal S3 shown in FIG. 5C, which rises from the low level to the high level at the timings T11, T21,. The first output clock signal S3 is supplied to the selector 173.

  The counter 174 updates the count value C and outputs it to the random value storage circuit 176 every time the rising edge of the first output clock signal S3 supplied from the selector 173 is input.

  On the other hand, the selector 173 operates from the clock signal generation circuit 171 when the frequency-divided clock signal S2 input from the frequency dividing circuit 172 is at a low level, that is, during the period from T21 to T12, from T22 to T13,. The input reference clock signal S1 is output from the second output terminal O2. Thus, the second output terminal O2 of the selector 173 outputs the second output clock signal S4 shown in FIG. 5D that rises from the low level to the high level at the timing T12, T22,. The second output clock signal S4 is supplied to the latch signal output circuit 175.

  The latch signal output circuit 175 synchronizes the start winning signal SS shown in FIG. 5 (E) input from the input terminal D with the rising edge of the second output clock signal S4 supplied from the selector 173. The latch signal SL shown in F) is output.

  Thereby, the random number generation circuit 17 updates the count value C at timings T11, T21, T31 among timings T11, T12, T21, T22, T31, T32,..., And is different from the timings T11, T21, T31. At timing T22, the latch signal SL can be output.

  The random value storage circuit 176 shown in FIG. 4 is an 8-bit register, and stores a random value R that is read in a winning process in step S102 described later. The random value storage circuit 176 stores the count value C input from the counter 174 as the random value R in response to the latch signal SL input from the latch signal output circuit 175.

  FIG. 6 is a circuit diagram showing a configuration example of the random value storage circuit 176. As shown in FIG. 6, the random value storage circuit 176 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, eight Philip flop circuits 211 to 218, and eight OR circuits. 221 to 228.

  The input terminal of the AND circuit 201 is connected to the output terminal Q of the latch signal output circuit 175 and the output terminal of the NOT circuit 204, and the output terminals are the input terminal of the NOT circuit 202 and the clock terminals Clk1 of the Philip flop circuits 211 to 218. To Clk8. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the I / O port 104 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 204. An input terminal of the NOT circuit 204 is connected to an output terminal of the AND circuit 203, and an output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 221 to 228.

  The input terminals D1 to D8 of the Philip flop circuits 211 to 218 are connected to the output terminal of the counter 174. The clock terminals Clk1 to Clk8 of the Philip flop circuits 211 to 218 are connected to the output terminal of the AND circuit 201, and the output terminals Q1 to Q8 are connected to the other input terminals of the OR circuits 221 to 228, respectively.

  The input terminals of the OR circuits 221 to 228 are connected to the output terminal of the NOT circuit 204 and the output terminals of the flip-flop circuits 211 to 218, and the output terminals are connected to the I / O port 104 of the game control microcomputer 100. ing.

  The operation of the random value storage circuit 176 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the game control microcomputer 100 (when one input of the AND circuit 203 is low level), the latch signal SL is output from the latch signal output circuit 175. When input (in the example shown in FIG. 7, at timings T1, T2, and T7), the inputs of the AND circuit 201 are both at a high level, and the signal SR output from the output terminal is at a high level. The signal SR output from the AND circuit 201 is input to the clock terminals Clk1 to Clk8 of the Philip flop circuits 211 to 218.

  The Philip flop circuits 211 to 218 respond to the rising edges of the signal SR input from the clock terminals Clk1 to Clk8 and receive bit data C1 to C8 of the count value C input from the counter 174 via the input terminals D1 to D8. Are latched and stored as bit data R1 to R8 of random values, and the bit data R1 to R8 of the stored random values R are output from the output terminals Q1 to Q8.

  When the output control signal SC is not input (in the example shown in FIG. 7, the period up to the timing T3 and the period after the timing T6), one input of the AND circuit 203 is at the low level, and therefore the output is output from the output terminal. The signal SG to be output becomes a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one input terminal of the OR circuits 221 to 228.

  Thus, since one input of the OR circuits 221 to 228 is at a high level, regardless of whether the signal input to the other input terminal is at a high level or a low level, that is, an input random value Regardless of whether the values of the R bit data R1 to R8 are “0” or “1”, the signals SO1 to SO8 output from the OR circuits 221 to 228 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 176 is always “255 (= 11111111b)”, and the random value R cannot be read from the random value storage circuit 176. That is, when the output control signal SC is not input, the random value storage circuit 176 is in a non-readable (disabled) state.

  Then, when the output control signal SC is input from the game control microcomputer 100 when the latch signal SL is not input from the latch signal output circuit 175 (in the example shown in FIG. 7, from the timing T4 to the timing T6). (Period), since both inputs of the AND circuit 203 are at a high level, the signal SG output from the output terminal thereof is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminals of the OR circuits 221 to 228.

  Since one input of the OR circuits 221 to 228 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the values of the bit data R1 to R8 of the random value R inputted to the other input terminals of the OR circuits 221 to 228 are directly from the output terminals of the OR circuits 221 to 228 (the values of the bit data R1 to R8 are “1”). "1" and "0" for "0") are output. As a result, the random value R can be read from the random value storage circuit 176. That is, when the output control signal SC is input, the random number storage circuit 176 is in a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 175 before the output control signal SC is input from the game control microcomputer 100, one input of the AND circuit 203 becomes low level. After that, even when the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 7, it is output from the output terminal). The signal SG remains at a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 221 to 228.

  Thus, since one input of the OR circuits 221 to 228 is at a high level, the output from the OR circuits 221 to 228 is output regardless of whether the signal input to the other input terminal is at a high level or a low level. The signals SO1 to SO8 are all at a high level, and the random number value R cannot be read from the random value storage circuit 176 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 176 becomes incapable of receiving the output control signal SC.

  Further, when the output control signal SC is input from the gaming microcomputer 100 before the latch signal SL is input from the latch signal output circuit 175, one input of the AND circuit 201 becomes low level. Even if the latch signal SL is input while the output control signal SC is being input (in the example shown in FIG. 7, timing T5), the signal SR output from the output terminal remains at the low level. It becomes. Therefore, the signal SR input to the clock terminals Clk1 to Clk8 of the Philip flop circuits 211 to 218 does not rise from the low level to the high level, and the bit data R1 of the random value R stored in the Philip flop circuits 211 to 218. ˜R8 is not updated despite the latch signal SL being input. That is, when the output control signal SC is input, the random value storage circuit 176 becomes incapable of receiving the latch signal SL.

  The timer circuit 177 shown in FIG. 4 measures the time during which the start winning signal SS is input from the start winning port switch 70, and when the measured time reaches a predetermined time (for example, 3 ms), the timer winning signal SS is displayed. The data is output to the latch signal output circuit 175.

  In this embodiment, the timer circuit 177 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. The timer circuit 177 counts up or down the reference clock signal S1 sequentially input from the clock signal generation circuit 171 while the input is at a high level. When the count value obtained by counting up or down becomes a value corresponding to 3 ms, the timer circuit 177 determines that the input signal is the start winning signal SS, and the start winning signal SS is latched. Output to the output circuit 175.

  The main board 11 shown in FIG. 3 includes a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a control. A CPU (Central Processing Unit) 103 that performs the operation and an I / O (Input / Output) port 104 are incorporated.

  Further, as shown in FIG. 8, the game control microcomputer 100 includes a special figure holding memory 110, a jackpot determination table memory 111, a flag memory 112, and a start winning opening switch timer memory 113. .

  In the special figure holding memory 110, a condition (execution condition) for executing a variable symbol display (special symbol game) for a game ball winning the normal variable winning ball device 6 is established. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 110 includes four entries, and each entry has a holding number and a random number value R read from the random value storage circuit 176 according to the winning order in the order of winning in the normal variable winning ball apparatus 6. Are stored in association with each other. Each time the special symbol confirmation command is sent from the main board 11 to the display control board 12 and the special symbol variable display is finished once or the big hit gaming state is finished, the variable display based on the highest level information is performed. The start condition is satisfied, and variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball newly wins the normal variable winning ball apparatus 6 while the special symbol is variably displayed, the random value R read from the random value storage circuit 176 based on the winning is the highest empty. Registered in the entry.

  The jackpot determination table memory 111 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 111 stores a normal big hit determination table 121 shown in FIG. 9A and a probability change big hit determination table 122 shown in FIG. 9B.

  Whether the normal big hit determination table 121 shown in FIG. 9 (A) and the probability variation big hit determination table 122 shown in FIG. 9 (B) use the display result of the special figure game by the variable display device 4 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 121 and 122, a random value R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 122, more random numbers R are associated with the display result of “big hit” than in the normal big hit determination table 121. That is, by determining the display result of the special figure game using the probability change big hit determination table 122, it is possible to achieve a probability improvement state in which the probability of being in the big hit gaming state is higher than in the normal gaming state.

  In the flag memory 112 shown in FIG. 8, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 112 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (described later) (FIG. 12). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

  The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The start winning port switch timer memory 113 is for storing a timer value that is added or cleared in accordance with the start winning signal SS input from the start winning port switch 70.

  The switch circuit 107 shown in FIG. 3 takes in the start winning signal SS from the start winning port switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The display control board 12 performs display control for image processing in the variable display game independently of the main board 11. Based on the display control command output from the main board 11, the display control board 12 displays an image used for the variable display game on the variable display device 4, and controls turning on / off the normal symbol display 40. . In other words, the display control board 12 controls the display operation of the variable display device 4 based on the control command from the main board 11, thereby controlling the effect by the image display related to the progress of the game.

  The audio control board 13 and the lamp control board 14 are sub-side controls that execute the audio output control and the lamp output control independently of the main board 11 based on the control command transmitted from the main board 11. It is a substrate. That is, the sound control board 13 controls the sound output operation by the speakers 8L and 8R based on the control command from the main board 11, thereby controlling the effect by the sound related to the progress of the game. In addition, the lamp control board 14 controls the lighting / flashing operation of the game effect lamp 9 based on the control command from the main board 11, thereby controlling the effect of lighting, blinking or extinguishing of the lamp related to the progress of the game. . The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 10 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, interrupt processing is permitted (step S3), and then loop processing is started.

  When the CPU 103 that has executed the game control main process shown in FIG. 10 receives the interrupt request signal from the CTC and receives the interrupt request, the CPU 103 executes the game control interrupt process shown in the flowchart of FIG.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined switch process (step S11). In the switch process, it is determined whether or not the start winning signal SS input from the start winning port switch 70 via the switch circuit 107 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the start winning port switch timer memory 113. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and if necessary, warning can be generated according to the diagnosis result (step S12). Thereafter, a determination random number update process for updating a predetermined determination random number (step S13) and a display random number update process for updating a predetermined display random number (step S14) are sequentially executed.

  Next, the CPU 103 executes special symbol process processing (step S15). In the special symbol process, the corresponding process is selected and executed according to the special symbol process flag provided in the flag memory 112 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state. Following the special symbol process, the CPU 103 executes a normal symbol process (step S16). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag provided in the flag memory 112 in order to control the normal symbol display 40 in a predetermined order.

  Furthermore, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the display control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S17). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in a predetermined command transmission table, and so on, for the sub-side control board such as the display control board 12. A control signal for controlling the progress of the game is transmitted. The display control command sent from the main board 11 by the command control process is received by the CPU of the display control board 12, and the display control of the variable display device 4 and the lighting control of the normal symbol display 40 are performed according to the display control command. .

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S18). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movement of the movable blade piece in the normal variable winning ball device 6 and open / close the opening / closing plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S19). Thereafter, by executing predetermined prize ball processing, the number of prize balls is set based on the start winning signal SS input from the start winning opening switch 70, and a payout control command is output to the payout control board 15. It is possible (step S20).

  FIG. 12 is a flowchart showing the special symbol process executed in step S15. When the special symbol process is started, the CPU 103 first checks whether or not the game ball has won the normal variable winning ball device 6 by checking the timer value stored in the starting winning port switch timer memory 113. It discriminate | determines (step S101). In step S101, the CPU 103 loads the timer value stored in the starting winning a prize opening switch timer memory 113, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). As a result, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is performed a predetermined number of times (for example, twice) (for example, 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S101; Yes), the winning process is executed (step S102), and the timer value is set. clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S101; No), and the winning process is skipped.

  FIG. 13 is a flowchart showing the winning process in step S102. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S121). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S121; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S121; No), an output control signal SC is sent to the random value memory circuit 176, and the random value memory circuit 176 is controlled to be readable (enabled). (Step S122).

  Subsequently, the CPU 103 reads the random value R from the random value storage circuit 176 (step S123), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S124), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 176 is stopped, and the random number value storage circuit 176 is controlled to be unreadable (disabled) (step S125). Then, the CPU 103 adds “1” to the starting winning memory number (step S126), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S127).

  Thereafter, the CPU 103 selects one of the nine processes of steps S110 to S118 shown in FIG. 12 based on the value of the special symbol process flag stored in the flag memory 112. Below, each process of step S110-S118 is demonstrated.

  The special symbol normal process of step S110 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0”. Here, in the special figure holding memory 110, when various data such as the random number R corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S111 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 14, the CPU 103 first reads a random value R stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S131). At this time, “1” is subtracted from the reserved storage number, and the random number R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is increased by one entry. (Step S132).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S133). If the probability change is not in progress (step S133; No), the CPU 103 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table 121 as shown in FIG. 9A is set (step S134). On the other hand, if the probability change is in progress (step S133; Yes), the probability change big hit determination table 122 as shown in FIG. 9B is set (step S135).

  Based on the random number value R read in step S131, the CPU 103 determines whether or not to display the special game display result as a jackpot using the jackpot determination table 121 or 122 set in step S134 or step S135. (Step S136). If it is determined to be a big hit (step S136; Yes), the big hit state flag provided in the flag memory 112 is set to the on state (step S137), and if it is determined to be lost. (Step S136; No), the big hit state flag is cleared and turned off (Step S138). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S139).

  The confirmed symbol determination process in step S112 shown in FIG. 12 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 determines whether or not the big hit state flag provided in the flag memory 112 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S113 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 first determines whether or not the big hit state flag provided in the flag memory 112 is turned on, and whether or not it is determined to reach in the determined symbol determination process in step S112. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in the current special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 103 updates the value of the special symbol process flag to “4” which is a value corresponding to the variable display command process.

  The variable display command process of step S114 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 103 controls the variable display device 4 to start variable display for all the special symbols. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S112 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S113 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S115 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 performs settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S116 is a process executed when the value of the special symbol process flag is “6”. In this process, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S117 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S118 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the display control board 12. In addition, the CPU 103 clears the big hit state flag provided in the flag memory 112 and turns it off. Then, the value of the special symbol process flag is updated to “0”.

  As described above, according to this embodiment, the selector 173 has the reference clock signal S1 input from the clock signal generation circuit 171 when the frequency-divided clock signal S2 input from the frequency-dividing circuit 172 is at a high level. Are output from the first output terminal O1, and the first output clock signal S3 rising from the low level to the high level is supplied to the counter 174 at the timings T11, T21, T31,. On the other hand, when the divided clock signal S2 is at the low level, the reference clock signal S1 is output from the second output terminal, and the second output clock rising from the low level to the high level at the timings T12, T22, T32,. The signal S4 is supplied to the latch signal output circuit 175. The latch signal output circuit 175 synchronizes the start winning signal SS input from the start winning port switch 70 with the second output clock signal, and at timing T22, the latch signal SL rises from a low level to a high level as a random value. The data is output to the memory circuit 176.

  As a result, the random number generation circuit 17 includes the timings T11, T12, T21, T22, T31, T32,... Of the reference clock signal S1 output from the clock signal generation circuit 171 from the low level to the high level. The count value C can be updated at T21, T31,..., And the latch signal SL can be output at timings T12, T22, T32,. The random value storage circuit 176 stores the updated count value C as a random value R in response to the rising edge of the latch signal SL.

  Therefore, the random number generation circuit 17 can reliably change the update timing of the count value C by the counter 174 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 175. In addition, since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S1, even if the falling edge of the reference clock signal S1 is gentle, the update is performed. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire a random value.

  The start winning port switch 70 outputs a start winning signal SS to the main board 11 and the random number generation circuit 17 based on the fact that the game ball has won the normal variable winning ball device 6 which is the starting winning port. The CPU 103 of the main board 11 is based on the fact that the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). The winning process is executed. In this winning process, the CPU 103 sends an output control signal SC to the random value storage circuit 176 to control the random value storage circuit 176 to a readable (enable) state, and then reads the random value R from the random value storage circuit 176. . Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 176 and controls the random value storage circuit 176 to the unreadable (disabled) state, and then the read random value R becomes the predetermined determination value “ It is determined whether or not the display result of the special game by the variable display device 4 is set to the big hit gaming state by determining whether or not it coincides with “3” or the like.

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 176 to the readable state only when the CPU 103 reads the random number value R. Can do. Further, since the CPU 103 reads the random value R from the random value storage circuit 176 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  The random number generation circuit 17 does not directly input the start winning signal SS output from the start winning port switch 70 to the latch signal output circuit 175, but instead inputs it to the timer circuit 177 and inputs the start winning signal SS. The time is measured, and when the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 175. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 175 from erroneously outputting the latch signal SL to the random value storage circuit 176 due to the influence of noise or the like. Since the timer circuit 177 is set to “3 ms” which is shorter than “4 ms” between the executions of the two timer interrupt processes, the random number value R read from the random value storage circuit 176 by the CPU 103 is the previous value. It is possible to prevent the same value as the random value R read at the time of winning a prize.

  In addition, when the latch signal is input from the latch signal output circuit 175, the random value storage circuit 176 converts the output control signal (high level signal) SC input from the game control microcomputer 100 into a low level signal. By performing the conversion, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R from the random value storage circuit 176 when the random value R stored in the random value storage circuit 176 is updated. 1 can reliably and stably update the random value R.

  Further, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 176 converts the latch signal (high level signal) SL input from the latch signal output circuit 175 into a low level signal. By converting to, the latch signal SL is controlled so as not to be received. This prevents the random number value R stored in the random value storage circuit 176 from being updated when the game control microcomputer 100 reads the random value R from the random value storage circuit 176. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, the selector 173 receives the reference clock signal S1 input from the clock signal generation circuit 171 from the first output terminal O1 when the frequency-divided clock signal S2 input from the frequency divider circuit 172 is at a high level. When the frequency-divided clock signal S2 is low level, the reference clock signal S1 is output from the second output terminal O2. However, the present invention is not limited to this, and the selector 173 outputs the reference clock signal S1 from the first output terminal O1 when the divided clock signal S2 is at low level, and the divided clock signal S2 is at high level. In this case, the reference clock signal S1 may be output from the second output terminal O2.

  In the above embodiment, the counter 174 is an up counter. However, the present invention is not limited to this, and may be a down counter. Further, the numerical value updating means is not limited to the counter 174, and may be a pseudo random number generation circuit. In addition, the connection between the output terminal of the bit data C1 to C8 of the count value C of the counter 174 and the input terminal of the bit data C1 to C8 of the count value C of the random value storage circuit 174 may be changed. Then, the randomness of the count value C input to the random value storage circuit 176 can be improved.

  Furthermore, in the above embodiment, the random value storage circuit 176 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 221 to 228 to control the reception of the latch signal SL and the output control signal SC and output the random value R. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 176 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 104 and the latch signal output circuit 175, and the latch signal SL. In response to the input of the output control signal SC and the path to the I / O port 104 and the latch signal output circuit 175, the enable / disable control of the latch signal SL and the output control signal SC is performed. Also good.

  In the above embodiment, the timer circuit 177 is activated in response to the input of the high level signal, and the reference sequentially input from the clock signal generation circuit 171 while the input is at the high level. The clock signal S1 is up-counted or down-counted, and when the up-counted or down-counted value becomes a value corresponding to a predetermined time, the input signal is determined to be a high level signal and a latch signal is output. Output to the circuit 175. However, the present invention is not limited to this, and the timer circuit 177 measures the time when the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. Any signal may be used as long as it outputs the winning signal SS to the latch signal output circuit 175.

  Further, in the above embodiment, the timer circuit 177 measures the signal input time using the reference clock signal S1 sequentially input from the clock signal generation circuit 171, but the present invention is not limited to this. The timer circuit 177 may use a clock signal obtained by dividing the reference clock signal S1 or a clock signal output from a clock signal generation circuit different from the clock signal generation circuit 171. In the above embodiment, the timer circuit 177 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, but from the 4 ms which is the execution time of the two timer interrupt processes. Can be arbitrarily set as long as the time is short.

  In the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 177 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  In the above-described embodiment, the gaming machine has a variable display start condition (for example, the previous variable display and jackpot game in the variable display device 4) after the variable display execution condition (for example, winning in the normal variable winning ball device 6) is established. A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the establishment of (end of state). This is a pachinko gaming machine that controls a specific gaming state (for example, a big hit gaming state) advantageous to the player when a predetermined specific display result is obtained.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 15, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 15 uses a predetermined start signal as a start signal output means of the present invention based on an operation of the start lever 1011 by a player, a game control means (for example, a main board) or a random number generation means ( For example, a start switch (not shown) for outputting to a random number generation circuit is provided. Note that the liquid crystal display 1001 shown in FIG. 15 functions as rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  1, 2 and 15, block configurations shown in FIGS. 3, 4 and 8, timing chart configurations shown in FIGS. 5 and 7, circuit configurations shown in FIG. 6, and FIG. 9. The table configurations shown and the flowchart configurations shown in FIGS. 10 to 14 can be arbitrarily changed and modified without departing from the spirit of the invention.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows the structural example of a random number generation circuit. 3 is a timing chart for explaining the operation of a random number generation circuit. It is a circuit diagram which shows the structural example of a random value storage circuit. 3 is a timing chart for explaining the operation of a random value storage circuit. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the structural example of the table for jackpot determination. It is a flowchart which shows a game control main process. It is a flowchart which shows a game control interruption process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Variable display device
6 ... Ordinary variable winning ball device
7 ... Special variable winning ball device 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board
17 ... Random number generation circuit 21, 22 ... Solenoid
40 ... Normal symbol display
70 ... Start prize opening switch 100 ... Microcomputer for game control 101 ... ROM
102 ... RAM
103 ... CPU
104 ... I / O port 107 ... Switch circuit 108 ... Solenoid circuit 110 ... Special figure holding memory 111 ... Table game for jackpot judgment 112 ... Flag memory 113 ... Start winning port switch timer memory 121 ... Table for jackpot judgment at normal time 122 ... Certain change Big hit determination table 171 ... Clock signal generation circuit 172 ... Frequency division circuit 173 ... Selector 174 ... Counter 175 ... Latch signal output circuit 176 ... Random value storage circuit 177 ... Timer circuits 201, 203 ... AND circuits 202, 204 ... NOT circuit 211-218 ... Philip flop circuits 221-228 ... OR circuit 1000 ... slot machine 1001 ... liquid crystal display 1002 ... variable display device 1011 ... start lever

Claims (4)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays a plurality of types of identification information, each of which can be identified, is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state advantageous to the player when the result is obtained,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
A start signal output means for outputting a start signal to the game control means and the random number generation means based on the execution condition being satisfied;
With
The random number generating means includes
Clock signal generating means for generating and outputting a reference clock signal of a predetermined period;
Numerical value updating means for updating numerical data at a first timing among a plurality of timings at which the reference clock signal output from the clock signal generating means rises from a low level to a high level at each predetermined period;
Latch signal output means for outputting a start signal input from the start signal output means as a latch signal at a second timing different from the first timing among the plurality of timings;
Random value storage means for storing numerical data updated by the numerical value updating means as a random value in response to a latch signal input from the latch signal output means;
Including
The game control unit reads a random number value from the random value storage unit based on the input of the start signal from the start signal output unit, and whether the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display is a specific display result by determining whether or not
The random number generating means includes
A frequency dividing means for dividing the reference clock signal input from the clock signal generating means to generate a divided clock signal, and outputting the generated divided clock signal;
When the frequency-divided clock signal input from the frequency dividing means is at one of a high level and a low level, the reference clock signal input from the clock signal generating means is output from the first output terminal. By outputting, the first clock signal rising from the low level to the high level at the first timing is supplied to the numerical value updating means, and the divided clock signal inputted from the frequency dividing means is high level and low level. When the reference clock signal is at a level different from that when the reference clock signal is output from the first output terminal, the reference clock signal input from the clock signal generation means is output from the second output terminal. Accordingly, the second clock signal rising from the low level to the high level at the second timing is converted into the latch signal. A clock signal supply means for supplying the force means,
Including
The numerical value updating means updates the numerical data at the first timing by responding to the rising edge of the first clock signal supplied from the clock signal supply means,
The latch signal output means synchronizes the start signal input from the start signal output means with the rising edge of the second clock signal supplied from the clock signal supply means, so that the latch signal is output at the second timing. outputs a,
The game control means outputs an output control signal to the random value storage means so that the random number value storage means can be read before the display result determination means reads the random value from the random value storage means. Read control for stopping the output of the output control signal to the random value storage means and controlling the random value storage means to the unreadable state after the display result determination means reads the random value from the random value storage means Including means,
The random value storage means includes an output control signal reception control means for maintaining an unreadable state even when an output control signal is outputted from the read control means when a latch signal is inputted from the latch signal output means. ,
A gaming machine characterized by that. The random number generation means measures a time during which a start signal is input from the start signal output means, and outputs a start signal to the latch signal output means when the measured time reaches a predetermined time. Including means,
The gaming machine according to claim 1. The game control means includes a timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal input periodically.
The display result determining means is based on the fact that a start signal is continuously input from the start signal output means while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes. Read the random value from the random value storage means,
The timer means includes
Setting means for setting, as the predetermined time, a time shorter than a time when a predetermined number of timer interrupt processes are executed by the timer interrupt process executing means;
When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.
The gaming machine according to claim 2, wherein: The random value storage means includes latch signal reception control means for controlling the latch signal output from the latch signal output means to be in an unreceivable state when an output control signal is input from the read control means.
The gaming machine according to any one of claims 1 to 3, wherein

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