JP2006263013A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which achieves the accurate and stable acquisition of random numbers. <P>SOLUTION: A clock signal generation circuit 172 latches and outputs a feed back signal from an opposite phase output terminal Q (bar) through a normal phase output terminal Q responding to the leading edge of the reference clock signal S0 while outputting an inversion signal through the opposite phase output terminal Q (bar). An i-th counter 173i (i=1, 2 and 3) updates counts Ci at the rising timing of the output signal from the normal phase output terminal Q and an ith latch signal output circuit 174i outputs a latch signal SLi at the rising timing of the output signal from the opposite phase output terminal Q (bar). In this manner, a random number generation circuit 17 can make a difference between the timings of updating and latching the counts Ci. As a result, a pachinko game machine enables the accurate and stable acquisition of the random numbers for judging the jackpot. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified A variable display device that variably displays is provided, and when the display result of the identification information becomes a specific display result, it is controlled to a specific gaming state advantageous to the player, and when the predetermined condition is satisfied, the specific gaming state is ended. The present invention relates to a gaming machine that controls to a higher probability state than the normal gaming state in which the probability of the specific display result after being different from that in the normal gaming state.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  Currently, in game machines, a random number used to determine whether or not to make a “big hit” (a big hit determination random number) is generated by the CPU executing a predetermined application program. However, such a random number generation method has a problem that the processing load on the CPU at the time of generation increases.

To solve this problem, a game machine that generates a big hit determination random number using a random number generation circuit, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. However, a gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 1).
JP-A-7-124296 (page 3-4, FIG. 1).

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). A gaming machine that stores random numbers is also disclosed (for example, see Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2).

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  Further, in the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gentle, the rising edge of the inverted clock pulse also becomes gentle. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reliably and stably obtaining a random value.

  In order to achieve the above object, the gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a special symbol display) after a variable display execution condition (for example, a winning to the normal variable winning ball apparatus 6) is established. Variable display that variably displays a plurality of types of identification information (for example, special symbols and decorative symbols), each of which can be identified based on the establishment of the previous variable display and end of jackpot gaming state in the device 41 and the image display device 4. A display device (for example, special symbol display 41 or image display device 4) is provided, and when the display result of the identification information becomes a specific display result, it is controlled to a specific game state (for example, a big hit game state) advantageous to the player, Further, when a predetermined condition is satisfied, a high probability state in which the probability that the specific display result is obtained after the specific game state is ended is higher than that in the normal game state different from the specific game state. A gaming control microcomputer (for example, a pachinko gaming machine 1) that includes a game control CPU (for example, CPU 103) for controlling the progress of the game (for example, a gaming control microcomputer mounted on the main board 11) 100), a random number generation circuit (for example, the random number generation circuit 17 or 27) for generating a random number (for example, the big hit determination random number R1), and the execution signal for the variable display is satisfied, Start signal output means (for example, left / middle / right start port switches 71 to 73) for outputting to the microcomputer, and the random number generation circuit includes a reference clock signal (for example, reference clock signal S0) having a predetermined period. A reference clock signal output means (for example, a reference clock signal output circuit 171), and a reference clock signal based on the reference clock signal. Clock signal generating means (for example, a clock signal generating circuit 172) that generates a plurality of signals having the same period and different phases, and the clock signal generating means receives the reference clock signal from the reference clock signal output means. Are input to the clock terminal (for example, the input terminal CK of the clock signal generation circuit 172), the input terminal to which the first signal is input (for example, the input terminal D of the clock signal generation circuit 172), and the first signal At a timing when the change state changes every predetermined period of the reference clock signal input from the clock terminal (for example, timing T10, T11, T12,..., When the reference clock signal S0 rises from a low level to a high level). A first output terminal for outputting a synchronized signal (for example, a positive phase output terminal of the clock signal generation circuit 172) Child Q) and a second output terminal for outputting a signal having the same period and a different phase as the signal output from the first output terminal (for example, the reverse phase output terminal Q (bar) of the clock signal generation circuit 172) And the clock signal generation means connects the second output terminal and the input terminal to thereby connect a first clock signal (for example, a clock signal for counting) output from the first output terminal. S1) and a second clock signal (for example, latch count signal S2) output from the second output terminal and having the same period and different phase as the first clock signal, and generating the random number The circuit has a first timing at which the first clock signal generated by the clock signal generating means changes in a predetermined manner (for example, the count clock signal S1 is changed from low level to high level). , Etc.), the specific display result determination numerical data (for example, count values C1 to C3) used when determining whether or not the display result of variable display is the specific display result. Specific display result determination numerical data (for example, first to third counters 1731 to 1733) to be updated, and a second clock signal generated by the clock signal generation means changes in the predetermined manner. Latch signal output means (for example, first to third latch signal output circuits) for outputting a latch signal at timing (for example, timings T11, T13, T15,... When the latch clock signal S2 rises from low level to high level) 1741 to 1743) and the latch signal input from the latch signal output means, Random number storage means (for example, first to third random value storage circuits 1751 to 1753) for storing the specific display result determination numerical data updated by the specific display result determination numerical data update means as random numbers. The game control microcomputer receives a start signal from the start signal output means (for example, the CPU 103 determines Yes in step S141, S143, or S145, or step S1142, S1146, or S1150). The random display unit for reading random numbers from the random number storage unit (for example, the part where the CPU 103 executes the process of step S202 or the process of S1211) and the variable display start condition are satisfied. The random number value read by the random value reading means is Whether or not to make the display result in the variable display a specific display result by determining whether or not it matches a predetermined specific display result determination value (for example, “2001 to 2184”, “2001 to 3104”, etc.) Specific display result determination (for example, the part where the CPU 103 executes the jackpot determination process of step S304), and whether or not the predetermined condition for controlling to the high probability state is satisfied after the specific gaming state ends. High probability state condition determination numerical data update means (for example, a portion where the CPU 103 executes the processing of steps S131 to S133) for updating the high probability state condition determination numerical data used in the determination, and the high probability state condition determination Numerical data for high probability state condition determination storing numerical data for high probability state condition determination updated by the numerical data update means The high probability state condition determination numerical data updated by the storage means (for example, probability change determination random number counter 116) and the high probability state condition determination numerical data update means are extracted from the high probability state condition determination numerical data storage means. Numerical data extraction means for high probability state condition determination (for example, a portion where the CPU 103 executes the process of step S307) and numerical data for high probability state condition determination extracted by the numerical data extraction means for high probability state condition determination When the indicated value matches a predetermined high probability state condition determination value (for example, an odd value), high probability state condition determination means for determining that the predetermined condition is satisfied (for example, the CPU 103 executes the probability variation determination process in step S309). And the high probability state condition determination means determine that the predetermined condition is satisfied. After the specific gaming state is finished, it is updated by a high probability state control means (for example, the part where the CPU 103 executes the process of step S311) for controlling to the high probability state and the numerical data update means for high probability state condition determination. Initial value changing numerical data updating means (for example, CPU 103) for updating initial value changing numerical data (for example, initial value determining random number R5) used for determining an initial value for updating the high probability state condition determining numerical data. Is a portion for executing the initial value determining random number update process in step S14, and initial value changing numerical data storage means (for example, initial value) for storing the initial value changing numerical data updated by the initial value numerical data updating means. A random number counter for determination 117) and high probability state condition determination by updating by the high probability state condition determination numerical data updating means. A one-round determination means (for example, a portion where the CPU 103 executes the processing of steps S134 and S135) for determining whether or not the value indicated by the regular numerical data has made one round, and the one-round determination means for determining a high probability state condition When it is determined that the value indicated by the numerical data has made one round (for example, when the CPU 103 determines Yes in the process of step S135), the initial value changing data updated by the initial value changing numerical data updating means Numerical data is extracted by the initial value changing numerical data extracting means (for example, the part where the CPU 103 executes the process of step S136) and the initial value changing numerical data extracting means for extracting the numerical data from the initial value changing numerical data storage means. The initial value changing numerical data thus obtained is updated by the high probability state condition determining numerical data updating means. It includes an initial value changing means for setting the initial value data of use numerical data (e.g., portions CPU103 is executing the processing in steps S137 and S138), and characterized in that.

3. The gaming machine according to claim 2, wherein the game control microcomputer executes a timer interrupt process in response to an interrupt request signal input periodically (for example, every 2 ms). Execution means (for example, a portion where the CPU 103 executes game control interrupt processing);
Whether or not a start signal is continuously input from the start signal output means while the timer interrupt process execution means is executing a predetermined number of times (for example, twice) of timer interrupt processing (for example, for 4 ms). It is determined that the start signal is continuously input by the start signal input determining means (for example, the part where the CPU 103 executes the process of step S103, S108, or S113) and the start signal input determining means. (For example, when the CPU 103 determines Yes in step S1142, S1146, or S1150), a latch start signal output means for outputting a latch start signal to the random number generation circuit (for example, the CPU 103 performs the process of step S1202). The latch signal output means is the latch start signal output means. The input latch start signal is output to the random value storage means as the latch signal, and the random value read means outputs the latch start signal by the latch start signal output means. The random number value is read out from the random number value storage means (for example, the CPU 103 executes the process of step S1211).

  In the gaming machine according to claim 3, the start signal output means further outputs a start signal to the random number generation circuit based on the fact that the variable display execution condition is satisfied, and the random number generation circuit Timer means for measuring the time when the start signal is input from the start signal output means, and outputting the start signal to the latch signal output means when the measured time reaches a predetermined time (for example, 3 ms) (For example, first to third timer circuits 1761 to 1763), and the latch signal output means outputs a start signal input from the start signal output means as the latch signal.

  5. The gaming machine according to claim 4, wherein the game control microcomputer executes a timer interrupt process in response to an interrupt request signal input periodically (for example, every 2 ms). Including an execution means (for example, a portion where the CPU 103 executes a game control interrupt process), and the random value reading means is configured to execute a timer interrupt process a predetermined number of times (for example, twice) by the timer interrupt process execution means. The random number value is read from the random value storage means based on the fact that the start signal is continuously input from the start signal output means while the timer means executes the timer interrupt processing. Setting means (for example, the first to third timer circuits 1761 to 1763 set the time shorter than the time when the timer interruption process is executed by the means for a predetermined time as the predetermined time. When the measured time reaches a time set as a predetermined time by the setting means. A start signal is output to the latch signal output means.

  In the gaming machine according to claim 5, the latch signal output means is configured to detect the start signal output from the start signal output means (for example, the CPU 103 performs the process of step S103, S108, or S113). When the determination is Yes), the latch signal is output to the random value storage means, and the game control microcomputer responds to an interrupt request signal periodically (for example, every 2 ms), The timer interrupt process execution means (for example, the part where the CPU 103 executes the game control interrupt process) that executes the interrupt process and the input from the start signal output means are turned on each time the timer interrupt process is executed. A switch-on process execution means (for example, the CPU 103 executes the switch process in step S11). The high probability state condition determination numerical data extraction means performs a predetermined number of times that the input from the start signal output means is in the ON state in the switch-on process. High probability updated by the high probability state condition determination numerical data updating means (for example, when the CPU 103 determines Yes in step S103, S108, or S113) when performed continuously (for example, twice) The numerical data for state condition determination is extracted from the high probability state condition determination numerical data storage means (for example, the CPU 103 executes the process of step S308).

  The gaming machine according to claim 6 includes a plurality of start signal output means (for example, the first start port switch 71 corresponding to the left ordinary variable winning ball device 6L and the central ordinary variable winning ball device 6C). A corresponding second starting port switch 72 and a third starting port switch 73 corresponding to the right ordinary variable winning ball apparatus 6R), the specific display result determining numerical data updating means, and the latch signal. A plurality of output means and random number storage means are provided corresponding to the start signal output means (for example, the first counter 1731 and the first latch signal corresponding to the first start port switch 71). The output circuit 1741 and the first random value storage circuit 1751 correspond to the second start port switch 72, and the second counter 1732, the second latch signal output circuit 1742, and the second random value storage circuit. 1752 is provided with a third counter 1733, a third latch signal output circuit 1743, and a third random value storage circuit 1753 corresponding to the third start port switch 73, respectively, The display result determination numerical data updating means uses the first and second clock signals generated in common by the clock signal generation means based on the reference clock signal, and independently uses the specific display result determination numerical values. The data is updated (for example, the first counter 1731 has the count value C1, the second counter 1732 has the count value C2, the third counter 1733 has the count value C3, and the count clock signal S1 and the latch clock signal, respectively. S2 is commonly used and updated independently), and a plurality of the latch signal output means each of the corresponding start signal output means (For example, the first latch signal output circuit 1741 uses the start winning signal SS1 from the first start port switch 71 as the latch signal SL1, and the second latch signal output circuit 1742 outputs the latch signal SL1). The start winning signal SS2 from the second start port switch 72 is output as the latch signal SL2, and the third latch signal output circuit 1743 outputs the start winning signal SS3 from the third start port switch 73 as the latch signal SL3. ), A plurality of the random value storage means, respectively, in response to the latch signal from the corresponding latch signal output means, the specific display result determination updated by the corresponding specific display result determination numerical data update means Numerical value data is stored as a random value (for example, the first random value storage circuit 1751 is responsive to the latch signal S1. The second random number value storage circuit 1752 is responsive to the latch signal S2 and the third random number value storage circuit 1753 is responsive to the latch signal S3 to determine the count value C3. Stored as the value of the random number R1 for use).

  In the gaming machine according to claim 7, the game control microcomputer is updated in numerical data (synchronized with specific display result determination numerical data updated by the specific display result determination numerical data update means). For example, when the CPU 103 executes the process of step S206, numerical data acquisition means (for example, the CPU 103 of step S222) acquires a reach determination random number R2 whose value is updated in synchronization with the value of the big hit determination random number R1. A predetermined effect is executed by determining whether or not the value indicated by the numerical data acquired by the numerical data acquisition means matches a predetermined effect determination value (for example, “8”). Effect determining means for determining whether or not to perform (for example, a portion where the CPU 103 executes the reach determination processing in step 223); Including the.

  In the gaming machine according to claim 8, a frequency dividing unit (for example, a frequency divider) that takes in and divides at least one of the reference clock signal, the first clock signal, and the second clock signal. When the clock signal frequency-divided by the frequency dividing circuit 181) and the frequency dividing means is not input for a predetermined period or longer, an abnormal signal (for example, reset) is indicated as a signal indicating that an abnormality has occurred in the operating state of the random number generating circuit. And an abnormal signal output means (for example, a reset IC 182 with a watchdog) that outputs a signal SR) to the game control microcomputer, and further includes a random number generation circuit monitoring means (for example, the monitoring circuit 18). The computer uses an abnormal signal determining means (for example, an abnormal signal determining means for determining whether an abnormal signal is output from the abnormal signal output means (for example, When the PU 103 determines that an abnormal signal has been output by the abnormal signal determination means (for example, when the CPU 103 determines Yes in the process of step S121). And an abnormal process executing means (for example, a part where the CPU 103 executes the processes of steps S122 and S123).

  The inventions according to claims 1 to 8 of the present application have the following effects.

According to the configuration of the first aspect, the random number generation circuit generates the first clock signal and the second clock signal having the same period and different phases, and the first clock signal changes in a predetermined manner. The specific display result determination numerical data is updated at the first timing, and the latch signal is output at the second timing when the second clock signal changes in a predetermined manner. In this way, the random number generation circuit can reliably change the update timing of the specific display result determination numerical data and the latch timing of the specific display result determination numerical data. The random value can be acquired reliably and stably.
In addition, the game control microcomputer uses the specific display result determination numerical data (random number value) updated by the random number generation circuit to determine whether or not to obtain the specific display result, while in a high probability state. Is determined using the high probability state condition determination numerical data updated by the high probability state condition determination numerical data update means of the game control microcomputer. In this way, by using numerical data with different update methods for determining whether or not to obtain a specific display result and determining whether or not to obtain a high probability state, the results of these two determinations have periodicity. Since it can prevent that it arises, the randomness between determination results can be improved.
Furthermore, the game control microcomputer changes the initial value of the high probability state condition determination numerical data updated by the high probability state condition determination numerical data update means every time the value is made one round, thereby determining the determination result. The randomness between them can be further enhanced.

  According to the configuration of the second aspect, the game control microcomputer indicates that the start signal is continuously input while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes. When the determination is made by the start signal determination means, a latch start signal is output to the random number generation circuit. Therefore, the game control microcomputer can prevent the latch start signal output means from erroneously outputting the latch start signal to the random number generation circuit due to the influence of noise or the like. Further, the specific display result determination means reads the random number value from the random value storage means in the timer interruption process after the latch start signal output means outputs the latch start signal. It is possible to prevent the numerical value from being the same as the previously read random number value.

  According to the configuration of the third aspect, instead of directly outputting the start signal input from the start signal output means to the latch signal output means, the input time of the start signal is measured by the timer means, When the set time is reached, a start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting the latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration of claim 4, since the timer means is set as the predetermined time shorter than the execution time of the predetermined number of timer interruption processes by the timer interruption process execution means, the random value It is possible to prevent the random number value read by the reading means from the random value storage means from being the same as the random value read last time.

  According to the configuration of the fifth aspect, the random number generation circuit latches the specific display result determination numerical data and disturbs the random value storage means when the start signal output from the start signal output means is detected. While being stored as a numerical value, the gaming control microcomputer determines that the input from the start signal output means is in the ON state in the switch-on process, and the high probability state condition is The determination numerical data is extracted from the high probability state condition determination numerical data storage means. Thus, the game control microcomputer extracts the specific display result determination numerical data (random number value) from the random number generation circuit, and the high probability state condition determination numerical data from the high probability state condition determination numerical data storage means. Since it is possible to make the timing for extracting a different, it is possible to prevent fraud by a malicious player.

According to the configuration of the sixth aspect, when a plurality of start signal output means are provided, the specific display result determination numerical data update means, the latch signal output means, and the random value storage means each output the start signal. Since a plurality of units are provided corresponding to the means, even when the variable display execution conditions corresponding to the plurality of start signal output units are satisfied at the same time, the storage of the specific display result determination numerical data in the random value storage unit is Each is executed independently. As a result, the game control microcomputer can extract random numbers from a plurality of random number storage means without shifting the timing, and thus can prevent the player from feeling unfair. .
Even when a plurality of start signal output means are provided, the reference clock signal output means and the clock signal generation means can be used in common, so that an increase in manufacturing cost can be suppressed.

According to the configuration described in claim 7, it is determined whether or not to execute the predetermined effect based on the numerical data updated in synchronization with the random value read from the random value storage means. Therefore, when a predetermined effect is not executed over a long period of time, or when a predetermined effect is executed over a long period of time, it can be estimated that a failure has occurred in the random number generation circuit, and a failure has occurred in the random number generation circuit It is possible to prevent the player from suffering a significant disadvantage. Here, by setting the probability that the predetermined effect is executed higher than the probability that the variable display result of the identification information becomes the specific display result, the random number generation circuit fails when the specific display result is not obtained over a long period of time. It is possible to estimate the occurrence of a failure within a shorter period than when it is estimated that the error has occurred.
Further, since a special configuration for monitoring the random number value read from the random value storage means is not necessary, an increase in manufacturing cost can be suppressed.

  According to the configuration of the eighth aspect, when an abnormality occurs in the operating state of the random number generation circuit, an abnormality signal is output from the abnormality signal output means to the game control microcomputer. The gaming control microcomputer executes a predetermined abnormality process based on the determination that the abnormal signal has been output by the abnormal signal determination means, thereby causing an abnormality in the random number generation circuit. Thus, it is possible to prevent a situation in which the player is disadvantaged.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. An image display device 4 is provided at almost the center position of the game area so as to display the decorative symbol as variable identification information. On the upper side of the image display device 4, a special symbol display 41 is provided, and on the lower side, left, middle and right ordinary variable winning ball devices (start winning ports) 6L, 6C, 6R are arranged. Has been. A special variable winning ball apparatus (large winning opening) 7 is disposed below the central ordinary variable winning ball apparatus 6C. In addition, a normal symbol display 42 is provided on the right side of the special variable winning ball apparatus 7.

  The special symbol display 41 is composed of, for example, a 7-segment LED, and the execution condition is, for example, that a game ball wins one of the left, middle, and right ordinary variable winning ball devices 6L, 6C, 6R. In the special game, the variable symbol special symbol composed of numbers, characters, symbols and the like is started to be displayed, and when a predetermined time elapses, the fixed symbol which is the variable symbol variable display result is stopped and displayed (derived display).

  The image display device 4 includes an LCD (Liquid Crystal Display) module that variably displays a symbol as identification information by a plurality of variable display units. For example, the special symbol display 41 starts variable display of the special symbol. When this is done, variable display of three display symbols (decorative symbols) composed of numbers, letters, symbols, etc. is started, and the fixed symbol is stopped and displayed as a variable symbol display result of the special symbol on the special symbol indicator 41. Sometimes, the display symbols are determined in the order of left, right, and middle. The image display device 4 has four start memory displays for displaying the number of effective winning balls, that is, the starting memory number, which are entered in any of the left, middle and right variable variable winning ball devices (start winning ports) 6L, 6C, 6R. An area may be provided. Further, the starting memory number may be specified by a display (start winning memory display) provided separately from the image display device 4. For example, it is only necessary that the start winning memory indicator is constituted by an LED, a lamp, and the like, and that the display format of the LED and the lamp is controlled on the main board 11 side so that the start winning memory number can be specified.

  The normal symbol display 42 is configured to include a light emitting diode (LED) and the like, and is turned on, blinked, colored, etc., in a normal diagram game in which a game ball starts through a passing gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is "winning", and the electric tulips constituting the left, middle and right normal variable winning ball devices 6L, 6C, 6R are displayed. The movable blade piece is controlled to tilt until a predetermined time elapses.

  The left, middle, and right ordinary variable winning ball devices 6L, 6C, and 6R are respectively controlled to move between a vertical (normally open) position and a tilted (expanded open) position by solenoids 21 to 23 (FIG. 2). A tulip-shaped accessory (ordinary electric accessory) having a movable wing piece is constructed. The winning balls that have entered the left, middle, and right ordinary variable winning ball devices 6L, 6C, and 6R are guided to the back of the game board 2, and are respectively operated by left, middle, and right start-up switches 71 to 73 (FIG. 2). Detected. The special symbol variable display 110, which will be described later up to a predetermined number of times (four times in the present embodiment), is displayed for special symbols based on the winning of game balls on the left, middle, and right ordinary variable winning ball devices 6L, 6C, 6R. (FIG. 3).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 24 (FIG. 2). This opening / closing plate is normally closed, and a special symbol game is performed by the special symbol display 41 based on the winning of the game ball in any of the left, middle, and right ordinary variable winning ball devices 6L, 6C, 6R. As a result, when the big hit gaming state is reached, the solenoid 24 opens the winning area (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. The game ball that falls in the game area during its opening is received. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit (for example, a count switch). In response to the detection of the winning ball, a predetermined number of winning balls are paid out by a main board 11 and a predetermined payout control board described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  Further, on the back surface of the pachinko gaming machine 1, main boards such as a power supply board 10, a main board 11, and an effect control board 12 are arranged at appropriate positions.

  FIG. 2 is a block diagram showing a system configuration example centering on the main board 11 and the effect control board 12. 2 also shows the power supply board 10, the random number generation circuit 17, the monitoring circuit 18, the left / middle / right start port switches 71 to 73, and the like.

  The left / middle / right start port switches 71 to 73 are based on detecting the winning of a game ball to the left / middle / right ordinary variable winning ball devices 6L, 6C, 6R, which are start winning ports, respectively. The start winning signals (high level signals) SS1 to SS3 are output to the main board 11 and the random number generation circuit 17.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 includes a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. Further, the main board 11 is connected with wiring to the effect control board 12 and wiring from the left, middle, and right start port switches 71 to 73. The main board 11 is also connected to a wiring from a winning opening switch 74 for detecting a winning of a game ball to other winning openings such as a special variable winning ball apparatus 7 which is a large winning opening. Further, on the main board 11, a solenoid 21 for performing movable control of the movable blade pieces in the left, middle and right ordinary variable winning ball devices 6L, 6C, 6R and opening / closing control in the special variable winning ball device 7 is provided. Wirings to ˜24 are connected.

  The game control microcomputer 100 is, for example, a one-chip microcomputer, and is controlled according to a ROM (Read Only Memory) 101 for storing a game control program, a RAM (Random Access Memory) 102 used as a work memory, and the program. A CPU (Central Processing Unit) 103 and an I / O (Input / Output) port 104 are included. The game control microcomputer 100 has a function for generating random numbers used in a special game, a function for outputting and transmitting control commands as examples of command information to the effect control board 12, and a special symbol display 41. It has a function of performing display control, a function of performing on / off control of the normal symbol display 42, and the like.

  The control command transmitted from the main board 11 to the effect control board 12 is an effect control command transmitted as an electrical signal using, for example, signal lines of the effect control signals CD0 to CD7. The effect control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). As this effect control command, for example, an error effect start command for instructing the start of an error effect is prepared in advance.

  As shown in FIG. 3, the game control microcomputer 100 includes a special figure holding memory 110, a switch timer memory 111, a jackpot determination table memory 112, a variable display pattern determination table memory 113, and a reach determination random number. A counter 114, a variable display pattern determining random number counter 115, a probability variation determining random number counter 116, an initial value determining random number counter 117, an initial value buffer memory 118, and a flag memory 119 are provided.

  The special figure holding memory 110 is a condition for executing a variable display of special symbols (special figure game) when a game ball wins one of the left, middle and right normal variable winning ball devices 6L, 6C, 6R ( Memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as the execution condition is satisfied but the previous variable display is being executed It is. The special figure holding memory 110 includes four entries, and each entry has a holding number, left, middle, and right in the order of winning in any of the left, middle, and right ordinary variable winning ball devices 6L, 6C, and 6R. Acquired from one of the first to third random number value storage circuits 1751 to 1753 (FIG. 9) of the random number generation circuit 17 depending on which of the right ordinary variable winning ball devices 6L, 6C, 6R is won. The value of the jackpot determination random number R1 is stored in association with each other. Each time the special symbol variable display by the special symbol display 41 is finished once or the big hit gaming state is finished, the variable display start condition based on the top information is established, and the top information is displayed. Based on the variable display is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball newly wins one of the left, middle, and right ordinary variable winning ball devices 6L, 6C, 6R while the special symbol is variably displayed, the left, middle, and right ordinary variable winning balls The value of the jackpot determination random number R1 read from any one of the first to third random value storage circuits 1751 to 1753 (FIG. 9) based on the winning of any of the devices 6L, 6C, 6R is the highest. Registered in the upper empty entry.

  In the switch timer memory 111, the start winning signals SS1 to SS3 input from the first to third start port switches 71 to 73 and the detection signals input from other winning port switches 74 are on or off. A plurality of switch timers to be added or cleared depending on whether they are in a state are stored.

  The jackpot determination table memory 112 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 112 stores a normal big hit determination table 120 shown in FIG. 4A and a probabilistic change big hit determination table 121 shown in FIG. 4B.

  The normal big hit determination table 120 shown in FIG. 4 (A) and the probability variation big hit determination table 121 shown in FIG. 4 (B) use the special symbol display result of the special symbol display 41 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 120 and 121, the value of the jackpot determination random number R1 and setting data indicating the display result of the special figure game are stored in association with each other. In the probability variation big hit determination table 121, more values of the big hit determination random number R1 are associated with the display result of “big hit” as compared to the normal big hit determination table 120. That is, by determining the display result of the special figure game using the probability change jackpot determination table 121, it is possible to achieve a probability improvement state in which the probability of becoming a big hit gaming state is higher than in the normal gaming state.

  In this embodiment, in the normal-time big hit determination table 120 shown in FIG. 4A, “2001 to 2184” among the values “0 to 65335” of the big hit determination random number R1 generated from the random number generation circuit 17 is stored. Corresponding to the display result of “big hit”. On the other hand, in the probability variation jackpot determination table 121 shown in FIG. 4B, “2001 to 3104” among the values “0 to 65335” of the jackpot determination random number R1 generated from the random number generation circuit 17 is “big hit”. It is associated with the display result.

  The variable display pattern determination table memory 113 shown in FIG. 3 stores a plurality of variable display patterns used in the special figure game. Specifically, the variable display pattern determination table memory 113 includes a normal variable display pattern determination table 130 shown in FIG. 5A, a reach variable display pattern determination table 131 shown in FIG. The big hit variable display pattern determination table 132 shown in FIG. 5C is stored.

  The normal variable display pattern determination table 130 shown in FIG. 5A is used to select a variable display pattern for deriving and displaying a fixed symbol for losing without reaching the special symbol game by the special symbol display 41. It is a table. The reach variable display pattern determination table 131 shown in FIG. 5B is a variable display pattern for deriving and displaying a fixed symbol of a lose without winning after reaching a special symbol game by the special symbol display 41. It is a table for selecting. 5C is a table for selecting a variable display pattern in which the display result of the variable symbol special display is a jackpot in the special symbol game by the special symbol display 41. It is.

  In each of the variable display pattern determination tables 130 to 132, for example, a plurality of variable display patterns and the value of the variable display pattern determination random number R3 are stored in association with each other. Based on the value of the variable display pattern determination random number R3 extracted from the variable display pattern determination random number counter 115, the special symbols are variably displayed in the special game from among the variable display pattern determination tables 130 to 132. The variable display pattern to be executed at the time of selection is selected and determined.

  The normal A and normal B variable display patterns selected using the normal variable display pattern determination table 130 are variable display patterns that do not involve reach. The variable display pattern of reach A (losing) selected using the variable display pattern determination table 131 at the time of reach is a variable display pattern that has a reach mode but the variable display result (determined symbol) does not cause a big hit. is there. On the other hand, the variable display pattern of reach A (big hit) selected using the big hit variable display pattern determination table 132 is a variable display pattern that has a reach mode and the variable display result causes a big hit.

  The variable display pattern of reach B is a variable display pattern having a reach form different from reach A. Here, different reach modes mean that different variable display modes (variable display speed and rotation direction of special symbols, etc.), characters, etc. appear after reaching reach. For example, in the reach A, the reach mode is realized by only one type of variable display mode, whereas in the reach B, the reach mode including a plurality of variable display modes having different variable display speeds and rotation directions of special symbols is provided. Realized.

  In addition, the variable display pattern of reach C is a variable display pattern having a reach form different from reach A and reach B. Unlike the reach A to reach C, the variable display pattern of reach D is a variable display pattern in which reach effect display by moving images is performed. In Reach A to Reach D, there are cases where there is a big hit or no big hit depending on the variable display pattern determination tables 130 to 132.

  Further, when the reach variable display pattern determination table 131 and the big hit variable display pattern determination table 132 are compared, the assignment of the random R3 value to each variable display pattern (reach type) is different. That is, the ratio of reach types to be selected differs depending on whether or not the display result in the special figure game is a big hit. Accordingly, the probability that the display result is a big hit differs depending on the type of reach that appears in the special figure game.

  In the example shown in FIG. 5, when the display result is lost, the ratio at which the reach A variable display pattern is used is higher than the ratio at which the reach D variable display pattern is used. On the other hand, when the display result is a big hit, the ratio at which the reach display variable display pattern is used is lower than the ratio at which the reach D variable display pattern is used. For this reason, when the reach by the variable display pattern of reach D appears in the special figure game, the probability that the display result will be a big hit is higher than when the reach by the variable display pattern of reach A appears. The probability that the display result determined for each type of reach is a big hit is referred to as the reach big hit reliability, or simply the reach reliability.

  The reach determination random number counter 114 shown in FIG. 3 stores the value of the reach determination random number R2 that is updated in synchronization with the value of the big hit determination random number R1 acquired by the CPU 103 from the random number generation circuit 17. The reach determination random number R2 takes a value in the range of “0” to “9”, and when the reach determination random number extracted from the reach determination random number counter 114 by the CPU 103 is “8”, A determination of “reach” is made.

  The variable display pattern determining random number counter 115 counts a variable display pattern determining random number R3 for determining a variable display pattern used for variable display of a special symbol. The variable display pattern determining random number R3 takes a value in the range of “0” to “250”.

  The probability variation determination random number counter 116 counts the probability variation determination random number R4 for determining whether or not to perform probability variation control (probability variation control) for shifting to the probability improvement state after the pachinko gaming machine 1 is put into the big hit gaming state. Is to do. This probability variation determination random number R4 takes a value in the range of “0” to “99”. If the value of the reach determination random number extracted from the reach determination random number counter 114 by the CPU 103 is an odd number, the probability variation big hit is determined. If it is an even number, it is usually determined that it is a big hit.

  The initial value determination random number counter 117 counts the initial value determination random number R5 for determining the initial count value of the probability variation determination random number R4 counted by the probability variation determination random number 116. The initial value determining random number R5 takes a value in the range of “0” to “99”, as is the case with the probability variation determining random number R4.

  In this embodiment, in order to prevent synchronization between the update cycle of the value of the probability variation determination random number R4 and the update cycle of the value of the initial value determination random number R5, the probability variation determination is performed in one game control interrupt process. The value of the random number for use R4 is incremented by one, whereas the value of the initial value determination random number R5 is set to be incremented by three.

  The initial value buffer memory 118 stores the value of the initial value determination random number R5 extracted from the initial value determination random number counter 117 by the CPU 103 as the initial value of the probability variation determination random number R4.

  In the flag memory 119 shown in FIG. 3, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 119 is provided with a special symbol process flag, a normal symbol process flag, a big hit flag, a probability change confirmation flag, a probability change flag, an input state flag, an error flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (FIG. 17) described later. The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 42 in a predetermined order.

  The jackpot flag is set to an on state when the display result of the special symbol game by the special symbol display unit 41 is a jackpot, and is cleared to an off state when the jackpot game state is finished. The probability variation confirmation flag is set to an on state when the special symbol display 41 is started, and if it is determined that the variable display result in the special symbol game is a probability variation big hit, the big hit gaming state is set. Is cleared and goes off when is finished.

  The probable change flag is set to ON when the probable change confirmation flag is on when the big hit gaming state ends, and is cleared when the big hit gaming state based on the fact that the big hit is normal Turns off. The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The error flag is set to an on state based on the input of a reset signal from a reset IC (integrated circuits) 182 with watchdog (FIG. 9). The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The switch circuit 107 shown in FIG. 2 takes in the start winning signals SS1 to SS3 from the left, middle and right start opening switches 71 to 73 and the detection signals from the other winning opening switches 74, and controls the game control microcomputer. 100. The solenoid circuit 108 drives the solenoids 21 to 24 in accordance with instructions from the game control microcomputer 100. The solenoids 21 to 23 are connected to the movable wing pieces of the left, middle, and right ordinary variable winning ball devices 6L, 6C, and 6R through link mechanisms, respectively. The solenoid 24 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The effect control board 12 controls the display operation in the image display device 4, the sound output operation from the speakers 8L and 8R, the lighting operation and the extinguishing operation of the game effect lamp 9. For example, the effect control board 12 performs control for executing various effect displays by causing the image display device 4 to perform image switching display based on an effect control command transmitted from the main board 11. The effect control board 12 is connected to wiring for transmitting control signals to the audio output circuit 13 and the lamp driver circuit 14.

  FIG. 6 is a block diagram illustrating a hardware configuration example of the effect control board 12. The effect control board 12 includes a CPU 200, a ROM 201, a RAM 202, a VDP (Video Display Processor) 203, a CGROM (Character Generator ROM) 204, a VRAM (Video RAM) 205, an audio data output circuit 206, and lamp data. And an output circuit 207.

  When receiving the effect control command transmitted from the main board 11, the CPU 200 reads control data for effect control from the ROM 201 while using a predetermined area of the RAM 202 as a work area. Based on the read control data, the CPU 200 performs display control of the image display device 4 by sending a drawing command to the VDP 203, or causes the audio data output circuit 206 to output audio data. Then, sound output control is performed, and lamp lighting control is performed by causing the lamp data output circuit 207 to output lamp data to the lamp driver circuit 14.

  The VDP 203 has, for example, a display control function and a high-speed drawing function for performing image display by the image display device 4, and executes image processing according to a drawing command from the CPU 200. Further, it has a two-dimensional address space independent of the CPU 200, and the VRAM 205 is mapped there. For example, the VDP 203 develops image data read from the CGROM 204 in a predetermined area of the VRAM 205. Then, a video signal including R (red), G (green), and B (blue) signals and a synchronization signal is output to the image display device 4. As an example, the R, G, and B signals are each represented by 8 bits, and the image display apparatus 4 combines 256 colors of R, G, and B according to instructions from the VDP 203, and synthesizes them to obtain approximately 16.7 million colors. Color display can be performed. Note that the number of bits of the R, G, and B signals may be other than 8 bits, and the number of bits of the R, G, and B signals may be different from each other.

  The CGROM 204 is for storing various image data used for displaying an image in the image display device 4. For example, the CGROM 204 stores character image data frequently used among images displayed on the image display device 4, specifically, a person, an animal, a character, a figure, a symbol, or the like in advance. . In this embodiment, the CGROM 204 stores image data composed of character strings for notifying that an abnormality has occurred in the random number generation circuit 17.

  A VRAM 205 is a frame buffer memory in which image data is expanded by the VDP 203.

  The audio data output circuit 206 receives the control command from the CPU 200 and outputs audio data to the audio output circuit 13. The audio output circuit 13 generates an audio signal by performing digital / analog conversion on the audio data received from the audio data output circuit 206, for example, and supplies the audio signal to the speakers 8L and 8R to output the audio.

  The lamp data output circuit 207 receives a control command from the CPU 200 and outputs lamp data to the lamp driver circuit 14. In the lamp driver circuit 14, for example, a lamp driving signal corresponding to the lamp data received from the lamp data output circuit 207 is generated and supplied to the game effect lamp 9 to switch on / off the lamp.

  The effect control board 12 includes a reception command buffer memory 210 and a flag memory 211 as shown in FIG.

  The reception command buffer memory 210 is provided with a plurality of reception command buffers for storing effect control commands received from the main board 11. FIG. 8 is a diagram illustrating a configuration example of the reception command buffer memory 210. In the example shown in FIG. 8, twelve received command buffers are provided, and a received command buffer for storing received commands is designated by a command reception number counter. The command reception number counter takes values from “0” to “11”. Each reception command buffer is composed of, for example, 1 byte, and by using a plurality of reception command buffers as ring buffers, it is possible to store 6 2-byte effect control commands.

  The flag memory 211 shown in FIG. 7 is for setting a plurality of types of flags that are set or cleared in accordance with the effect control command received from the main board 11. In the flag memory 211, for example, an effect control process flag and an error effect flag are provided. The effect control process flag indicates which process should be selected and executed in the effect control process (described later) (FIG. 24). The error effect flag is set to an on state when an error effect start command transmitted from the main board 11 is received.

  FIG. 9 is a block diagram showing the configuration of the random number generation circuit 17 and the monitoring circuit 18.

  As shown in FIG. 9, the random number generation circuit 17 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, first to third counters 1731 to 1733, and first to third latch signal output circuits. 1741 to 1743, first to third random value storage circuits 1751 to 1753, and first to third timer circuits 1761 to 1763. The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The reference clock signal output circuit 171 generates a reference clock signal S0 having a predetermined frequency (for example, 20 MHz). The reference clock signal output circuit 171 outputs the generated reference clock signal S0 to the clock signal generation circuit 172 and the first to third timer circuits 1761 to 1763.

  The clock signal generation circuit 172 is configured by a D-type lip flop circuit or the like. The clock terminal CK of the clock signal generation circuit 172 is connected to the output terminal of the reference clock signal output circuit 171, and the positive phase output terminal Q is connected to the counter 173. Further, the anti-phase output terminal (inverted output terminal) Q (bar) of the clock signal generation circuit 172 is connected to the input terminal D and the clock terminals CK of the first to third latch signal output circuits 1741 to 1743. Yes.

  The clock signal generation circuit 172 outputs a signal fed back from the reverse phase output terminal Q (bar) to the input terminal D at a timing when the reference clock signal S0 input from the reference clock signal output circuit 171 to the clock terminal CK rises. In synchronization, the signal is output from the positive phase output terminal Q, and the negative phase signal (inverted signal) of the signal output from the positive phase output terminal Q is output from the negative phase output terminal Q (bar). In this way, the clock signal generation circuit 172 generates two clock signals (counting clock signal S1 and latching clock signal S2) having the same cycle and different phases, and outputs the counting clock signal S1 in the positive phase. From the terminal Q, the latch clock signal S2 can be output from the negative phase output terminal Q (bar).

  Specifically, a count clock signal S1 having a frequency of 10 MHz is output from the positive phase output terminal Q, and a negative phase signal of the count clock signal S1, that is, a count is output from the negative phase output terminal Q (bar). Similarly to the clock signal S1, a latch clock signal S2 having a frequency of 10 MHz and having a phase different from that of the counting clock signal S1 by π (= 180 °) is output.

  The first to third counters 1731 to 1733 output the count value C output in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 to a predetermined initial value. Is updated cyclically to a predetermined final value.

  In this embodiment, the first to third counters 1731 to 1733 are both 16-bit binary counters, and each time the rising edge of the count clock signal S1 is input, the count values C1 to C3 is incremented by 1 from “0” to “65535”. When the count values C1 to C3 are counted up to “65535”, the count values are returned to “0” and counted up to “65535” again. That is, the count values C1 to C3 are “0” → “1” →... → “65535” each time the rising edge of the count clock signal S1 is input to the first to third counters 1731 to 1733, respectively. “0” →... Is updated cyclically.

  The first to third latch signal output circuits 1741 to 1743 are configured by D-type lip flop circuits or the like. The input terminals D of the first to third latch signal output circuits 1741 to 1743 are connected to the output terminals of the first to third timer circuits 1761 to 1763, respectively, and the clock terminal CK is the inverse of the clock signal generation circuit 172. It is connected to the phase output terminal Q (bar). The output terminals Q of the first to third latch signal output circuits 1741 to 1743 are connected to the first to third random value storage circuits 1751 to 1753, respectively.

  The first to third latch signal output circuits 1741 to 1743 synchronize the start winning signals SS1 to SS3 input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK, respectively. The latch signals SL1 to SL3 are generated and output from the output terminal Q.

  The first to third random number value storage circuits 1751 to 1753 are 16-bit registers, and the values of the jackpot determination random number R1 read in the first to third winning processes in steps S142, S144, and S146, which will be described later, respectively. Remember. The first to third random value storage circuits 1751 to 1753 are responsive to the rising edges of the latch signals SL1 to SL3 input from the output terminals Q of the first to third latch signal output circuits 1741 to 1743, respectively. The start winning signals SS1 to SS3 are input to the random number generation circuit 17 by latching and storing the count values C1 to C3 input from the first to third counters 1731 to 1733 as the value of the big hit determination random number R1. Each time, the value of the jackpot determination random number R1 stored is sequentially updated.

  FIG. 10 is a diagram for explaining the details of the connection between the output terminal of the i-th random value storage circuit 175 i (i = 1, 2, 3) and the I / O port 104 of the game control microcomputer 100. . In this embodiment, the bits of the output terminal of the i-th random value storage circuit 175i and the input port of the jackpot determination random number R1 included in the I / O port 104 are switched as shown in FIG. Connected. Thereby, the randomness of the random number input to the game control microcomputer 100 can be enhanced.

  The first to third timer circuits 1761 to 1763 shown in FIG. 9 measure the time during which the start winning signals SS1 to SS3 are input from the left, middle, and right start port switches 71 to 73, respectively. When a predetermined time (for example, 3 ms) is reached, the start winning signals SS1 to SS3 are output to the first to third latch signal output circuits 1741 to 1743.

  In this embodiment, the first to third timer circuits 1761 to 1763 are constituted by, for example, an up counter or a down counter, and are activated in response to the input of a high level signal. The first to third timer circuits 1761 to 1763 each have a predetermined timer value in response to the rising edge of the reference clock signal S0 input from the reference clock signal output circuit 171 while the input is at a high level. Count up or down. When the timer value counted up or down reaches a value corresponding to 3 ms, the first to third timer circuits 1761 to 1763 determine that the input signals are the start winning signals SS1 to SS3, respectively. Then, the start winning signals SS1 to SS3 are output to the first to third latch signal output circuits 1741 to 1743.

  FIG. 11 is a timing chart for explaining the operation of the random number generation circuit 17.

  As shown in FIG. 11A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  In response to the rising edge of the reference clock signal S0 input from the clock terminal CK, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 11B, the positive phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 11D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 11C, the i-th counter 173i counts the count value in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Ci is updated and output. On the other hand, the i-th latch signal output circuit 174i receives the start winning signal SSi shown in FIG. 11 (E) input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SLi shown in FIG. 11F is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2 input to.

  The i-th random value storage circuit 175i receives the count value Ci input from the i-th counter 173i to the input terminal D and from the output terminal Q of the i-th latch signal output circuit 174i to the clock terminal CK. In response to the rising edge of the latch signal SLi, the value of the jackpot determination random number R1 to be stored is updated as shown in FIG. 11G by latching and storing the value as the value of the jackpot determination random number R1.

  In this way, the random number generation circuit 17 can reliably make the update timing of the count value Ci different from the latch timing of the count value Ci.

  The monitoring circuit 18 shown in FIG. 9 includes a frequency dividing circuit 181 and a reset IC 182 with a watchdog. The monitoring circuit 18 is for monitoring the operation state of the random number generation circuit 17, more specifically the operation state of the reference clock signal output circuit 171 and the like.

  The frequency dividing circuit 181 takes in and divides the frequency of any one of the reference clock signal S0, the counting clock signal S1, and the latching clock signal S2 used when the random number generating circuit generates a random number. The divided clock signal is output to a reset IC with a watchdog. In this embodiment, the frequency dividing circuit 181 divides the count clock signal S1 output from the positive phase output terminal Q of the clock signal generation circuit 172, generates the frequency divided clock signal S3, and resets with a watchdog. Output to the IC 182.

  The reset IC 182 with a watchdog is a reset IC that incorporates a watchdog circuit (not shown). The reset IC 182 with a watchdog counts up or down the timer value of the watchdog circuit in response to the clock pulse. The reset IC 182 with watchdog initializes the timer value of the watchdog circuit in response to the rising edge of the divided clock signal S3 input from the frequency dividing circuit 181.

  Here, the time that can be measured by the watchdog circuit, that is, the time until the timer value of the watchdog circuit is counted up or down from the initial value to the final value is longer than the cycle of the divided clock signal S3. Is set to For this reason, when the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17 are operating normally, the rising edge of the divided clock signal S3 is periodically input to the watchdog circuit. Therefore, the timer value never reaches the final value.

  On the other hand, when an abnormality occurs in the reference clock signal output circuit 171 and the clock signal generation circuit 172, and the reference clock signal S0, the count clock signal S1, and the latch clock signal S2 are not generated, the watchdog circuit Since the rising edge of the divided clock signal S3 is not input, the timer value reaches the final value.

  In this way, when the watchdog circuit times out without the frequency-divided clock signal being input from the frequency-dividing circuit 181, the reset IC 182 with watchdog has an abnormality in the reference clock signal output circuit 171 and the clock signal generation circuit 172. As a thing, a predetermined reset signal SR is output to the main board 11. In the main board 11, based on the detection of the reset signal SR by the CPU 103, predetermined error processing (FIG. 15) is executed. By executing such error processing, the pachinko gaming machine 1 can prevent a situation in which the player is disadvantaged due to the occurrence of an abnormality in the random number generation circuit 17.

  The count value is periodically counted up, and a counter that receives the reference pulse (reference clock signal) of the random number circuit and clears the count value is compared with the count value in the counter and a predetermined threshold value. A monitoring circuit including a comparator that outputs a reset signal when this threshold is reached has already been disclosed (for example, JP-A-11-313966). When this is applied to the present embodiment as it is and the random number generation circuit 17 is monitored by taking the reference clock signal S0 into the monitoring circuit 18, an abnormality caused by the malfunction of the reference clock signal output circuit 171 can be detected. However, an abnormality caused by the malfunction of the clock signal generation circuit 172 cannot be detected. That is, the reference clock signal output circuit 171 operates normally and the reference clock signal S0 is generated, but the clock signal generation circuit 172 malfunctions, and the count clock signal S1 and the latch clock signal S2 are not generated. When the value of the big hit determination random number R1 is not updated, the occurrence of the abnormality cannot be detected. For this reason, it is preferable that the monitoring circuit 18 monitors the random number generation circuit 17 by acquiring the count clock signal S1 or the latch clock signal S2 as in this embodiment. By doing so, it is possible to detect not only the reference clock signal output circuit 171 but also the abnormality occurring in the clock signal generation circuit 172, and the monitoring function of the monitoring circuit 18 is further increased.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 12 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, interrupt processing is permitted (step S3), and then loop processing is started.

  CPU103 which performed the game control main process shown in FIG. 12 will perform the game control interruption process shown in the flowchart of FIG. 13, if the interruption request signal from CTC is received and an interruption request | requirement is received.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined switch process to detect detection signals input from the first to third starter switches 71 to 73 and the like via the switch circuit 107. The state is determined (step S11). Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and if necessary, warning can be generated according to the diagnosis result (step S12).

  Thereafter, a random number update process for updating a predetermined determination random number (step S13), an initial value determination random number update process for updating a predetermined initial value determination random number (step S14), and a display for updating a predetermined display random number The symbol random number update process (step S15) is sequentially executed.

  Next, the CPU 103 executes special symbol process processing (step S16). In the special symbol process, the corresponding process is selected and executed according to the special symbol process flag provided in the flag memory 119 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state. Following the special symbol process, the CPU 103 executes a normal symbol process (step S17). In the normal symbol process process, in order to control the normal symbol display 42 in a predetermined order, the corresponding process is selected and executed according to the normal symbol process flag provided in the flag memory 119.

  Further, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the effect control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S18). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in the predetermined command transmission table, and so on, for the sub-side control board such as the effect control board 12, etc. A control signal for controlling the progress of the game is transmitted. The effect control command sent from the main board 11 by this command control processing is received by the CPU 200 of the effect control board 12, and display control of the image display device 4 is performed according to the display control command.

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S19). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to a predetermined information terminal board.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movable blade piece in the normal variable winning ball device 6 and open / close the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S20). Thereafter, by executing predetermined prize ball processing, setting of the number of prize balls based on the start winning signals SS1 to SS3 input from the first to third start port switches 71 to 73 is performed, and the payout control board The payout control command can be output with respect to (step S21).

  Thereafter, the CPU 103 performs a special symbol display control process (step S22) for performing display control of the special symbol display unit 41 and a normal symbol display control process (step S23) for performing on / off control of the normal symbol display unit 42. Run sequentially.

  FIG. 14 is a flowchart showing the switch process executed in step S11. In this switch process, as shown in FIG. 14, the CPU 103 first determines whether or not the detection signal from the left start port switch 71 is in an ON state (step S101). If it is determined that the switch is on (step S101; Yes), the value of the left start port switch timer provided in the switch timer memory 111 is incremented by 1 (step S102).

  Subsequently, the CPU 103 checks the value of the left start port switch timer and determines whether or not the value has reached a predetermined switch-on determination value “2” (step S103). When it is determined that the value of the left start port switch timer has become “2” (step S103; Yes), the CPU 103 performs a predetermined number of times (for example, two times) of timer interruption processing (for example, 4 ms). It is determined that the start winning signal SS1 is continuously input from the left start port switch 71, the left start port switch on flag included in the input state flag is set (step S104), and the process proceeds to step S106. move on.

  On the other hand, when it is determined that the value of the left start port switch timer is not yet “2” (step S103; No), the process of step S104 is skipped and the process proceeds to step S106.

  If it is determined in step S101 that the detection signal from the left start port switch 71 is in the off state (step S101; No), the value of the left start port switch timer is cleared (step S105). The process proceeds to step S106.

  Next, the CPU 103 determines whether or not the detection signal from the middle start port switch 72 is in an on state (step S106). If it is determined that the switch is on (step S106; Yes), the value of the middle start port switch timer provided in the switch timer memory 111 is incremented by 1 (step S107).

  Subsequently, the CPU 103 checks the value of the middle start port switch timer and determines whether or not the value has become “2” (step S108). When it is determined that the value of the middle start port switch timer has become “2” (step S108; Yes), the CPU 103 performs a predetermined number of times (for example, twice) of timer interruption processing (for example, 4 ms). It is determined that the start winning signal SS2 is continuously input from the intermediate start port switch 72, the intermediate start port switch on flag included in the input state flag is set (step S109), and the process proceeds to step S111. move on.

  On the other hand, when it is determined that the value of the middle start port switch timer is not “2” (step S108; No), the process of step S109 is skipped and the process proceeds to step S111.

  If it is determined in step S106 that the detection signal from the middle start port switch 72 is in the OFF state (step S106; No), the value of the middle start port switch timer is cleared (step S110). The process proceeds to step S111.

  Subsequently, the CPU 103 determines whether or not the detection signal from the right start port switch 73 is in an on state (step S111). If it is determined that the switch is on (step S111; Yes), the value of the right start port switch timer provided in the switch timer memory 111 is incremented by 1 (step S112).

  Subsequently, the CPU 103 checks the value of the right start port switch timer and determines whether or not the value has become “2” (step S113). When it is determined that the value of the right start port switch timer has become “2” (step S113; Yes), the CPU 103 performs a predetermined number of times (for example, two times) of timer interruption processing (for example, 4 ms). It is determined that the start winning signal SS3 is continuously input from the right start port switch 73, the right start port switch on flag included in the input state flag is set (step S114), and the process proceeds to step S116. move on.

  On the other hand, when it is determined that the value of the right start port switch timer is not “2” (step S113; No), the process of step S114 is skipped and the process proceeds to step S116.

  If it is determined in step S111 that the detection signal from the right start port switch 73 is off (step S111; No), the value of the right start port switch timer is cleared (step S115). The process proceeds to step S116.

  Further, the CPU 103 also determines the state of the detection signal input from the other prize opening switch 74 (step S116).

  FIG. 15 is a flowchart showing the error process executed in step S12. In this error processing, as shown in FIG. 15, the CPU 103 first checks an input state flag or the like provided in the flag memory 119 to determine whether or not the reset signal SR is input from the monitoring circuit 18. It discriminate | determines (step S121). If it is determined that the reset signal SR has not been input (step S121; No), the error processing is terminated as it is.

  On the other hand, when it is determined that the reset signal SR is input (step S121; Yes), it is determined that an abnormality has occurred in the reference clock signal output circuit 171 and the clock signal generation circuit 172 of the random number generation circuit 17. The error flag provided in the flag memory 119 is set to the on state (step S122), and the error effect start command is set in the command transmission buffer for the effect control command. 12 is set to be sendable (step S123).

  FIG. 16 is a flowchart showing the random number update process executed in step S13. In this random number update process, as shown in FIG. 16, the CPU 103 first adds 1 to the count value in the probability variation determination random number counter 116 (step S131), and whether or not the count value after the addition has reached “100”. Is determined (step S132). When the count value after the addition reaches “100” (step S132; Yes), the count value in the random number counter for probability variation determination 116 is set to “0”, which is the initial count value, assuming that the count value has reached the upper limit value. (Step S133). On the other hand, when the count value after the addition does not reach “100” (step S132; No), the process of step S133 is skipped.

  Subsequently, the CPU 103 compares the count value in the probability variation determination random number counter 116 with the value of the initial value determination random number R5 stored as the initial value of the probability variation determination random number R4 in the initial value buffer memory 118. (Step S134), it is determined whether or not the count value in the probability variation determination random number counter 116 matches the stored value in the initial value buffer memory 118 (Step S135). When the count value in the probability variation determination random number counter 116 matches the value stored in the initial value buffer memory 118 (step S135; Yes), it is determined that the update of the probability variation determination random number R4 has been completed. In order to change the initial value, the initial value determining random number R5 is extracted from the initial value determining random number counter 117 (step S136).

  Then, the CPU 103 sets the value of the initial value determination random number R5 extracted in the process of step S136 in the probability variation determination random number counter 116 as the initial value of the probability variation determination random number R4 (step S137), and also sets the initial value buffer. The data is stored in the memory 118 (step S138). In this way, the initial value of the random number R4 for probability variation determination is changed every time the value is updated.

  On the other hand, if it is determined in step S135 that the count value in the probability variation determination random number counter 116 does not match the stored value in the initial value buffer memory 118 (step S135; No), the CPU 103 performs steps S136 to S138. Skip processing.

  Thereafter, the CPU 103 executes a predetermined normal symbol determination random number update process (step S139), thereby updating the normal symbol determination random number used for the lottery of the normal symbol display 42, and ends the random number update process. . In this normal symbol determination random number update process, the normal symbol determination random number may be updated by executing the same processes as in steps S131 to S138.

  17 and 18 are flowcharts showing the special symbol process executed in step S16. When the special symbol process is started, as shown in FIG. 17, the CPU 103 first determines whether or not the game ball has won the left normal variable winning ball device 6L by using an input state flag provided in the flag memory 119. A determination is made by checking the left start port switch-on flag (step S141). When the game ball wins the left normal variable winning ball apparatus 6L and the left start port switch 71 is in the on state (step S141; Yes), the first winning process is executed (step S142). On the other hand, when the game ball has not won the left normal variable winning ball apparatus 6L (step S141; No), the first winning process is skipped.

  Next, the CPU 103 determines whether or not the game ball has won the central normal variable winning ball device 6C by checking the start-up switch on flag in the input state flag provided in the flag memory 119. (Step S143). When the game ball wins the center normal variable winning ball device 6C and the middle start opening switch 72 is in the ON state (step S143; Yes), the second winning process is executed (step S144). On the other hand, when the game ball has not won the central normal variable winning ball apparatus 6C (step S143; No), the second winning process is skipped.

  Further, the CPU 103 determines whether or not the game ball has won the right normal variable winning ball device 6R by checking the right start port switch-on flag of the input state flag provided in the flag memory 119 ( Step S145). When the game ball wins the right normal variable winning ball apparatus 6R and the right start port switch 73 is turned on (step S145; Yes), the third winning process is executed (step S146). On the other hand, if the game ball has not won the right normal variable winning ball apparatus 6R (step S145; No), the third winning process is skipped.

  FIG. 19 is a flowchart showing the i-th winning process (i = 1, 2, 3) executed in steps S142, S144, and S146. In the i-th winning process, as shown in FIG. 19, first, the CPU 103 determines whether or not the starting winning memory number stored in the special figure holding memory 110 is the maximum value “4” (see FIG. 19). Step S201). Here, in the special figure holding memory 110, when the value of the big hit determination random number R1 corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”. .

  When the start winning memorization number is “4” (step S201; Yes), the start detection by the current winning is invalidated, and the i-th winning process is finished as it is. On the other hand, when the start winning memorized number is less than “4” (step S201; No), the value of the big hit determination random number R1 is read from the i-th random value storage circuit 175i (step S202), and the read big hit determination is performed. The value of the random number R1 is stored, for example, in a predetermined buffer area provided in the RAM 102 (step S203). Then, the CPU 103 adds “1” to the starting winning memory number (step S204), and sets the value of the jackpot determination random number R1 stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S204). S205).

  After executing the process of step S205, the value of the reach determination random number R2 corresponding to the value of the big hit determination random number R1 acquired in the process of step S202 is set in the reach determination random number counter 114 (step S206). For example, as shown in FIG. 20, the CPU 103 sets the value of the reach determination random number R2 to any one of “0” to “9” according to the value of the big hit determination random number R1 acquired in step S202. The reach determination random number counter 114 is set. As a result, the reach determination random number counter 114 updates the value of the reach determination random number R2 in synchronization with the value of the big hit determination random number R1 read from the i-th random value storage circuit 175i.

  Thereafter, the CPU 103 selects one of the seven processes of steps S150 to S156 shown in FIG. 18 based on the value of the special symbol process flag stored in the flag memory 119. Below, each process of step S150-S156 is demonstrated.

  The special symbol normal process of step S150 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, as shown in FIG. 21, first, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0” (step S211). Here, in the special figure holding memory 110, when various data such as the value of the jackpot determination random number R1 corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. The If the reserved storage number is “0” (step S211; Yes), the special symbol normal process is terminated by displaying a demonstration screen on the image display device 4 via the effect control board 12 or the like.

  On the other hand, if it is determined that the reserved storage number is not “0” (step S211; No), the value of the jackpot determination random number R1 stored in correspondence with the hold number “1” is read from the special figure holding memory 110 ( Step S212). At this time, “1” is subtracted from the reserved storage number, and the value of the random number R1 for jackpot determination stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is obtained. One entry is shifted up (step S213).

  After that, the CPU 103, based on the value of the jackpot determination random number R1 read out in the process of step S212, as a display result in the special symbol game executed by the special symbol display 41, is a probable big hit symbol (for example, “7”). A special symbol determination process is executed to determine whether to stop-display, or to normally display a big-hit symbol (for example, “3”) or to stop-display a lost symbol (for example, symbol numbers other than “3” and “7”) ( Step S214). After executing the jackpot determination process, the CPU 103 updates the value of the special symbol process flag to “1” which is a value corresponding to the variable display pattern setting process (step S215).

  FIG. 22 is a flowchart showing the special symbol determination process executed in step S214 shown in FIG. In this special symbol determination process, as shown in FIG. 22, the CPU 103 first checks the probability changing flag provided in the flag memory 119 to determine whether or not the probability improving state (probably changing) ( In step S301), if the probability change is not in progress (step S301; No), it is determined that the game is in the normal game state, and a table for determining whether or not the display result of the special figure game is a big hit is shown in FIG. The normal big hit determination table 120 as shown in FIG. On the other hand, if the probability change is in progress (step S301; Yes), the probability change big hit determination table 121 as shown in FIG. 4B is set (step S303).

  Subsequently, based on the value of the jackpot determination random number R1 read out in step S212, the CPU 103 uses the jackpot determination table 120 or 121 set in step S302 or S303 to win the display result of the special figure game. A jackpot determination process is performed to determine whether or not (step S304). If it is determined to be lost (step S305; No), the big hit flag provided in the flag memory 119 is cleared and turned off (step S306), and then the process proceeds to step S313.

  On the other hand, when it is determined to be a big hit (step S305; Yes), the big hit flag provided in the flag memory 119 is set to an on state (step S307). Subsequently, the CPU 103 extracts the value of the probability variation determination random number R4 from the probability variation determination random number counter 116 (step S308), and the probability variation big hit is determined depending on whether the extracted value of the probability variation determination random number R4 is an odd number or an even number. Probability change determination processing for determining whether or not to be a normal big hit is executed (step S309).

  When the value of the extracted random number for probability variation determination R4 is an odd number, it is determined that the probability variation is a big hit (step S310; Yes), and the probability variation confirmation flag provided in the flag memory 119 is set to an on state ( Step S311). On the other hand, if it is an even number, it is determined that it is usually a big hit (step S310; No), and the probability variation confirmation flag is cleared and turned off (step S312).

  Then, the CPU 103 determines a determined symbol for determining a determined symbol in the special symbol game executed on the special symbol display 41 based on the determination result of the jackpot determination processing in step S304 and the determination result of the probability variation determination processing in step S309. Processing is executed (step S313).

  In this fixed symbol determination process, the CPU 103 determines whether or not the big hit flag provided in the flag memory 119 is turned on, and if the big hit flag is turned on, the probability change fixed flag is further turned on. It is determined whether or not. As a result of these determinations, when both the big hit flag and the probability variation confirmation flag are on, the special symbol indicating “7” which is the probability variation big hit symbol is determined as the final symbol in the current special symbol game. When the big hit flag is on and the probability change confirmation flag is off, the special symbol indicating “3”, which is the normal big hit symbol, is determined as the final symbol in the current special symbol game. On the other hand, when the big hit flag is off, a special symbol having a symbol number different from “7”, which is a probable big hit symbol, and “3”, which is a normal big hit symbol, is determined as a confirmed symbol in the current special symbol game. . It should be noted that the determined symbol may be determined by referring to, for example, a predetermined determined symbol determination table regardless of the determination result of big hit or loss or the determination result of normal big hit or probable big hit. . In this case, on the side of the effect control board 12, the CPU 200 specifies whether it is a big hit or a loss, a normal big hit or a probable big hit, based on the variable display start command and the symbol designation command from the main board 11, and makes a probable big hit. For example, in a round game that is performed in a big hit game state, the image display device 4 executes a predetermined effect display or emits a predetermined sound from the speakers 8L and 8R, so that the player is surely changed. What is necessary is just to alert | report that it is a big hit.

  The variable display pattern setting process in step S151 shown in FIG. 18 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 23, the CPU 103 first determines whether or not the big hit flag provided in the flag memory 119 is on (step S221). When the big hit flag is off (step S221; No), the reach determination random number counter 114 extracts the value of the reach determination random number R2 (step S222), and the reach determination is based on the extracted reach determination random number R2. A reach determination process for determining whether or not to be performed is executed (step S223).

  When not reaching (step S224; No), the normal variable display pattern determination table 130 shown in FIG. 5A is set as a table for selecting the variable display pattern (step S225). When reaching (step S224; Yes), the reach variable display pattern determination table 131 shown in FIG. 5B is set as a table for selecting a variable display pattern (step S226).

  When it is determined in step S221 that the big hit flag is on (step S221; Yes), the table for selecting the variable display pattern is used for determining the big hit variable display pattern shown in FIG. 5C. The table 132 is set (step S227).

  The CPU 103 extracts the value of the variable display pattern determining random number R3 from the variable display pattern determining random number counter 115 (step S228), and based on the extracted value of the random R3, the variable set in the processing of steps S225 to S227. From the display pattern determination table, a variable display pattern to be used in the current special figure game is determined (step S229).

  Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the variable display control process, and the variable display pattern determination process is ended (step S230).

  The special symbol variable display process of step S152 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 controls the image display device 4 to start variable display for all the decorative symbols. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S313 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S151 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation commands can be sent to the effect control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “3” which is a value corresponding to the special symbol stop process.

  The special symbol stop process in step S153 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 makes settings for sending a special symbol confirmation command from the main board 11 to the effect control board 12. Specifically, the special symbol confirmation command is set to be able to be sent to the effect control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Note that such a special symbol confirmation command may not be sent to the effect control board 12. In this case, on the side of the effect control board 12, when the predetermined variable display time timer has timed out or when a predetermined period has elapsed since the time-out, the decorative design by the image display device 4 may be determined and displayed. . Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “4”, which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S154 is a process executed when the value of the special symbol process flag is “4”. In this processing, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “5” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S155 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches, for example, 16, the condition for ending the specific gaming state (big hit gaming state) is established. As a result, the value of the special symbol process flag is updated to “6” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S156 is a process executed when the value of the special symbol process flag is “6”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the effect control board 12. In addition, the CPU 103 clears the big hit flag provided in the flag memory 119 and sets it to the off state. Then, the value of the special symbol process flag is updated to “0”.

  Next, the operation in the effect control board 12 will be described. FIG. 24 is a flowchart showing an effect control main process executed by the effect control CPU 200 mounted on the effect control board 12. When the production control main process is started, as shown in FIG. 24, first, a predetermined initialization process is executed to clear the RAM 202, set various initial values, and determine the activation control activation interval. The second timer is initialized (step S31).

  Thereafter, the CPU 200 monitors a predetermined timer interrupt flag and executes a loop process until the timer interrupt flag is set (step S32; No). In this embodiment, a timer interrupt occurs every 33 milliseconds in the CPU 200, and when this timer interrupt occurs, a timer interrupt flag is set by executing a predetermined timer interrupt process.

  In the CPU 200, an interrupt for receiving the effect control command from the main board 11 is generated separately from the timer interrupt generated every 33 milliseconds. This interruption is an interruption that occurs when the effect control INT signal from the main board 11 is turned on. When an interruption occurs due to the turn-on of the effect control INT signal, the CPU 200 automatically sets the interrupt prohibited state. However, if a CPU that does not automatically enter the interrupt prohibited state is used, It is preferable to issue an insertion prohibition instruction (DI instruction).

  When the production control INT signal from the main board 11 is turned on, an interrupt is generated in the CPU 200, whereby execution of the command reception interrupt process shown in the flowchart of FIG. 25 is started. In this command reception interrupt process, the CPU 200 first saves the value of each register in the stack (step S41). Subsequently, an effect control command is read from a predetermined input port or the like that receives a control signal assigned to the input of the effect control command data and transmitted from the main board 11 (step S42). And it is discriminate | determined whether it is the 1st byte of the production control commands of 2 bytes structure (step S43). Here, the first byte (MODE) and the second byte (EXT) of the effect control command are configured to be immediately distinguishable on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. When the first bit of the received command is “1”, it is determined that the valid first byte (MODE data) of the effect control command having a 2-byte configuration has been received.

  When it is determined in the process of step S43 that the MODE data is the first byte (step S43; Yes), the received command is stored in the reception command buffer specified by the command reception number counter in the reception command buffer memory 210. Store (step S44). After executing step S44, the process proceeds to step S50. On the other hand, if it is not the first byte of the effect control command (step S43; No), it is determined whether or not the first byte of MODE data has already been received (step S45). Whether or not the first byte of MODE data has been received can be determined by checking the command data stored in the received command buffer.

  If the first byte has already been received (step S45; Yes), it is determined whether or not the first bit of the one byte received this time is “0”, and if the first bit is “0”. For example, assuming that a valid second byte has been received, the received command is stored in the next reception command buffer specified by the command reception number counter (step S46). If it is determined in step S45 that the first byte of the effect control command has not been received (step S45; No), the first bit of the data received as the second byte is not “0”. In step S50, the process proceeds to step S50.

  When the command data of the second byte is stored in the process of step S46, the value of the command reception number counter is incremented by 2 (step S47), and it is determined whether or not the value is “12” or more (step S48). . If it is “12” or more (step S48; Yes), the command reception number counter is cleared and its value is returned to “0” (step S49). On the other hand, when it is less than “12” (step S48; No), the process of step S49 is skipped. Thereafter, the register saved in the process of step S41 is restored (step S50), and interrupt permission is set (step S51).

  By such command reception interrupt processing, the effect control command transmitted from the main board 11 is stored in the reception command buffer provided in the reception command buffer memory 210, while the timer interrupt is performed in the processing of step S32 shown in FIG. Occurrence is confirmed. When occurrence of a timer interrupt is confirmed (step S32; Yes), a predetermined command analysis process is executed after the timer interrupt flag provided in the flag memory 211 is cleared and turned off (step S33).

  When the command analysis process is completed, the CPU 200 executes a predetermined error process to indicate that an error has occurred by the image display device 4, the speakers 8L and 8R, the game effect lamp 9, and the like as necessary. (Step S34). Subsequently, after executing a counter update process (step S35) for updating a random value counted by a predetermined random counter, the CPU 200 executes an effect control process process (step S36).

  FIG. 26 is a flowchart showing the command analysis processing in step S33 shown in FIG. In this command analysis process, as shown in FIG. 26, the CPU 200 first checks whether or not the effect control command received from the main board 11 is stored in the command reception table provided in the reception command buffer memory 210. (Step S401).

  When the reception command is stored in the command reception table (step S401; Yes), the CPU 200 reads the reception command from the command reception table (step S402), and whether or not the read reception command is an error effect start command. Is determined (step S403). When read, the read pointer value is incremented by one.

  When it is determined that the received command read in the process of step S402 is an error effect designation command (step S403; Yes), the CPU 200 sets an error effect start flag provided in the flag memory 211 to an ON state (step S403). In step S404, the process returns to step S401.

  On the other hand, if the received command read in the process of step S402 is another effect control command (step S403; No), a command reception flag corresponding to the received command is set (step S405), and the process of step S401 is performed. Return to

  On the other hand, if it is determined in step S401 that the received command is not stored in the command reception table (step S401; No), the command analysis process is terminated as it is.

  FIG. 27 is a flowchart showing details of the error processing executed in step S34 of FIG. In this error processing, as shown in FIG. 27, the CPU 200 first determines whether or not the error presentation start flag provided in the flag memory 211 is on (step S411). If it is determined in step S411 that the error effect start flag is off (step S411; No), the error process is terminated.

  On the other hand, if it is determined in step S411 that the error effect start flag is on (step S411; Yes), the error effect start flag is cleared (step S412), and then a random number is generated from the CGROM 204. In the image display device 4, the image data composed of a character string for notifying that an abnormality has occurred in the circuit 17 is read out and a drawing command according to the read image data is sent to the VRAM 205. Settings are made to start an effect display that notifies the random number generation circuit 17 that an abnormality has occurred (step S413).

  In this embodiment, a message indicating that an abnormality has occurred is displayed in an area above the area where the decorative symbol is variably displayed. For this reason, as shown in FIG. 28, even when decorative display variable display is being executed, a message indicating that an abnormality has occurred can be interrupted and displayed in the decorative display variable display. Note that a message indicating that an abnormality has occurred may be displayed on the image display device 4 after the variable display of the decorative symbols is completed or after the big hit gaming state is completed.

  Further, when notifying that an abnormality has occurred, not only a display operation by the image display device 4 but also an operation of turning on a predetermined error lamp or generating a warning sound from the speakers 8L and 8R may be added. In addition, it may be in a mode of notifying that a payout error has occurred only by turning on an error lamp or generating a warning sound.

  As described above, according to this embodiment, the clock signal generation circuit 172 inputs the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The i-th counter 173i outputs the count value Ci at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Update sequentially.

  When a game ball wins one of the left, middle and right ordinary variable winning ball devices 6L, 6C and 6R which is the starting winning opening, the corresponding starting of the right, middle and left starting opening switches 71 to 73 is started. The mouth switch 7i sends a start prize signal SSi to the main board 11 and the random number generation circuit 17, and the start prize signal SSi sent to the random number generation circuit 17 passes through the i-th timer circuit 176i. The signal is input to the input terminal D of the i-th latch signal output circuit 174i. The i-th latch signal output circuit 174i receives the start winning signal SSi input to the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At a timing T11, T13, T15,... When the signal S2 rises from the low level to the high level, the signal S2 is output from the output terminal Q as the latch signal SLi.

  The i-th random value storage circuit 175i receives the count value Ci input from the i-th counter 173i to the input terminal D and from the output terminal Q of the i-th latch signal output circuit 174i to the clock terminal CK. In response to the rising edge of the latch signal SLi, it is latched and stored as the value of the jackpot determination random number R1.

  In this way, the random number generation circuit 17 ensures that the update timing of the count value Ci by the i-th counter 173i is different from the output timing (latch timing) of the latch signal SLi by the i-th latch signal output circuit 174i. Can be made. Since the random number generation circuit 17 updates the count value Ci and outputs the latch signal SLi without inverting the reference clock signal S0, the random number generation circuit 17 can update even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the value of the jackpot determination random number R1.

  The random number generation circuit 17 includes first to third counters 1731 to 1733 corresponding to the start port switches 71 to 73 of the left, middle, and right ordinary variable winning ball devices 6L, 6C, and 6R. 1st to 3rd latch signal output circuits 1741 to 1743, 1st to 3rd random number value storage circuits 1751 to 1753, and 1st to 3rd timer circuits 1761 to 1763 are provided. . For this reason, even when a game ball wins at least two normal variable winning ball devices of the left, middle, and right normal variable winning ball devices 6L, 6C, 6R, the first to third disturbances of the count values C1 to C3. The storage in the numerical value storage circuits 1751 to 1753 is performed independently. The values of the jackpot determination random numbers R1 (count values C1 to C3) taken into the plurality of first to third random number value storage circuits 1751 to 1753 at the same time are obtained as a single game control interruption process. Are read out in the corresponding winning process and are stored in the special figure holding memory 110.

  As described above, the CPU 103 can extract the value of the big hit determination random number R1 based on the fact that the game ball has won the plurality of ordinary variable winning ball devices at the same time without shifting the timing. It can prevent giving an unfair feeling to Also in this case, since the reference clock signal output circuit 171 and the clock signal generation circuit 172 can be used in common, an increase in manufacturing cost can be suppressed.

  The random number generation circuit 17 does not directly input the start winning signal SSi output from the start port switch 7i to the i-th latch signal output circuit 174i, but instead inputs it to the i-th timer circuit 176i to start The input time of the winning signal SSi is measured, and when the measured time reaches a preset time (3 ms), the start winning signal SSi is input to the i-th latch signal output circuit 174i. Therefore, the pachinko gaming machine 1 can prevent the i-th latch signal output circuit 174i from erroneously outputting the latch signal SLi to the i-th random value storage circuit 175i due to the influence of noise or the like. Since the i-th timer circuit 176i is set to “3 ms” which is shorter than “4 ms” between the executions of the two timer interrupt processes, the CPU 103 reads out from the i-th random value storage circuit 175 i. It is possible to prevent the value of the jackpot determination random number R1 from being the same as the value of the jackpot determination random number R1 read at the time of the previous winning.

  As described above, the jackpot determination random number R1 updated by the random number generation circuit 17 is used for the jackpot determination, while the CPU 103 stores software stored in the ROM 101 for the probability change determination. Thus, the value of the random number for probability variation determination R4 that is updated by executing the random number update process in step S13 is used.

  In this way, by using random numbers with different update methods for the jackpot determination and the probability variation determination, it is possible to prevent periodicity from occurring in the results of these two determinations. Can be increased. Further, in the random number update process in step S13, the initial value of this random number update is changed each time the value of the probability variation determination random number R4 is updated, so that the randomness between the determination results is further improved. Can do.

  The random number generation circuit 17 latches the count value Ci updated by the counter 173i when the start prize signal SSi is detected by the i-th timer circuit 176i from the start port switch 7i, and the i-th It is stored in the random value storage circuit 175i as the value of the jackpot determination random number R1. On the other hand, when the CPU 103 of the main board 11 determines that the input from the start port switch 7i is in the ON state in the switch process of step S11, a predetermined number of times (for example, twice) is made continuously. The value of the probability variation determination random number R2 is extracted from the probability variation determination random number counter 116.

  Thus, the CPU 103 can make the timing for reading the value of the big hit determination random number R1 from the random number generation circuit 17 different from the timing for extracting the value of the probability variation determination random number R2 from the probability variation determination random number counter 116. , Fraud by malicious players can be prevented.

  Further, every time the CPU 103 acquires the value of the jackpot determination random number R1 from the i-th random value storage circuit 175i in the process of step S203, the reach determination random number R2 corresponding to the acquired value of the jackpot determination random number R1. Is set in the reach determination random number counter 114 in step S206. Accordingly, the value of the reach determination random number R2 stored in the reach determination random number counter 114 is updated in synchronization with the value of the big hit determination random number R1 read from the i-th random value storage circuit 175i. . The value of the reach determination random number R2 set in the reach determination random number counter 114 is read by the CPU 103 in step S222 and used in the reach determination process in step S223. Therefore, when a failure occurs in the random number generation circuit 17 and the value of the jackpot determination random number R1 is not updated, the value of the reach determination random number R2 is not updated, and the image display device 5 performs a plurality of times. In the variable display of the decorative design, the variable display mode is continuously reached, or the display result is normally lost without reaching reach for a long period of time.

  With such a variable display mode of decorative symbols, the player can estimate whether or not a failure has occurred in the random number generation circuit 17 and can prevent a significant disadvantage from being caused when a failure occurs. Generally, the probability that the variable display mode of decorative symbols will reach is set to be higher than the probability that the variable display result will be a big hit. The occurrence of a failure can be estimated in a shorter period than when it is estimated that a failure has occurred in the circuit 17. In addition, since a special configuration for monitoring the value of the jackpot determination random number R1 read from the i-th random value storage circuit 175i is not necessary, an increase in manufacturing cost can be suppressed.

  Further, the frequency dividing circuit 181 of the monitoring circuit 18 takes in and divides the count clock signal S1 output from the clock signal generating circuit 172, and a frequency-divided clock signal S3 obtained by frequency division is provided with a watchdog. Output to the reset IC 182. In response to the clock pulse, the reset IC 182 with watchdog counts up or down the timer value of the built-in watchdog circuit, and responds to the rising edge of the divided clock signal S3 input from the frequency dividing circuit 181. Then, this timer value is initialized.

  When the timer value of the watchdog circuit reaches the final value without receiving the frequency-divided clock signal S3, the reset IC with watchdog 182 sends the reference clock signal output circuit 171 and the clock signal generation circuit 172 to the random number generation circuit 17. A predetermined reset signal SR is output to the main board 11 as an abnormality has occurred. On the main board 11 side, on the basis of the detection of the reset signal SR by the CPU 103, an error flag provided in the flag memory 119 is set to ON and an error effect is provided to the effect control board 12. Send a start command.

  On the side of the effect control board 12, the CPU 200 starts an effect display for notifying the random number generation circuit 17 that an abnormality has occurred in the image display device 4 based on the reception of this error effect start command.

  In this way, by notifying the player that the random number generation circuit 17 has an abnormality and recognizing it, the player is prevented from continuing the game while the random number generation circuit 17 remains abnormal. can do.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above-described embodiment, the left / middle / right start opening switches 71 to 73 are used for winning the game balls to the left / middle / right ordinary variable winning ball apparatuses 6L, 6C, 6R corresponding to the start winning openings. Are output to the main board 11 and the random number generation circuit 17, and the random number generation circuit 17 outputs the first to third timers. In the circuits 1761 to 1763, the time when the start winning signals SS1 to SS3 are input from the corresponding left, middle and right start port switches 71 to 73 are measured, and the measured time is set to a predetermined time (for example, 3 ms). At that time, the start winning signals SS1 to SS3 were output to the first to third latch signal output circuits 174.

  However, the present invention is not limited to this, and the left, middle, and right start port switches 71 to 73 output start winning signals SS1 to SS3 only to the main board 11 and are mounted on the main board 11, respectively. The CPU 103 continues to receive the start winning signals SS1 to SS3 from the left / middle / right start port switches 71 to 73 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). On the basis of the input, the latch start winning signals SE1 to SE3 may be sent to the corresponding first to third latch signal output circuits 1741 to 1743, respectively.

  A gaming machine according to such a modification will be described below with reference to the drawings. FIG. 29 is a block diagram showing a configuration of a random number generation circuit 27 according to this modification. In addition, in the random number generation circuit 27, about the same structure as the random number generation circuit 17 which concerns on the said embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted as needed.

  As shown in FIG. 29, the random number generation circuit 27 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, first to third counters 1731 to 1733, and first to third latch signal output circuits. 1741 to 1743, and first to third random value storage circuits 1751 to 1753.

  The input terminals D of the first to third latch signal output circuits 1741 to 1743 are connected to the I / O port 104, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. ing. The output terminals Q of the first to third latch signal output circuits 1741 to 1743 are connected to the first to third random value storage circuits 1751 to 1753, respectively. The first to third latch signal output circuits 1741 to 1743 respectively synchronize the latch start winning signals SE1 to SE3 input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK. Thus, the latch signals SL1 to SL3 are generated and output from the output terminal Q.

  FIG. 30 is a timing chart for explaining the operation of the random number generation circuit 27.

  As shown in FIG. 30A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  In response to the rising edge of the reference clock signal S0 input from the clock terminal CK, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 30B, the positive phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 30D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 30C, the i-th counter 173i responds to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172, and the count value C Is updated and output. On the other hand, the i-th latch signal output circuit 174i receives the latch start winning signal SEi shown in FIG. 30 (E) input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. A latch signal SLi shown in FIG. 30F is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2 input to the terminal CK.

  The i-th random value storage circuit 175i receives the count value Ci input from the i-th counter 173i to the input terminal D and the latch signal SLi input from the output terminal Q of the latch signal output circuit 174i to the clock terminal CK. In response to the rising edge, the big hit determination random number R1 is latched and stored as shown in FIG. 30G, thereby updating the stored big hit determination random number R1.

  Even in this case, the random number generation circuit 27 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In this modification, the flag memory 119 shown in FIG. 3 is provided with first to third random number read flags in addition to the above-described flags. The first to third random number read flags are set to the ON state when the latch start winning signals SE1 to SE3 are sent to the first to third latch signal output circuits 1741 to 1743, respectively. When the value of the jackpot determination random number R1 is read from the third random number value storage circuits 1751 to 1753, it is cleared and turned off.

  FIG. 31 is a flowchart showing the special symbol process executed in step S16 in this modification. When the special symbol process is started, the CPU 103 first determines whether or not the first random number read flag provided in the flag memory 119 is turned on (step S1141).

  When the first random number read flag is off (step S1141; No), whether or not the game ball has won the left normal variable winning ball device 6L is determined based on the left of the input state flag provided in the flag memory 119. A determination is made by checking the start port switch-on flag (step S1142). When the game ball wins the left normal variable winning ball apparatus 6L and the left start port switch 71 is in the on state (step S1142; Yes), the first winning process is executed (step S1143). On the other hand, when the game ball has not won the left normal variable winning ball apparatus 6L (step S1142; No), the first winning process is skipped.

  On the other hand, when it is determined in the process of step S1141 that the random number read flag is on (step S1141; Yes), the first random value read process is executed (step S1144).

  Next, the CPU 103 determines whether or not the second random number read flag provided in the flag memory 119 is on (step S1145).

  When the second random number read flag is off (step S1145; No), whether or not the game ball has won the central variable winning ball device 6C is determined from the input status flags provided in the flag memory 119. A determination is made by checking the start port switch-on flag (step S1146). When the game ball wins the central variable ball player 6C at the center and the middle start port switch 72 is in the on state (step S1146; Yes), the second winning process is executed (step S1147). On the other hand, if the game ball has not won the central normal variable winning ball apparatus 6C (step S1146; No), the second winning process is skipped.

  On the other hand, when it is determined in the process of step S1145 that the second random number read flag is on (step S1145; Yes), the second random value read process is executed (step S1148).

  Subsequently, the CPU 103 determines whether or not the third random number read flag provided in the flag memory 119 is turned on (step S1149).

  When the third random number read flag is off (step S1149; No), whether or not the game ball has won the right normal variable winning ball device 6R is determined to the right of the input state flag provided in the flag memory 119. A determination is made by checking the start-port switch-on flag (step S1150). When the game ball wins the right normal variable winning ball apparatus 6R and the right start opening switch 73 is turned on (step S1150; Yes), the third winning process is executed (step S1151). On the other hand, when the game ball has not won the right normal variable winning ball apparatus 6R (step S1150; No), the third winning process is skipped.

  On the other hand, when it is determined in the process of step S1149 that the third random number read flag is on (step S1149; Yes), the third random value read process is executed (step S1152).

  FIG. 32 is a flowchart showing the i-th winning process (i = 1, 2, 3) executed in steps S1143, S1147, and S1151. In this i-th winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S1201). Here, in the special figure holding memory 110, when the value of the big hit determination random number R1 corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”. .

  When the start winning memory number is “4” (step S1201; Yes), the start detection by the current winning is invalidated, and the i-th winning process is finished as it is. On the other hand, when the start winning memory number is less than “4” (step S1201; No), the latch start winning signal SEi is sent to the i-th latch signal output circuit 174i (step S1202), and the i-th random number value is read. The flag is set to an on state (step S1203).

  FIG. 33 is a flowchart showing the i-th random number value reading process executed in steps S1144, S1148, and S1152. In this i-th random number value reading process, the CPU 103 first reads the value of the jackpot determination random number R1 from the i-th random number value storage circuit 175i (step S1211), and uses the read value of the jackpot determination random number R1 as For example, after being stored in a predetermined buffer area provided in the RAM 102 (step S1212), the number of start winning memories is incremented by “1” (step S1213), and the value of the big hit determination random number R1 stored in the predetermined buffer area is specified. It is set at the head of the empty entry in the figure holding memory 110 (step S1214).

  After executing the process of step S1214, the value of the reach determination random number R2 corresponding to the value of the big hit determination random number R1 acquired in the process of step S1211 is set in the reach determination random number counter 114 (step S1215). For example, as shown in FIG. 20, the CPU 103 sets the value of the reach determination random number R2 to any one of “0” to “9” in accordance with the value of the jackpot determination random number R1 acquired in step S1211. The reach determination random number counter 114 is set. As a result, the reach determination random number counter 114 updates the value of the reach determination random number R2 in synchronization with the value of the big hit determination random number R1 read from the i-th random value storage circuit 175i.

  Thereafter, the CPU 103 selects one of the seven processes of steps S150 to S156 shown in FIG. 18 based on the value of the special symbol process flag stored in the flag memory 119.

  As described above, according to this modification, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The i-th counter 173i sets the count value C at the timing T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Update sequentially.

  When a game ball wins one of the left, middle and right ordinary variable winning ball devices 6L, 6C and 6R which is the starting winning opening, the corresponding starting of the right, middle and left starting opening switches 71 to 73 is started. The mouth switch 7 i sends a start winning signal SSi only to the main board 11. The CPU 103 of the main board 11 is based on the fact that the start winning signal SSi is continuously input from the start port switch 7i while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Thus, it is determined that the game ball has won the corresponding ordinary variable winning ball apparatus, and a latch start winning signal SEi is sent to the random number generation circuit 27.

  The latch start winning signal SEi sent to the random number generation circuit 27 is inputted to the input terminal D of the i-th latch signal output circuit 174i. The i-th latch signal output circuit 174i latches the latch start winning signal SEi input to the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At a timing T11, T13, T15,... At which the clock signal S2 rises from the low level to the high level, it is output from the output terminal Q as the latch signal SLi.

  The i-th random value storage circuit 175i receives the count value Ci input from the i-th counter 173i to the input terminal D and from the output terminal Q of the i-th latch signal output circuit 174i to the clock terminal CK. In response to the rising edge of the latch signal SLi, it is latched and stored as the value of the big hit determination random number R1.

  Thereafter, in the first timer interruption process, the CPU 103 reads the value of the jackpot determination random number R1 from the i-th random value storage circuit 175i, and the read value of the jackpot determination random number R1 is the predetermined determination value “ It is determined whether or not the display result of the special figure game by the image display device 4 is set to the big hit gaming state by determining whether or not it matches with “2001 to 2184” or the like.

  In this way, the random number generation circuit 27 ensures that the update timing of the count value Ci by the i-th counter 173i is different from the output timing (latch timing) of the latch signal SLi by the i-th latch signal output circuit 174i. Can be made. Further, since the random number generation circuit 27 performs the updating of the count value Ci and the output of the latch signal SLi without inverting the reference clock signal S0, the update is performed even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the value of the jackpot determination random number R1.

  Further, when the CPU 103 determines that the game ball has won any of the left, middle and right ordinary variable winning ball devices 6L, 6C, 6R, the first to third latch signal outputs of the random number generation circuit 27 are output. In order to output the latch start winning signal SEi to the corresponding i-th latch signal output circuit 174i in the circuit 174i, the pachinko gaming machine 1 uses the first to third start port switches 71 to 73 to generate a random number generation circuit 27. There is no need to provide a path for supplying the start winning signals SS1 to SS3, and the hardware configuration can be simplified.

  Furthermore, based on the fact that the start winning signals SS1 to SS3 are continuously input while the timer interruption process is executed twice, the CPU 103 inputs the game ball to the corresponding ordinary variable winning ball device 6. Accordingly, the pachinko gaming machine 1 can prevent the latch start winning signals SE1 to SE3 from being erroneously output to the random number generation circuit 27 due to the influence of noise or the like.

  In addition, when the CPU 103 determines that a game ball has won any of the left, middle, and right ordinary variable winning ball devices 6L, 6C, 6R, in the first timer interruption process, Since the value of the big hit determination random number R1 is read out from the i-th random number value storage circuit 175i, the value of the read big hit determination random number R1 is prevented from being the same as the value of the big hit determination random number R1 read out last time. be able to.

  In the above embodiment, the positive phase output terminal Q of the clock signal generation circuit 172 is connected to the input terminals of the first to third counters 1731 to 1733, and the negative phase output terminal Q (bar) is the first one. The third latch signal output circuits 1741 to 1743 are connected to the input terminal D. However, the present invention is not limited to this, and the positive phase output terminal Q of the clock signal generation circuit 172 is connected to the input terminal Q of the first to third latch signal output circuits 1741 to 1743, and the negative phase output terminal Q (bar ) May be connected to the input terminals of the first to third counters 1731 to 1733, respectively.

  Furthermore, in the said embodiment, although the 1st-3rd counter 1731-1733 was an up counter, this invention is not limited to this, A down counter may be sufficient. Furthermore, the big hit determination numerical data updating means is not limited to the binary counter, and may be a pseudo random number generation circuit. Also, the connection between the output terminal of the bit data Ci0 to Ci15 of the count value Ci of the i-th counter 173i and the input terminal of the bit data Ci0 to Ci15 of the count value Ci of the i-th random value storage circuit 175i is changed. In this case, the randomness of the count value Ci input to the i-th random value storage circuit 175i can be improved.

  In the above embodiment, the first to third counters 1731 to 1733 are described as counting up the count values C1 to C3 by “1” every time the rising edge of the count clock signal S1 is input. did. However, the present invention is not limited to this. In the first to third counters 1731 to 1733, the value counted up each time the rising edge of the counting clock signal S1 is input is arbitrary, It may be different. For example, the first counter 1731 counts up by “1”, and the second counter 1732 counts up by “3”. Further, the third counter 1733 may be incremented by “5”.

  As described above, if the value counted up every time the rising edge is input is made different between the first counter 1731, the second counter 1732, and the third counter 1733, even when winning at the same timing, Depending on which of the normal variable winning ball devices 6L, 6C, 6R is won, the value of the generated jackpot determination random number R1 is different, so that the randomness of the jackpot generation can be improved.

  Furthermore, when the same value is counted up each time the rising edge of the counting clock signal S1 is input, one counter is shared by the first to third starter switches 71 to 73. You may make it use.

  In the above embodiment, the i-th timer circuit 176i is activated in response to the input of the high level signal, and the reference clock signal output circuit 171 receives the signal while the input is at the high level. In response to the input of the reference clock signal S0, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, the input signal is a high level signal. This is determined and output to the i-th latch signal output circuit 174i. However, the present invention is not limited to this, and the i-th timer circuit 176i measures the time during which the start winning signal SSi is input from the start port switch 7i, and when the measured time reaches a predetermined time. The start winning signal SSi is optional as long as it is output to the i-th latch signal output circuit 174i.

  Further, in the above embodiment, the first to third timer circuits 1761 to 1763 measure the signal input time using the reference clock signal S0 sequentially input from the reference clock signal output circuit 171. The present invention is not limited to this, and a clock signal obtained by dividing the reference clock signal S0 or a clock signal output from a clock signal output circuit different from the reference clock signal output circuit 171 may be used. In the above embodiment, 3 ms is set as the predetermined time in the first to third timer circuits 1761 to 1763, but the present invention is not limited to this, and two timer interruptions are performed. Any time can be set as long as it is shorter than the processing execution time of 4 ms.

  In the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 receives a start winning signal SS1 while three timer interrupt processes are being executed. The winning process may be executed based on the continuous input of .about.SS3. In this case, the first to third timer circuits 1761 to 1763 may be set to a time shorter than 6 ms that is the execution time of the three timer interruption processes.

  Further, in the above-described embodiment, the pachinko gaming machine 1 has three normal variable winning ball devices on the left, center, and right, but the present invention is not limited to this, and the number of normal variable winning ball devices is Are arbitrary and may be two or only one. The number of start port switches, counters, latch signal output circuits, random value storage circuits, and timer circuits may be provided according to the number of normally variable winning ball devices.

  In addition, by arranging a single normally variable winning ball apparatus and a rolling plate having a plurality of starting winning holes therein, the winning balls to the ordinary variable winning ball apparatus are distributed to any of the plurality of starting winning holes. May be allowed to enter.

  Further, among the left, middle and right ordinary variable winning ball devices 6L, 6C and 6R of the above embodiment, only the central ordinary variable winning ball device 6C has an electric tulip, and the left and right ordinary variable winning ball devices. The ball wound devices 6L and 6R may not have electric tulips.

  Further, in the above embodiment, the number of the image display devices 4 provided in the pachinko gaming machine 1 is one, but the present invention is not limited to this. For example, the left, middle and right normal winning ball devices Three image display devices corresponding to 6L, 6C, and 6R may be provided. In this case, for example, in a special figure game in which a game ball is won in the left ordinary variable winning ball apparatus 6L, the decorative symbol is variably displayed on the left image display apparatus among the three image display apparatuses. In the special game where the game ball is won in the central ordinary variable winning ball device 6C, the decorative image is variably displayed on the central image display device, and the right normal variable winning ball device 6R is displayed. In the special figure game in which the game ball is won in a special condition, the decorative image may be variably displayed on the right image display winning ball apparatus.

  Further, the random numbers that the CPU 103 updates in accordance with the software such as the ROM 101 are not limited to the random number R4 for probability variation, the random number R2 for reach determination, and the random number R3 for variable display determination. It is good also as what updates according to. For example, a short time determination random number for determining whether or not to perform short time control so that the variable display time is shorter than the normal gaming state, and the number of rounds for determining the number of rounds that can be executed in the big hit gaming state The CPU 103 may update the decision random number, the probability variation falling lottery random number for performing the lottery to determine whether or not the probability improvement state falls into the normal gaming state, according to the software.

  In the above embodiment, the abnormal signal output means is the reset IC 182 with a watchdog. However, the present invention is not limited to this, and the random number generation circuit 17 or 27 is based on whether or not a clock signal is input. As long as the operation state is monitored, any multi-vibrator composed of capacitors, resistors, transistor elements, and the like may be used. In this case, each time the rising edge of the divided clock signal is input to the multivibrator, the capacitor is charged for a predetermined period, and the capacitor continues to be discharged without the divided clock signal being input, and the voltage is set to a predetermined value. When the value falls below the threshold value, the reset signal SR may be output to the main board 11 on the assumption that an abnormality has occurred in the operation state of the random number generation circuit 17 or 27.

  Furthermore, in the above-described embodiment, the gaming machine can perform the variable display start condition (for example, the previous variable display and the display on the image display device 4) after the variable display execution condition (for example, winning the normal variable winning ball device 6) is satisfied. A variable display device (for example, the image display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the end of the big hit gaming state is established, This is a pachinko gaming machine that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the result is a predetermined specific display result.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 34, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 34 uses a game control means (for example, a main board) or a random number generation circuit as a start winning signal output means of the present invention based on a start lever 1011 operated by a player. A start switch (not shown) for outputting to (for example, a random number generation circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 34 functions as rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  Further, the apparatus configuration shown in FIGS. 1 and 34, the block configuration shown in FIGS. 2, 3, 6, 6, 7, 9 and 29, the timing chart configuration shown in FIGS. 11 and 30, the FIG. The table configuration shown in FIG. 5, the memory configuration shown in FIG. 8, the flowchart configurations shown in FIGS. 12-19, 21-27, and 31-33, and the image display examples shown in FIG. Changes and modifications can be arbitrarily made without departing from the scope.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of a winning ball. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the structural example of the table for jackpot determination. It is a figure which shows the structural example of the table for variable display pattern determination. It is a block diagram which shows the hardware structural example in an effect control board. It is a block diagram which shows the structural example of an effect control board. It is a figure which shows the structural example of a reception command buffer memory. It is a block diagram which shows the structural example of a random number generation circuit. It is a figure for demonstrating the connection of the output terminal of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random number generation circuit. It is a flowchart which shows the content of the game control main process. It is a flowchart which shows the content of the game control interruption process. It is a flowchart which shows the detail of the switch process in FIG. 14 is a flowchart showing details of error processing in FIG. 13. It is a flowchart which shows the detail of the random number update process in FIG. It is a flowchart which shows the detail of the special symbol process process in FIG. It is a flowchart which shows the detail of the special symbol process process in FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a figure which shows an example which sets the random number for reach determination. It is a flowchart which shows the detail of the special symbol normal process in FIG. It is a flowchart which shows the detail of the special symbol determination process in FIG. It is a flowchart which shows the detail of the variable display pattern setting process in FIG. It is a flowchart which shows the content of production control main processing. It is a flowchart which shows the content of a command reception interruption process. It is a flowchart which shows the detail of the command analysis process in FIG. It is a flowchart which shows the detail of the error process in FIG. It is a figure which shows the example of a display in an image display apparatus. It is a block diagram which shows the modification of a random number generation circuit. 30 is a timing chart for explaining the operation of the random number generation circuit of FIG. 29. It is a flowchart which shows the modification of the special symbol process process of FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the random value reading process in FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Image display device 6L, 6C, 6R ... Normal variable winning ball device
7 ... Special variable winning ball device
8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Production control board
13 ... Audio output circuit
14 ... Lamp driver circuit 17, 27 ... Random number generation circuit 21-24 ... Solenoid
41 ... Special symbol indicator
42 ... Normal symbol display 71-73 ... Start port switch
74… Other prize opening switches
100 ... Game control microcomputer 101, 201 ... ROM
102, 202 ... RAM
103, 200 ... CPU
104 ... I / O port
107… switch circuit
108… Solenoid circuit
110… Special figure hold memory
111 ... Switch timer memory
112 ... Table memory for jackpot determination
113 ... Table memory for determining variable display pattern
114 ... Random number counter for reach determination
115 ... Random number counter for variable display pattern determination
116 ... Probability change random number counter
117 ... Initial value determination random number counter
118 ... Initial value buffer memory 119, 211 ... Flag memory
120 ... Normal jackpot judgment table
121… Table for jackpot determination at probability change
130 ... Normal variable display pattern determination table
131 ... Reachable variable display pattern determination table
132 ... Table for variable display pattern determination at the time of big hit
171... Reference clock signal output circuit
172 ... Clock signal generation circuits 1731 to 1733 ... Counters 1741 to 1743 ... Latch signal output circuits 1751 to 1753 ... Random value storage circuits 1761 to 1763 ... Timer circuits
181 ... Frequency divider
182 ... Reset IC with watchdog
203 ... VDP
204 ... CGROM
205 ... VRAM
206 ... Audio data output circuit
207 ... Ramp data output circuit
210 ... Receive command buffer memory
1000… Slot machine
1001 ... Liquid crystal display
1002. Variable display device
1011 ... Start lever

Claims (8)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays each type of identification information that can be identified is provided, and the display result of the identification information is specified. When the result is reached, the player is controlled to a specific gaming state advantageous to the player. Further, when a predetermined condition is satisfied, the probability of the specific display result after the specific gaming state ends is different from the specific gaming state. A gaming machine that controls a higher probability state than in a normal gaming state,
A game control microcomputer including a game control CPU for controlling the progress of the game;
A random number generator for generating random numbers;
A start signal output means for outputting a start signal to the game control microcomputer based on the execution condition of the variable display being satisfied;
With
The random number generation circuit includes:
A reference clock signal output means for outputting a reference clock signal having a predetermined period;
A clock signal generating means for generating a plurality of signals having the same period and different phases based on the reference clock signal;
With
The clock signal generation means includes
A clock terminal to which the reference clock signal is input from the reference clock signal output means;
An input terminal to which the first signal is input;
A first output terminal that outputs a signal in which a change state of the first signal is synchronized with a timing that changes at every predetermined period of the reference clock signal input from the clock terminal;
A second output terminal that outputs a signal having the same period and a different phase as the signal output from the first output terminal;
Including
The clock signal generation means includes
By connecting the second output terminal and the input terminal, the first clock signal output from the first output terminal and the first clock signal output from the second output terminal And a second clock signal having the same period and different phases,
The random number generation circuit includes:
The specific display used when determining whether or not the display result of the variable display is the specific display result at the first timing when the first clock signal generated by the clock signal generating means changes in a predetermined manner. Specific display result determination numerical data updating means for updating result determination numerical data;
Latch signal output means for outputting a latch signal at a second timing at which the second clock signal generated by the clock signal generation means changes in the predetermined manner;
Random value storage means for storing the specific display result determination numerical data updated by the specific display result determination numerical data update means as a random value in response to a latch signal input from the latch signal output means;
Including
The game control microcomputer is:
Based on the input of the start signal from the start signal output means, random number reading means for reading a random value from the random value storage means,
Based on the establishment of the variable display start condition, it is determined whether the random value read by the random value reading means matches a predetermined specific display result determination value. Specific display result determination means for determining whether or not the display result in the display is the specific display result;
High probability state condition determination numerical value for updating high probability state condition determination numerical data used when determining whether or not the predetermined condition for controlling to the high probability state is satisfied after the specific gaming state ends Data updating means;
High probability state condition determination numerical data storage means for storing high probability state condition determination numerical data updated by the high probability state condition determination numerical data update means;
High probability state condition determination numerical data extraction means for extracting high probability state condition determination numerical data updated by the high probability state condition determination numerical data update means from the high probability state condition determination numerical data storage means;
When the value indicated by the high probability state condition determination numerical data extracted by the high probability state condition determination numerical data extraction unit matches a predetermined high probability state condition determination value, it is determined that the predetermined condition is satisfied. High probability state condition determining means to
A high-probability state control unit that controls the high-probability state after the specific gaming state is ended when the high-probability state condition determination unit determines that the predetermined condition is satisfied;
Initial value changing numerical data for updating initial value changing numerical data used for determining an initial value for updating high probability state condition determining numerical data updated by the high probability state condition determining numerical data updating means Update means;
Initial value changing numerical data storage means for storing initial value changing numerical data updated by the initial value numerical data updating means;
1-round determination means for determining whether or not the value indicated by the numerical data for high-probability state condition determination has made one round by the update by the numerical data update means for high-probability state condition determination;
When it is determined by the one-round determination means that the value indicated by the high-probability state condition determination numerical data is one round, the initial value change numerical data updated by the initial value change numerical data update means is Initial value changing numerical data extracting means for extracting from the initial value changing numerical data storage means;
The initial value changing numerical data extracted by the initial value changing numerical data extracting means is used as the initial value data of the high probability state condition determining numerical data updated by the high probability state condition determining numerical data updating means. Initial value changing means to be set;
including,
A gaming machine characterized by that. The game control microcomputer is:
Timer interrupt processing execution means for executing timer interrupt processing in response to an interrupt request signal periodically input;
Start signal input determination means for determining whether or not a start signal is continuously input from the start signal output means while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes;
A latch start signal output means for outputting a latch start signal to the random number generation circuit when the start signal input determination means determines that the start signal is continuously input;
Including
The latch signal output means includes
The latch start signal input from the latch start signal output means is output to the random number storage means as the latch signal,
The random value reading means includes:
In the timer interrupt process after the latch start signal output means outputs the latch start signal, the random number value is read from the random value storage means.
The gaming machine according to claim 1. The start signal output means includes
Based on the fact that the variable display execution condition is satisfied, a start signal is also output to the random number generation circuit,
The random number generation circuit includes:
A timer means for measuring the time when the start signal is input from the start signal output means, and outputting the start signal to the latch signal output means when the measured time reaches a predetermined time;
The latch signal output means includes
Outputting a start signal input from the start signal output means to the random value storage means as the latch signal;
The gaming machine according to claim 1. The game control microcomputer is:
In response to an interrupt request signal periodically input, includes timer interrupt processing execution means for executing timer interrupt processing,
The random value reading means includes:
While the timer interrupt process is executed by the timer interrupt process execution unit a predetermined number of times, the start signal is continuously input from the start signal output unit. Read
The timer means includes
Setting means for setting, as the predetermined time, a time shorter than a time when a predetermined number of timer interrupt processes are executed by the timer interrupt process executing means;
When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.
The gaming machine according to claim 3. The latch signal output means includes
When the start signal output from the start signal output means is detected, the latch signal is output to the random value storage means,
The game control microcomputer is:
Timer interrupt processing execution means for executing timer interrupt processing in response to an interrupt request signal periodically input;
A switch-on process execution means for executing a switch-on process for determining whether or not an input from the start signal output means is in an ON state each time the timer interrupt process is executed;
Including
The high probability state condition determination numerical data extraction means includes:
In the switch-on process, when the determination that the input from the start signal output means is in the ON state is made continuously a predetermined number of times, the high data updated by the high probability state condition determination numerical data update means Extracting the numerical data for determining the probability state condition from the numerical data storage means for determining the high probability state condition,
The gaming machine according to any one of claims 1 to 4, characterized in that: A plurality of the start signal output means,
A plurality of the specific display result determination numerical data updating means, the latch signal output means, and the random number storage means are provided corresponding to the start signal output means,
The plurality of specific display result determination numerical data update means includes:
Using the first and second clock signals that the clock signal generating unit generates based on the reference clock signal in common, the numerical data for determining the specific display result is independently updated,
The plurality of latch signal output means includes:
Each outputs a detection signal from the corresponding start signal output means as the latch signal,
There are a plurality of random value storage means,
In response to the latch signal from the corresponding latch signal output means, respectively, the corresponding specific display result determination numerical data updated by the specific display result determination numerical data update means is stored as a random value.
The gaming machine according to any one of claims 1 to 5, characterized in that: The game control microcomputer is:
Numerical data acquisition means for acquiring numerical data updated in synchronization with the specific display result determination numerical data updated by the specific display result determination numerical data update means;
Effect determining means for determining whether or not to execute the predetermined effect by determining whether or not the value indicated by the numerical data acquired by the numerical data acquiring means matches a predetermined effect determination value;
including,
The gaming machine according to any one of claims 1 to 6, characterized in that: Frequency dividing means for taking in and dividing at least one of the reference clock signal, the first clock signal, and the second clock signal;
When the clock signal divided by the frequency dividing means has not been input for a predetermined period or longer, an abnormal signal is output to the game control microcomputer as a signal indicating that an abnormality has occurred in the operating state of the random number generating circuit. Abnormal signal output means for
A random number generation circuit monitoring means comprising:
The game control microcomputer is:
An abnormal signal determining means for determining whether an abnormal signal is output from the abnormal signal output means;
An abnormality process execution means for executing a predetermined abnormality process when the abnormality signal determination means determines that an abnormality signal has been output;
including,
The gaming machine according to any one of claims 1 to 7, characterized in that:

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