JP4286179B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more specifically, a first variable display means for variably displaying a plurality of types of identification information that can be identified based on the first start condition being satisfied, A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the establishment of a second start condition different from the first start condition, and the identification information by the first variable display means When the display result of the variable display is a combination of predetermined specific identification information, or when the display result of the variable display of the identification information by the second variable display means is the combination of the specific identification information The present invention also relates to a gaming machine that controls a specific gaming state that is advantageous to the player.

  In gaming machines such as pachinko machines, variable display is performed by updating or scrolling predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on the display result.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In this game, the case where the stop symbol form when the display is completely stopped is a predetermined specific display form is determined as “big hit”. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

  The selection and determination of the display pattern variable display mode is based on the detection of a game ball that passes through the start winning opening and the random number value (mainly including a big hit random number and other random numbers for determining a figure stop symbol). Based on the extracted random number value, it is determined by determining whether or not to make a jackpot gaming state, a variation mode, and the like. As an example of a random number circuit for enabling such processing, Patent Document 1 discloses a configuration in which a counter is updated by a clock signal and a count value is acquired based on a predetermined timing signal. .

Also, some pachinko gaming machines have a plurality of start winning openings and a variable display unit corresponding to each starting winning opening, and one clock count circuit and two pieces are provided so as to correspond to this type of gaming machine. Patent Document 2 discloses a circuit including a count value storage circuit and two latch signal output circuits.
JP 7124296 A JP 2003-190483 A

When the random number circuit disclosed in Patent Document 1 is simply used in a pachinko gaming machine having a configuration having a plurality of start winning openings and a variable display unit corresponding to each starting winning opening, Depending on the winning timing, there is a possibility that the count value of the counter being updated is acquired or the same count value (random number value) is acquired for a plurality of variable display units.
Further, in the configuration of the random number circuit disclosed in Patent Document 2, since the output value of the common clock count circuit is latched by the two count value storage circuits, the same value may be obtained depending on the timing of winning to a plurality of start winning ports. There is a risk that the jackpot will be synchronized or the display will be synchronized.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine including a random number circuit capable of asynchronously outputting a plurality of random numbers for variable display areas.
Another aspect of the present invention provides a gaming machine including a random number circuit capable of making a random number update timing and a latch (memory) timing different from each other in a plurality of random display circuits for variable display areas. Objective.

In order to achieve the above object, a gaming machine according to claim 1 of the present application,
Based on the fact that the first start condition is satisfied after the first start condition (for example, winning to the first ordinary variable winning ball apparatus 5A) is satisfied, a plurality of types of identification information that can be identified are variable. The first variable display means for displaying (for example, the first variable display device 4A) and the second starting condition (for example, the second ordinary variable winning ball device 5B) different from the first starting condition. Second variable display means (for example, the first variable display device 4B) that variably displays a plurality of types of identification information that can be identified based on the fact that the second start condition is satisfied after the And when the display result of the variable display of the identification information by the first variable display means is a predetermined combination of specific identification information, or the variable display of the identification information by the second variable display means Is the specific identification information When a combination a gaming machine to control the advantageous specific game state for the player,
Random number generating means (for example, random number circuit 104) for generating a random number based on the establishment of the first start condition and the second start condition,
Game control means (for example, CPU 101) for controlling the progress of the game using the variable display of the first and second variable display means based on the random number value generated by the random number generation means;
With
The random number generating means includes
Numerical data updating means (for example, a reference clock signal generation circuit 201, a count clock signal generation circuit 202, a counter 203) for updating and outputting numerical data at a predetermined cycle;
In response to a first latch signal (for example, the rising edge of the first latch signal SLA), a first random value storage unit (for example, a first random value storage unit) that stores the numerical data output from the numerical data update unit as a random value. 1 random value storage circuit 205A),
In response to a second latch signal (for example, the rising edge of the second latch signal SLB), a second random value storage unit (for example, a first random number value storage unit) that stores the numerical data output from the numerical data update unit as a random value. 2 random value storage circuit 205B),
Latch timing signal generating means (for example, a count) that generates a first latch timing signal indicating the output timing of the first latch signal and a second latch timing signal indicating the output timing of the second latch signal A clock signal generation circuit 202, a mask circuit 211, a quaternary counter 212),
A first start signal (for example, a start signal SSA) input based on the establishment of the first start condition is used as a first latch timing signal (for example, a signal) generated by the latch timing signal generating means. First latch signal output means (for example, first latch signal output circuit) that outputs the first latch signal (for example, latch signal SLA) to the first random value storage means in synchronization with the rise of S2A 204A)
A second start signal (for example, a start signal SSA) input based on the establishment of the second start condition is used as a second latch timing signal (for example, a signal) generated by the latch timing signal generating means. In synchronization with the rising edge of S2B, second latch signal output means (for example, a second latch signal output circuit) outputs the second latch signal (for example, latch signal SLB) to the second random number value storage means. 204B), and
The latch timing signal output means is configured so that each period from when the numerical data update means updates the numerical data to when it is updated next (for example, a period from when the counter 203 updates the count value to when it is updated next). The first latch timing signal (the rising edge of the latch clock signal S2A) and the second latch timing signal (the rising edge of the latch clock signal S2B) are output so that only one of the latch timing signals is output. Each outputs periodically,
The game control means includes
The random number value stored in the first random value storage means and the random value stored in the second random value storage means are respectively stored in the first random value storage means and the second random value value storage. Storage means (for example, RAM 102) for reading out and storing from the means;
Based on the establishment of the first start condition, the random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. By determining whether or not it matches the value data, it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the second start condition is satisfied Based on this, it is determined whether or not the random value generated by the establishment of the second start condition that triggered the second start condition and stored in the storage means matches the predetermined determination value data. Accordingly, viewed including a display result determining means for determining whether a specific display results display result in the variable display in the second variable display means (e.g., the portion CPU103 is executing the processing in step S 111), the ,
The latch timing signal generation means (for example, the count clock signal generation circuit 202 in FIG. 12) is a signal having a cycle that is twice a predetermined cycle that is a cycle in which the numeric data update unit updates numeric data. And the second latch timing signal having a period twice as long as the predetermined period and having a phase shifted by 180 ° from the first latch timing signal. It is characterized by.

In the gaming machine according to claim 2 of the present application,
Based on the fact that the first start condition is satisfied after the first start condition (for example, winning to the first ordinary variable winning ball apparatus 5A) is satisfied, a plurality of types of identification information that can be identified are variable. The first variable display means for displaying (for example, the first variable display device 4A) and the second starting condition (for example, the second ordinary variable winning ball device 5B) different from the first starting condition. Second variable display means (for example, the first variable display device 4B) that variably displays a plurality of types of identification information that can be identified based on the fact that the second start condition is satisfied after the And when the display result of the variable display of the identification information by the first variable display means is a predetermined combination of specific identification information, or the variable display of the identification information by the second variable display means Is the specific identification information When a combination a gaming machine to control the advantageous specific game state for the player,
Random number generating means (for example, random number circuit 104) for generating a random number based on the establishment of the first start condition and the second start condition,
Game control means (for example, CPU 101) for controlling the progress of the game using the variable display of the first and second variable display means based on the random number value generated by the random number generation means;
With
The random number generating means includes
Numerical data updating means (for example, a reference clock signal generation circuit 201, a count clock signal generation circuit 202, a counter 203) for updating and outputting numerical data at a predetermined cycle;
In response to a first latch signal (for example, the rising edge of the first latch signal SLA), a first random value storage unit (for example, a first random value storage unit) that stores the numerical data output from the numerical data update unit as a random value. 1 random value storage circuit 205A),
In response to a second latch signal (for example, the rising edge of the second latch signal SLB), a second random value storage unit (for example, a first random number value storage unit) that stores the numerical data output from the numerical data update unit as a random value. 2 random value storage circuit 205B),
Latch timing signal generating means (for example, a count) that generates a first latch timing signal indicating the output timing of the first latch signal and a second latch timing signal indicating the output timing of the second latch signal A clock signal generation circuit 202, a mask circuit 211, a quaternary counter 212),
A first start signal (for example, a start signal SSA) input based on the establishment of the first start condition is used as a first latch timing signal (for example, a signal) generated by the latch timing signal generating means. First latch signal output means (for example, first latch signal output circuit) that outputs the first latch signal (for example, latch signal SLA) to the first random value storage means in synchronization with the rise of S2A 204A)
A second start signal (for example, a start signal SSA) input based on the establishment of the second start condition is used as a second latch timing signal (for example, a signal) generated by the latch timing signal generating means. In synchronization with the rising edge of S2B, second latch signal output means (for example, a second latch signal output circuit) outputs the second latch signal (for example, latch signal SLB) to the second random number value storage means. 204B), and
The latch timing signal output means is configured so that each period from when the numerical data update means updates the numerical data to when it is updated next (for example, a period from when the counter 203 updates the count value to when it is updated next). The first latch timing signal (the rising edge of the latch clock signal S2A) and the second latch timing signal (the rising edge of the latch clock signal S2B) are output so that only one of the latch timing signals is output. Each outputs periodically,
The game control means includes
The random number value stored in the first random number storage means and the random value stored in the second random value storage means are respectively stored in the first random value storage means and the second random value storage. Storage means (for example, RAM 102) for reading out and storing from the means;
Based on the establishment of the first start condition, the random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. By determining whether or not it matches the value data, it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the second start condition is satisfied Based on this, it is determined whether or not the random value generated by the establishment of the second start condition that triggered the second start condition and stored in the storage means matches the predetermined determination value data. Display result determining means (for example, a portion where the CPU 103 executes the process of step S111) for determining whether or not the display result in the variable display by the second variable display means is the specific display result,
The latch timing signal generating means (for example, the count clock signal generating circuit 202, the mask circuit 211, and the quaternary counter 212) has a cycle that is n times (n is a natural number) that the numerical data updating means updates the numerical data. And a first latch timing signal that is a signal having a period that is m times the predetermined period (where m is a natural number different from n), and the second latch timing signal. And

The present invention has the following effects.
According to the gaming apparatus of claims 1 and 2 , random numbers for a plurality of variable display means can be extracted using one numerical data updating means, and the circuit efficiency is good. In addition, since the timing for latching the numerical data is shifted between the first and second random value storage means, there is no possibility that both of the random value storage means store one numerical data in common.
Furthermore, a latch timing signal with a shifted timing can be generated with a simple configuration.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The gaming machine in the present embodiment is a gaming machine that performs a special game using a display device such as an LCD, and is a card reader (CR: Pachinko) gaming machine that lends a ball using a prepaid card.

  FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 that constitutes a gaming board surface, and a gaming machine frame (base frame) 3 that supports and fixes the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails. A first variable display device 4A and a second variable display device 4B that variably display special symbols as identification information that can be individually identified are provided at approximately the center position of the game area. The first and second variable display devices 4A and 4B are composed of, for example, an LCD. Below the first and second variable display devices 4A and 4B, a first ordinary variable winning ball device (starting winning port) 5A and a second ordinary variable winning ball device (starting winning port) 5B are arranged, respectively. ing. Further, below the first and second ordinary variable winning ball devices 5A and 5B, a first special variable winning ball device (large winning port) 6A and a second special variable winning ball device (large winning port) 6B, respectively. And are provided.

  In the variable display game (special game) in which the start condition (first start condition) is established based on the fact that the game ball has won the first ordinary variable winning ball apparatus 5A, The special symbols, which are composed of pictures and the like and function as plural types of identification information that can be identified, are variably displayed on a variable display section as a plurality of display areas. In the variable display game (special game) in which the start condition (second start condition) is established based on the game ball winning in the second ordinary variable winning ball apparatus 5B, the second variable display device 4B The special symbols, which are composed of pictures and the like and function as plural types of identification information that can be identified, are variably displayed on a variable display section as a plurality of display areas.

  In a special game played by the first and second variable display devices 4A and 4B, after a specific time has elapsed after starting the variable display of special symbols, the variable display results of the special symbols on each variable display unit are displayed in a predetermined order. The display is derived and displayed, and the confirmed symbol (final stop symbol) is stopped and displayed. At this time, if a specific combination of special symbols (a jackpot combination) is derived and displayed as a combination of fixed symbols (stop symbol form) in the special symbol game by the first variable display device 4A, the first special variable winning ball device 6A is displayed. A specific gaming state (big hit gaming state) is achieved by opening and closing the. In the jackpot gaming state based on the winning combination combination being derived and displayed in the special figure game by the first variable display device 4A, the opening / closing plate of the first special variable winning ball device 6A has a predetermined period (for example, 29 seconds) or a predetermined number. The game ball is opened in a period until (for example, 10) winning balls are generated, and the game ball that falls on the surface of the game board 2 is received while being opened, and then closed. The opening / closing cycle can be repeated up to a predetermined upper limit number of times (for example, 16 times).

  On the other hand, if the big hit combination is derived and displayed as the combination of the confirmed symbols in the special figure game by the second variable display device 4B, the specific game state (big hit game state) is achieved by opening and closing the second special variable winning ball device 6B. . In the jackpot gaming state based on the winning combination combination derived and displayed in the special game by the second variable display device 4B, the opening / closing plate of the second special variable winning ball device 6B has a predetermined period (for example, 29 seconds) or a predetermined number. The game ball is opened in a period until (for example, 10) winning balls are generated. While the ball is being opened, the game ball falling on the surface of the game board 2 is received and then closed. The opening / closing cycle can be repeated up to a predetermined upper limit number of times (for example, 16 times).

  As described above, in the first variable display device 4A and the second variable display device 4B, the special game is started on the basis that different starting conditions are satisfied. When the big win combination is derived and displayed as the combination of the determined symbols in the first variable display device 4A, the big special game state is controlled by opening and closing the first special variable winning ball device 6A. On the other hand, when the big hit combination is derived and displayed as the combination of the fixed symbols in the second variable display device 4B, the big special game state is controlled by opening and closing the second special variable winning ball device 6B. Note that the opening / closing operation modes of the first and second special variable winning ball devices 6A and 6B in the big hit gaming state may be set to be different from each other. For example, the first special variable winning ball apparatus 6A can repeat the opening / closing cycle of opening and closing the opening / closing plate up to 30 times in the period until 9 seconds or 5 winning balls are generated in the big hit gaming state. On the other hand, the second special variable winning ball device 6B can repeat the opening / closing cycle of opening and closing the opening / closing plate up to 5 times in the period until 49 seconds or 20 winning balls are generated in the big hit gaming state. Also good.

  In this embodiment, three variable display portions of left, middle, and right are provided as display areas in the first and second variable display devices 4A and 4B, respectively. ”To“ 9 ”can be variably displayed as 10 special symbols. Each symbol is arranged with a symbol number of “0” to “9”. When variable symbol special display is started, switching display and scroll display are performed in the order of symbol number, and symbol numbers are displayed. When the special symbol “9” or “0” is displayed, the special symbol whose symbol number is “0” or “9” is displayed. In the special game with each of the first and second variable display devices 4A and 4B, after the variable display of the special symbol is started, for example, the same special symbol or predetermined value is set in each of the left, middle and right variable display units. The first variable display in which the final symbol combination of the big hit combination is stopped and displayed when the final symbol combination that is a big hit combination is stopped and displayed, such as the combination of the special symbols received is stopped and displayed as the final display result. Corresponding to the device 4A or the second variable display device 4B, the pachinko gaming machine 1 becomes a big hit gaming state by opening and closing the first special variable winning ball device 6A or the second special variable winning ball device 6B.

  The first and second ordinary variable winning ball devices 5A, 5B have a tulip shape having a pair of movable wing pieces that are movable and controlled between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid (not shown). Each accessory (ordinary electric accessory) is provided. Each of the first and second ordinary variable winning ball devices 5A and 5B is provided with a start winning port switch, and a game ball winning for one of the first and second ordinary variable winning ball devices 5A and 5B is started. One of the first and second start conditions is met in response to the detection by the winning opening switch.

  The first and second special variable winning ball devices 6A and 6B are each provided with an opening / closing plate that opens and closes a winning area by a solenoid (not shown). The opening / closing plate is in a closed state at a normal time, for example, before the big hit gaming state occurs after the pachinko gaming machine 1 is powered on. On the other hand, when a big hit gaming state is achieved based on the result of the special game by the first variable display device 4A or the second variable display device 4B, a predetermined period or a predetermined number of winning balls are generated in the winning area by the solenoid. After opening in this period, it closes. When a game ball is won in the winning area when the first and second special variable winning ball devices 6A and 6B are opened, the game ball is detected by a predetermined big winning opening switch. Based on this, a predetermined number of prize balls are paid out.

  In addition to the above configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an outlet, a normal symbol display, and the like. Speakers 8L and 8R for reproducing and outputting sound effects and the like are provided at the left and right upper positions of the gaming machine frame 3, and a game effect lamp 9 is provided at the periphery of the game area.

The pachinko gaming machine 1 is mounted with a main board 11 and a display control board 12 as shown in FIG.
The main board 11 has start winning opening switches arranged in the first and second ordinary variable winning ball apparatuses 5A and 5B, and large winning opening switches provided in the first and second special variable winning ball apparatuses 6A and 6B. Also, wiring from each winning opening switch 70 including a switch for detecting a winning of a game ball to the winning opening and the like is also connected.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function for setting random numbers used in a special game, a function for inputting a signal from a switch or the like arranged at a predetermined position, and a sub-side control comprising a display control board 12 and a payout control board. Each board has a function of outputting and transmitting a control command as an example of command information as a control signal, and a function of outputting various kinds of information to a hall management computer.

  As the display control commands transmitted from the main board 11 to the display control board 12, for example, first and second variable display start commands corresponding to the first and second variable display devices 4A and 4B, First and second special symbol designation commands, first and second special symbol confirmation commands, and the like are prepared.

  The first and second variable display start commands are commands for instructing to start variable display of special symbols in the first and second variable display devices 4A and 4B. The variable display device 4A is instructed to start variable display of the special symbol, and the second variable display start command is instructed to start variable symbol display of the special symbol in the second variable display device 4B. On the display control board 12 side, in response to the first and second variable display start commands, the total variable display time of the special symbol, the determination result of whether or not the display result of the variable display is a big hit, and reach. The determination result of whether or not is specified.

  Here, the reach is a display mode in which variable display is performed for a symbol that has not yet been derived and displayed (referred to as a reach variation symbol) when the symbol that has been derived and displayed constitutes a part of the jackpot combination, or This is a display mode in which all or some of the symbols are synchronously variably displayed while constituting all or part of the jackpot symbol. Specifically, on a combination effective line that has not been stopped and displayed when a special symbol constituting a predetermined jackpot combination is stopped and displayed on some variable display portions on a predetermined combination effective line. The display mode in which variable display is performed in the variable display section (for example, the left, middle and right variable display sections provided in the display area are part of the jackpot symbol in the left and middle variable display sections. (For example, “7”) is displayed in a stopped state and the variable display portion on the right is still in a variable display state), or all or some of the special symbols on the variable display portion on the active line are displayed. A display mode in which variable display is performed synchronously while constituting all or part of the jackpot symbol (for example, in which state the variable display is performed on all of the left, middle, and right variable display portions provided in the display area. Even if is displayed, the same special symbol Tsu variable display in it have aspect is a display mode) that it has been made.

  The first and second special symbol designation commands correspond to the first and second variable display devices 4A and 4B, respectively, when starting the variable display of special symbols on the variable display devices 4A and 4B. This is a command for designating a special symbol as a fixed symbol that is derived and displayed in the middle variable display section and becomes a variable display result in a special game. The first and second special symbol confirmation commands are commands for instructing the end of variable symbol special display corresponding to each of the first and second variable display devices 4A and 4B.

  The main board 11 includes, for example, a game control microcomputer 100, a switch circuit 107, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and is controlled according to a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a program. A CPU (Central Processing Unit) 103 that performs operations, a random number circuit 104 that generates random numbers independently of the CPU 103, and an I / O (Input / Output) port 105 are included. The switch circuit 107 takes in the detection signal from each winning opening switch 70 and transmits it to the game control microcomputer 100.

The random number circuit 104 counts numerical data serving as a jackpot determination random number. As a specific example, the CPU 103 sets a random number generation operation by the random number circuit 104, and generates a jackpot determination random number by periodically (or irregularly) updating numerical data according to a predetermined procedure. The big hit determination random number is a random number used to determine whether or not the pachinko gaming machine 1 is put into the big hit gaming state by generating a big hit, and takes a value in the range of “0” to “65535”.
A specific configuration of the random number circuit 104 will be described later with reference to FIG.

  Note that random numbers other than the jackpot determination random number, for example, a definite symbol determination random number, a reach determination random number, a variable display pattern determination random number, and the like are generated by executing a random number program stored in the ROM 101. Here, the fixed symbol determining random number is a display random number used for determining the fixed symbol of the special symbol in the special symbol game. The reach determination random number indicates whether to determine and display the final symbol of the losing without reaching, if the final symbol is not a jackpot combination in the special game. This is a display random number used for determination. The random number for variable display pattern determination is a random number for display that is used to determine the variable display pattern used in the special figure game and to define the variable display mode and other effects of the special symbol in the special figure game. is there. In addition, in order to improve a game effect, random numbers other than the above may be used.

  In addition to the game control program, the ROM 101 stores various data tables used for controlling the progress of the game. For example, the ROM 101 stores a plurality of determination tables and determination tables prepared for the CPU 103 to perform various determinations and determinations. This determination table includes a jackpot determination table that is referred to in order to determine whether or not the determined symbol is a jackpot combination in the special figure game. In addition, the determination table includes a variable display pattern determination table for determining a variable display pattern used in the special game by each of the first and second variable display devices 4A and 4B.

  In the RAM 102, a game ball is won in one of the first and second ordinary variable winning ball devices 5A and 5B, and a special game by either the first or second variable display device 4A or 4B is executed. 1st and 2nd variable display of the hold information of the special figure game in which the condition for starting the variable display is not satisfied because the condition is satisfied but the previous special figure game is being executed. There are provided first and second special figure storage units for storing corresponding to each of the devices 4A, 4B. For example, the first special figure holding memory unit is associated with the first ordinary variable winning ball device 5A, the second special figure holding memory unit is associated with the second ordinary variable winning ball device 5B, and each is associated with each other. In addition, in the order of winning in the ordinary variable winning ball devices 5A and 5B, the storage number is a predetermined upper limit value (for example, “4”), which is the number of the hold number and the numerical data indicating the value of the jackpot determination random number extracted by the winning. Remember until you reach.

  In addition, the RAM 102 is set with a plurality of types of flags that are set or cleared in accordance with the gaming state in the pachinko gaming machine 1, the signal transmitted from each winning port switch 70 via the switch circuit 107, and the like. A game control flag setting area, a game control timer setting area for storing data indicating a plurality of types of timer values used for game control in the pachinko gaming machine 1, and the like may be provided. Note that a circuit used for setting a flag or a timer may be configured by a register circuit provided separately from the RAM 102.

  In the game control flag setting area, for example, corresponding to each of the first and second variable display devices 4A and 4B, a special symbol process flag (first and second special symbol process flag), a big hit flag (first and second) The second big hit flag) is provided. The first and second special symbol process flags should be selected and executed in the first and second special symbol process processing executed corresponding to each of the first and second variable display devices 4A and 4B. Instruct. The first and second big hit flags are determined that the variable display result in the special figure game is a big hit when the special figure game is started by each of the first and second variable display devices 4A and 4B. And set to the ON state. On the other hand, when the big hit gaming state ends, the big hit flag is cleared and turned off.

  In the game control timer setting area, for example, to realize a function as a variable display time timer (first and second variable display time timer) corresponding to each of the first and second variable display devices 4A and 4B. An area for storing data indicating the timer value is provided. The first and second variable display time timers measure on the main side the variable display time of the special symbol, which is the execution time of the special figure game by the corresponding one of the first and second variable display devices 4A and 4B. It is a down counter used for The first variable display time timer is determined according to the variable display pattern in the special game of the first variable display device 4A when the first variable display start command is sent from the main board 11 to the display control board 12. A timer initial value corresponding to the total variable display time is set. The second variable display time timer is determined according to the variable display pattern in the special game of the second variable display device 4B when the second variable display start command is sent from the main board 11 to the display control board 12. A timer initial value corresponding to the total variable display time is set.

  The display control board 12 is a sub-side control board independent of the main board 11, and controls display operations and the like in the first and second variable display devices 4A and 4B. For example, the display control board 12 causes the first and second variable display devices 4A and 4B to perform switching display of images based on a display control command transmitted from the main board 11, thereby displaying a special symbol in the special figure game. Various display effects such as variable display and display of the number of rounds in the big hit gaming state are possible.

Next, details of the random number circuit 104 will be described with reference to FIG.
As shown in FIG. 3, the random number circuit 104 includes a reference clock signal generation circuit 201, a count clock signal generation circuit 202, a counter 203, a first latch signal output circuit 204A, and a first random value storage circuit 205A. And a second latch signal output circuit 204B and a second random value storage circuit 205B.

  The reference clock signal generation circuit 201 outputs a reference clock signal S0 having a predetermined frequency, for example, 20 MHz, as shown in FIG.

  The count clock signal generation circuit 202 is composed of a D-type flip-flop, the reference clock signal S0 is supplied to the clock terminal Clk, the negative phase output (Q bar) signal S2 is fed back to the D input terminal, and the positive phase output Q is obtained. The counter 203 outputs the count clock signal S1, and the second latch signal output circuit 204B outputs it as a latch clock (latch timing) signal S2B.

  The counter 203 is composed of an up counter, and counts up the count value C from “0” to “65535” one by one in response to the rising edge of the count clock signal S1. When the counter 203 counts up the count value C to “65535”, the counter 203 returns to “0” and counts up to “65535” again.

  The first latch signal output circuit 204A is composed of a D-type flip-flop, the input terminal D is an output terminal of a prize opening switch 70A disposed in the ordinary variable prize opening apparatus 5A, and the clock terminal Clk is a reference clock signal generation circuit. The output terminals 201 are respectively connected. The first latch signal output circuit 204A synchronizes the start winning signal SSA input from the input terminal D with the rising edge (latch timing signal) of the latch clock signal S2A input from the clock terminal Clk, and the latch signal (high signal). Level signal) SLA is output from the output terminal Q.

  The first random value storage circuit 205A latches the count value of the counter 203 in response to the rising edge of the latch signal SLA from the first latch signal output circuit 204A.

  FIG. 4 is a circuit diagram showing a configuration example of the first random value storage circuit 205A. As shown in the figure, the first random value storage circuit 205A includes two AND circuits 301 and 303, two NOT circuits 302 and 304, 16 flip-flop circuits 310 to 325, and 16 OR circuits. Circuits 330 to 345.

  The input terminal of the AND circuit 301 is connected to the output terminal Q of the first latch signal output circuit 204 </ b> A and the output terminal of the NOT circuit 304, and the output terminals are the input terminal of the NOT circuit 302 and the flip-flop circuits 310 to 325. The clock terminals Clk0 to Clk15 are connected. The input terminal of the NOT circuit 302 is connected to the output terminal of the AND circuit 301, and the output terminal is connected to one input terminal of the AND circuit 303.

  The input terminal of the AND circuit 303 is connected to the output terminal of the NOT circuit 302 and the I / O port 105 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 304. The input terminal of the NOT circuit 304 is connected to the output terminal of the AND circuit 303, and the output terminal is connected to one input terminal of the AND circuit 301 and one input terminal of each of the OR circuits 330 to 345.

  The input terminals D0 to D15 of the flip-flop circuits 310 to 325 are connected to the output terminal of the counter 203, and any one of 16 bits constituting the count value C is supplied. The clock terminals Clk0 to Clk15 of the flip-flop circuits 310 to 325 are connected to the output terminal of the AND circuit 301, and the output terminals Q0 to Q15 are connected to the other input terminal of each of the OR circuits 330 to 345.

  The input terminals of the OR circuits 330 to 345 are connected to the output terminal of the NOT circuit 304 and the output terminals of the flip-flop circuits 310 to 325, and the output terminals are connected to the I / O port 105 of the game control microcomputer 100. ing.

  The second latch signal output circuit 204B shown in FIG. 3 is composed of a D-type flip-flop, and the input terminal D is counted as the output terminal of the prize opening switch 70B arranged in the ordinary variable prize opening apparatus 5B, and the clock terminal Clk is counted. Each is connected to the positive phase output terminal Q of the clock signal generation circuit 202. The second latch signal output circuit 204B synchronizes the start winning signal SSB input to the input terminal D with the rising edge (latch timing signal) of the second latch clock (timing) signal S2B input from the clock terminal Clk. And output from the output terminal Q as a second latch signal (high level signal) SLB.

  The latch clock signal S2A supplied to the clock terminal Clk of the first latch signal output circuit 204A and the latch clock signal S2B supplied to the clock terminal Clk of the second latch signal output circuit 204B are counted clock signal generations. The inverted signal is in the relationship between the reverse phase output and the normal phase output of the circuit 202 and is 180 ° out of phase.

  The second random value storage circuit 205B latches the count value of the counter 203 in response to the rising edge of the latch signal SLB from the second latch signal output circuit 204B. The configuration is substantially the same as the configuration of the first random value storage circuit 205A shown in FIG. However, the start winning signal is changed from SSA to SSB, the input clock signal is changed from S2A to S2B, the output signal (latch signal) is changed from SLA to SLB, and the read control signal is changed from SRCA to SRCB.

  The start winning signals SSA and SSB from the winning opening switches 70A and 70B arranged in the normal variable winning ball devices 5A and 5B are also supplied to the CPU 103. The CPU 103 is connected to the first random number storage circuit 205A and the second Each of the first special figure reservation memory and the second special figure reservation memory allocated in the RAM 102 is loaded with the count value (random number value) latched by the random number value storage circuit 205B. Store at the beginning of the entry.

  FIG. 5 is a timing chart for explaining the operation of the random number generation circuit 104.

  As shown in FIG. 5A, the reference clock signal generation circuit 201, for example, has a frequency of 20 MHz and rises from a low level to a high level at timings T11, T12,. The reference clock signal S 0 falling to the level is output to the count clock signal generation circuit 202.

  The count clock signal generation circuit 202 substantially divides the reference clock signal S0 by ½, and the count clock signal S1 of 10 MHz as shown in FIGS. 5B and 5C and its inverted signal are counted. The clock signal S2 is converted and output from the positive phase output terminal (Q) and the negative phase output terminal (Q bar).

  As shown in FIG. 5D, the counter 203 updates and outputs the count value (count value data) C in response to the rising edge of the count clock signal S1.

  The second latch clock signal S2 shown in FIG. 5C output from the count clock signal generation circuit 202 is supplied to the first latch signal shown in FIG. 5E at the clock terminal Clk of the first latch signal output circuit 204A. It is supplied as the clock signal S2A.

  The first latch signal output circuit 204A is configured to synchronize a start winning signal SSA output at the time of starting winning a prize as illustrated in FIG. 5G with a first latch clock signal (latch timing signal) S2A. The first latch signal SLA shown in 5 (H) is output.

The first random value storage circuit 205A latches the count value (random value) data in response to the first latch signal SLA (rising edge).
After that, the CPU 103 outputs a read control signal SRCA, reads the stored value, sets it in the special figure holding memory (if there is an empty space), and then turns off the read control signal SRCA to make it impossible to read.

  The positive phase (Q) output terminal of the count clock signal generation circuit 202 is supplied to the second latch signal output circuit 204B as the second latch clock signal S2B shown in FIG.

  As shown in FIGS. 5C to 5E, the first and second latch clock signals S2A and S2B have a cycle twice that of the count clock signal S1, that is, the count value update cycle of the counter 203. Are in a reverse phase relationship with each other being shifted by 180 °.

  The second latch signal output circuit 204B synchronizes with the second latch clock signal S2B a start winning signal SSB as illustrated in FIG. 5 (I) that is output at the time of starting winning, and is shown in FIG. 5 (J). The second latch signal SLB is output.

The second random value storage circuit 205B latches the count value (random value) data in response to the second latch signal SLB (rising edge).
Thereafter, the CPU 103 outputs a read control signal SRCB, reads the stored value, sets it in the special figure holding memory (if there is an empty space), and then turns off the read control signal SRCB to make it impossible to read.

  As shown in FIGS. 5D to 5F, the first and second latch clock signals S2A and S2B have two periods (the period of the count clock signal S1) in which the counter 203 updates the count value. It is in reverse phase with double period. For this reason, only one of these rising edges (latch timing) occurs in one count value of the counter 203 (period from when the count value is updated to when it is updated next). Accordingly, it is assumed that the game balls win the normal variable winning ball devices 5A and 5B almost simultaneously, and as shown in FIGS. 5G and 5I, the first and second start winning signals SSA and SSB almost simultaneously. As shown in FIGS. 5H and 5J, the timing at which the first and second latch clock signals (latch timing signals) S2A and S2B are output is different. The random number values stored in the second random number value storage circuits 205A and 205B are different. Therefore, although one counter 203 is used, a situation in which the random number value for the first variable display device 4A and the random value for the second variable display device 4B are synchronized is prevented.

  FIG. 6 is a block diagram illustrating a hardware configuration example of the display control board 12. The display control board 12 includes an oscillation circuit 110, a reset circuit 111, a display control CPU 112, a ROM 113, a RAM 114, first and second VDPs (Video Display Processors) 115A and 115B, first and second CGROMs 116A, 116B, and first and second VRAMs (Video RAMs) 117A and 117B. The first and second VDPs 115A and 115B, the first and second CGROMs 116A and 116B, and the first and second VRAMs 117A and 117B may be configured as one VDP, CGROM, and VRAM, respectively.

  The oscillation circuit 110 outputs a reference clock signal to the CPU 112, the first and second VDPs 115A and 115B, and the reset circuit 111 outputs a reset signal for resetting the CPU 112, the first and second VDPs 115A and 115B. It is. When the CPU 112 receives the display control command from the main board 11, the CPU 112 reads out control data for effect control from the ROM 113 while using the RAM 114 as a work area. Further, the CPU 112 sends a drawing command to the first and second VDPs 115A and 115B based on the read control data.

  The ROM 113 is a semiconductor memory that stores various control programs executed by the CPU 112, fixed parameters, and the like. The ROM 113 stores a plurality of types of variable display table data used for controlling the variable display mode of special symbols in the special symbol game by the first and second variable display devices 4A and 4B. For example, each variable display table data is configured to include a combination of a plurality of variable display time timer values and display control data serially written in time series, and an end code, and a special symbol variable display in a special game is started. Corresponding to the elapsed time (or the remaining variable display time of the special symbol in the special game), the variable display speed, display position, and size of the special symbol in each of the first and second variable display devices 4A and 4B. The display color, the background image, the display period in the display state, and other information related to the effect display are set in advance.

  The plurality of display control data included in each variable display table data is configured as display control information including, for example, read control information for designating read positions of image data in the first and second CGROMs 116A and 116B. Here, the reading position of the image data in the first and second CGROMs 116A and 116B is, for example, a storage address of the image data, a file name for storing the image data, or each stream when the image data is a stream type moving image data. An assigned identification number or the like may be designated. By referring to the variable display table data stored in the ROM 113, the CPU 112 reproduces an image corresponding to the timer values in the first and second display control time timers provided in the display control timer setting area of the RAM 114. The period (reproduction position) can be determined, and the display mode of the image in each of the first and second variable display devices 4A and 4B is controlled by sending a drawing command to each of the first and second VDPs 115. can do.

  The RAM 114 is a semiconductor memory used as a work area by the CPU 112. Display control for setting a plurality of types of flags that are set or cleared in the RAM 114 in accordance with the display state in each of the first and second variable display devices 4A and 4B, the display control command from the main board 11, and the like. Display control timer setting for storing data indicating a plurality of types of timer values for measuring various times used for controlling the display operation in each of the flag setting area and the first and second variable display devices 4A and 4B. An area or the like may be provided. Note that a circuit used for setting a flag or a timer may be constituted by a register circuit provided separately from the RAM 114.

  In the display control flag setting area, for example, display control process flags (first and second display control process flags) are provided corresponding to the first and second variable display devices 4A and 4B, respectively. Which of the first and second display control process flags should be selected and executed in the first and second display control process processes executed corresponding to the first and second variable display devices 4A and 4B, respectively. Instruct.

  In the display control timer setting area, for example, to realize a function as a display control time timer (first and second display control time timer) corresponding to each of the first and second variable display devices 4A and 4B. An area for storing data indicating the timer value is provided. The first and second display control time timers measure the variable display time of the special symbol, which is the execution time of the special symbol game by the corresponding one of the first and second variable display devices 4A and 4B, on the sub side, respectively. It is a down counter used for The first display control time timer is a timer corresponding to the total variable display time of the special symbol in the variable display pattern specified based on the content of the command when the first variable display start command is received from the main board 11. The initial value is set. The second display control time timer has a timer initial value corresponding to the total variable display time of the special symbol in the variable display pattern specified based on the content when the second variable display start command is received from the main board 11. Is set.

  The first and second VDPs 115A and 115B have a display control function and a high-speed drawing function for displaying images on the first and second variable display devices 4A and 4B, respectively, and images according to a drawing command from the CPU 112 Execute the process. The CPU 112 has a two-dimensional address space independent of the CPU 112, and the first and second VRAMs 117A and 117B are mapped thereto. For example, the first VDP 115A generates image data according to the data read from the first CGROM 116A and develops it on the first VRAM 117A. Then, R (red), G (green), B (blue) signals and a synchronization signal are output to the first variable display device 4A. On the other hand, the second VDP 115B generates image data according to the data read from the second CGROM 116B and develops it on the second VRAM 117B. Then, R, G, B signals and a synchronization signal are output to the second variable display device 4B.

  Each of the first and second CGROMs 116A and 116B is for storing various image data for displaying an image on each of the first and second variable display devices 4A and 4B. For example, in the first CGROM 116A, character image data that is frequently used among those displayed on the first variable display device 4A, specifically, a person, an animal, a character, a figure, a symbol, or the like is stored in advance. On the other hand, in the second CGROM 116B, character image data that is frequently used among the images displayed on the second variable display device 4B is stored in advance. The first VRAM 117A is a frame buffer memory for expanding the image data generated by the first VDP 115A. The second VRAM 117B is a frame buffer memory for expanding the image data generated by the second VDP 115B.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply voltage is supplied, the game control microcomputer 100 is activated, and the CPU 103 executes a predetermined game control main process. In this game control main process, the operation of each part of the pachinko gaming machine 1 is initialized and predetermined initial settings are performed. By executing such a game control main process, the CPU 103 is set to generate a timer interrupt periodically (for example, every 2 milliseconds).

Thereafter, in response to the timer interrupt, the CPU 103, as shown in FIG. 7, performs general processing (step S10), first special symbol process for special figure A (step S11), and second special symbol for special figure B. Process processing (step S12), first normal symbol process (step S13), second normal symbol process (step S14), command control processing (step 15), information output processing (step S16), solenoid output processing (step S17), winning ball processing (step SS18) is sequentially executed.
In the general process of step S10, a general process related to game control is executed.

  In the first special symbol process in step S11, the value of the first special symbol process flag provided in the game control flag setting area is updated according to the gaming state, and the display operation control or the first variable in the first variable display device 4A is performed. In order to set the opening / closing operation of the special variable winning ball apparatus 6A in a predetermined procedure, various processes are selected and executed. Subsequent to the first special symbol process, the second special symbol process is executed.

  In the second special symbol process in step S12, the value of the second special symbol process flag provided in the game control flag setting area is updated according to the gaming state, and the display operation control and the second variable display device 4B are controlled. In order to set the opening / closing operation of the 2 special variable winning ball apparatus 6B in a predetermined procedure, various processes are selected and executed.

  In step S13, the first normal symbol process is performed by a display operation (for example, lighting of a 7-segment LED or a lamp in a first normal symbol display provided in the game area or the like corresponding to the first normal variable winning ball apparatus 5A. , Extinction, etc.) are controlled to enable variable display (for example, lighting / blinking display) of the first normal symbol, setting of tilt control of the movable blade piece in the first normal variable winning ball apparatus 5A, and the like.

  The second normal symbol process in step S14 controls the display operation in the second normal symbol display provided in the game area or the like corresponding to the second normal variable winning ball device 5B, and the second normal symbol process is performed. Variable display and setting of the tilt control of the movable blade piece in the second ordinary variable winning ball apparatus 5B.

  In the command control process of step S15, a control command is transmitted from the main board 11 to a sub-side control board such as the display control board 12, and operation control in accordance with the gaming state is instructed. Furthermore, the contents of various output data storage areas are output to each output port included in the I / O port 105 by the information output processing in step S16. In this information output process, a command for outputting jackpot information, starting information, probability variation information, and the like to the hall management computer is also transmitted from the main board 11 to a predetermined information terminal board.

In the solenoid output process of step S17, when predetermined conditions are satisfied, the tilting control of the movable blade pieces in the first and second ordinary variable winning ball devices 5A and 5B and the first and second special variable winning ball devices 6A and 6B are performed. The opening / closing control of the opening / closing plate is performed.
Further, in the prize ball processing in step S18, the number of prize balls is set based on the detection signal input from each winning opening switch 70, and a payout control command can be output to a predetermined payout control board.

FIG. 8 is a flowchart showing details of the first special symbol process.
In the special symbol process shown in FIG. 8, the CPU 103 first determines whether or not a game ball has won a first normal variable winning ball device 5A provided in correspondence with the first variable display device 4A, for example, a first. The determination is made by checking a detection signal from a start winning port switch provided in the normal variable winning ball device 5A and included in each winning port switch 70 (step S100).

  When the game ball wins the normally variable winning ball apparatus 5A and the detection signal SSA from the start winning port switch 70 is turned on (step S100; Yes), a winning process is executed (step S101). On the other hand, when the game ball has not won (Step S100; No), the winning process is skipped.

  In the winning process in step S101, as shown in FIG. 9, the number of reserved memories in the first special figure reservation storage unit provided in the RAM 102 corresponding to the first variable display device 4A is the upper limit value (for example, “4”). It is determined whether or not this is the case (step S121). At this time, if the value of the jackpot determination random number corresponding to the upper limit value of the reservation number is stored in the first special figure reservation storage unit (step S121; Yes), the number of the stored storage is greater than or equal to the upper limit value. Determined. If the number of reserved memories is equal to or greater than the upper limit value, the start of the special figure game due to the current winning is invalid and nothing is performed. On the other hand, when the reserved storage number is less than the upper limit value (step S121; No), the read control signal SRCA is sent to the first random number value storage circuit 205A so that the first random number value storage circuit 205A can be read (enabled). ) State (step S122).

  Subsequently, the CPU 103 reads the random number value R from the first random value storage circuit 205A (step S123), and stores the read random number value R in, for example, a predetermined buffer area provided in the RAM 102 (step S124). ), The transmission of the output control signal SRCA to the first random value storage circuit 205A is stopped, and the reading is disabled (disabled) (step S125). Then, the CPU 103 adds “1” to the starting winning memory number (step S126), and sets the random number value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory (step S127).

  That is, as described with reference to FIGS. 3 to 5, in the random number circuit 104, the count clock signal generation circuit 202 generates the count clock signal S1 based on the reference clock signal S0. In response to the count clock signal S1, the counter 203 sequentially updates the count value. The start winning signal SSA from the start winning port switch 70A of the first ordinary variable winning ball apparatus 5A is also supplied to the first latch signal output circuit 203A, and the reverse phase output (Q bar) of the count clock signal generation circuit 202 is provided. Is output to the first random number storage circuit 205A as a latch signal SLA in synchronization with the first latch clock signal S2A output from the first random number storage circuit 205A. The first random value storage circuit 205A latches the count value output from the counter 203 in response to the latch signal SLA.

  When the number of reserved storages in the first special figure reservation storage unit provided in the RAM 102 is less than the upper limit value (for example, “4”), the CPU 103 stores the random number stored in the first random value storage circuit 205A. The numerical value is read out and set at the end of the first special figure storage unit.

  Thereafter, the CPU 103 performs the processes of steps S110 to S118 shown below according to the value of the first special symbol process flag provided in the game control flag setting area of the RAM 102 corresponding to the first variable display device 4A. Execute.

  The special symbol normal process of step S110 is executed when the value of the first special symbol process flag is “0”. This special symbol normal process includes a process of determining whether or not to start a special symbol game by the first variable display device 4A based on data stored in the first special symbol storage unit.

  The big hit determination process in step S111 is executed when the value of the first special symbol process flag is “1”. This jackpot determination process includes a process of determining whether or not the variable display result in the special figure game in which the start condition is satisfied is a jackpot.

  In this jackpot determination process, as shown in FIG. 10, the CPU 103 first reads a random value stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S131). At this time, “1” is subtracted from the reserved storage number, and the random number values stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure holding memory are shifted up by one entry. (Step S132).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S133). If the probability change is not in progress (step S133; No), the CPU 103 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table is set (step S134). On the other hand, if the probability change is in progress (step S133; Yes), the probability change big hit determination table is set (step S135).

  The CPU 103 determines whether or not the display result of the special figure game is a jackpot using the read random number value and the set jackpot determination table (step S136). If it is determined to be a big hit (step S136; Yes), the big hit state flag provided in the flag memory in the RAM 102 is set to the on state (step S137), and it is determined to be lost. (Step S136; No), the big hit state flag is cleared and turned off (step S138). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S139).

  The determined symbol setting process in step S112 is executed when the value of the first special symbol process flag is “2”. This fixed symbol setting process includes a process of setting a fixed symbol derived and displayed as a variable symbol display result of the special symbol in the special symbol game by the first variable display device 4A using software random numbers.

  The variable display pattern setting process in step S113 is executed when the value of the first special symbol process flag is “3”. The variable display pattern setting process executed when the value of the first special symbol process flag is “3” is based on the combination of the fixed symbols set in the fixed symbol setting process in step S112. This includes processing for selecting and determining a variable display pattern to be used in the special figure game by the device 4A. Corresponding to the fixed symbol set in the fixed symbol setting process in step S112 and the variable display pattern selected and determined in the variable display pattern setting process in step S113, for example, control data is stored in a predetermined command transmission table. For example, the first variable display start command and the first special symbol designation command are set to be transmittable from the main board 11 to the display control board 12 by being set. Thereafter, the command control process in step S15 shown in FIG. 7 is executed, whereby the first variable display start command and the first special symbol designation command are transmitted from the main board 11 to the display control board 12.

  When the variable display pattern for big hit is selected and determined in response to the first big hit flag being turned on in the variable display pattern setting process in step S113, the second big hit flag is checked, for example. 2 The second variable display, such as the fact that the special variable winning ball apparatus 6B is in the big hit game state by the opening / closing operation and the second variable display apparatus 4B derives and displays the big hit combination in the special figure game being executed. It is desirable to detect that the game state is controlled to the big hit gaming state based on the variable display result in the special figure game by the device 4B. When it is detected that the game is controlled to the big hit gaming state, the special display is used as the variable display pattern used in the special figure game by the first variable display device 4A as compared with the time required for the big hit gaming state to end. A variable display pattern having a sufficiently long total variable display time is selected and determined.

  The variable display control process in step S114 is executed when the value of the first special symbol process flag is “4”. The variable display control process is performed by the first variable display device 4A based on the timer value in the first variable display time timer provided in the game control timer setting area such as the RAM 102 corresponding to the first variable display device 4A. This includes processing for measuring the remaining variable display time of special symbols in the figure game. The variable display stop process in step S115 is executed when the value of the first special symbol process flag is “5”. In the variable display stop process, a setting for transmitting a first special symbol confirmation command for instructing deceleration stop of the special symbol variably displayed on the first variable display device 4A to the display control board 12 is performed. This includes processing to be performed. In the variable display stop process in step S115, the value of the first special symbol process flag is updated to “6” when the big hit combination is derived and displayed as a variable display result in the special game by the first variable display device 4A. The On the other hand, when the lost combination is derived and displayed as the variable display result, the value of the first special symbol process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S116 is executed when the value of the first special symbol process flag is “6”. This pre-opening process for the big prize opening includes an initialization process in a big hit operation such as opening / closing an opening / closing plate in the first special variable winning ball apparatus 6A. The special winning opening opening process in step S117 is executed when the value of the first special symbol process flag is “7”. This process during opening of the big prize opening includes various processes related to the big hit operation such as opening and closing the opening / closing plate in the first special variable winning ball apparatus 6A, and the opening time per time in the first special variable winning ball apparatus 6A. Includes processing to check. The jackpot end process in step S118 is executed when the value of the first special symbol process flag is “8”. The jackpot end process includes a process of determining whether or not the jackpot operation by the first special variable winning ball apparatus 6A is finished, and transmitting the command for instructing the jackpot end to the display control board 12 if finished. Yes.

  In the second special symbol process in step S14 shown in FIG. 7, a process in which the first special symbol process shown in FIG. 8 is adapted to the second variable display device 4B is executed.

  For example, in the process in which the winning process in step S101 shown in FIG. 8 is adapted to the second variable display device 4B, the reserved storage in the second special figure reservation storage unit provided in the RAM 102 corresponding to the second variable display device 4B. It is determined whether or not the number is equal to or greater than the upper limit value. If the number is less than the upper limit value, the reserved memory number is incremented by 1 and the jackpot determination random number obtained from the random number circuit 104 is stored in the second special figure reserved memory. Set to the beginning of the empty entry in the section. Thereafter, the CPU 103 performs a process in which the processes in steps S110 to S118 shown in FIG. 8 are adapted to the second variable display device 4B, in accordance with the second variable display device 4B, in the game control flag setting area of the RAM 102. Is selected and executed in accordance with the value of the second special symbol process flag provided in.

  For example, the special symbol normal process executed when the value of the second special symbol process flag is “0” is based on the data stored in the second special symbol holding storage unit and the special symbol by the second variable display device 4B. This includes processing for determining whether or not to start the game. If it is determined in the jackpot determination process that is executed when the value of the second special symbol process flag is “1” that the variable display result is a jackpot, the RAM 102 corresponds to the second variable display device 4B. When the second big hit flag provided in the game control flag setting area is set to the on state and it is determined that the game is lost, the second big hit flag is cleared and turned off.

  Next, the operation of the display control CPU 112 mounted on the display control board 12 will be described. In the display control board 12, the CPU 112 determines whether or not a timer interrupt flag provided in a display control flag setting area such as the RAM 114 is turned on, for example, to generate a timer interrupt every 33 milliseconds. For example, various timer interrupt processing programs stored in advance in the ROM 101 or the like for display control are executed. For example, each time the CPU 112 detects the occurrence of a timer interrupt, the CPU 112 executes first and second display control process processes corresponding to the first and second variable display devices 4A and 4B, respectively. In the first display control process, the value of the first display control process flag provided in the display control flag setting area is used to control the display operation in the first variable display device 4A in a predetermined procedure. Updating is performed according to the display state in 4A, and various processes provided in advance corresponding to the value of the first display control process flag are selected and executed. In the second display control process, the value of the second display control process flag provided in the display control flag setting area is set to the second variable in order to control the display operation in the second variable display device 4B according to a predetermined procedure. Updating is performed according to the display state on the display device 4B, and various processes provided in advance corresponding to the value of the second display control process flag are selected and executed.

  FIG. 11 is a flowchart illustrating an example of processing executed by the CPU 112 as the first display control process. In the first display control process shown in FIG. 8, the CPU 112 selects and executes each of the following steps S150 to S153 according to the value of the first display control process flag.

  The variable display start command reception waiting process in step S150 is executed when the value of the first display control process flag is “0”. This variable display start command reception waiting process determines whether or not the first variable display start command for instructing the variable display start command to start variable display of the special symbol in the special figure game by the first variable display device 4A is received from the main board 11. Processing. The special symbol variable display start process in step S151 is executed when the value of the first display control process flag is “1”. This special symbol variable display start processing is performed by, for example, a plurality of types of variable stored in the ROM 113 in order to produce various display effects including variable symbol special display in the special symbol game by the first variable display device 4A. This includes processing for setting the display operation of the first variable display device 4A, such as processing for selecting the one corresponding to the variable display pattern from the display table data.

  The special symbol variable display in-process in step S152 is executed when the value of the first display control process flag is “2”, and the display of the special symbol being changed is controlled.

  The special symbol stop waiting process of step S153 shown in FIG. 11 is executed when the value of the first display control process flag is “3”, receives the first special symbol confirmation command from the main board 11 and receives the first variable. The display device 4A includes a process of stopping and displaying a fixed symbol on each of the left, middle, and right variable display portions.

  As the second special symbol process S12 corresponding to the second variable display device 4B, a process in which the first special symbol process shown in FIG. 8 is adapted to the second variable display device 4B may be executed. For example, the CPU 112 provides, in the display control flag setting area of the RAM 114, processing corresponding to the second variable display device 4B corresponding to the processing of steps S110 to S118 shown in FIG. The selected second display control process flag is selected and executed according to the value of the second display control process flag.

As described above, according to the present invention, a special game using two variable display devices 4A and 4B becomes possible.
Also, a timing for latching a random value used for the jackpot determination in the special game in the first variable display device 4A and a random value used in the jackpot determination in the special game in the second variable display device 4B. Since the output timings of the first latch signal SLA and the second latch signal SLB are adjusted so that they are different from each other, problems such as fetching the same random number value or synchronizing the random number may occur in both special-purpose games. Therefore, the jackpot state is established with appropriate randomness, and the fun of the game can be enhanced.

The present invention is not limited to the above embodiment, and various modifications and applications are possible.
For example, in the above embodiment, the first latch clock signal S2A and the second latch clock signal S2B are signals having the same cycle and a phase difference of 180 °, but the first and second latch clock signals S2A are different. As for the period and the duty between S2B and S2B, the rising of the latch clock signals SLA and SLB (latch timing signal) occurs only once during each period from when the counter 203 updates the count value data to the next update. If so, it is optional.

  For example, the first latch clock signal S2A is as shown in FIG. 13F, and the second latch clock signal S2B is set with a period, waveform, duty, etc. as shown in FIG. 13G. Also good.

  In the example of FIG. 12, as shown in FIG. 13G, in the second latch clock signal S2B, a rising edge (latch timing signal) is generated once while the count value 4 is updated four times. As shown in FIG. 13F, the first latch clock signal S2A rises during a period other than the period when the second latch clock signal S2B rises. Even with such a technique, the random number value storage timing of the first random number value storage circuit 205A and the second random number value storage circuit 205B is different, and the random number value stored in the first random number value storage circuit 205A is different from the random number value stored in the first random number value storage circuit 205A. A situation in which the random number value stored in the second random value storage circuit 205B is synchronized can be prevented.

  The method of generating the first and second latch clock signals S2A and S2B is arbitrary. For example, as shown in FIG. 12, a mask circuit 211 and a quaternary counter 212 are added to the circuit of FIG. This can be achieved.

  The mask circuit 211 internally generates a mask signal as shown in FIG. 13E in accordance with the second count clock signal S2 shown in FIG. 13C from the reverse phase output (Q bar) of the count clock signal generation circuit 202. When the mask signal is off, the gate is opened and the input signal S2 is output as it is. When the mask signal is on, the gate is closed and the output signal is clamped to a low level. As a result, FIG. This is a circuit for outputting the first latch clock signal shown in FIG.

  Further, the quaternary counter 212 counts the falling edge of the first count clock signal S1 from the positive phase output (Q) of the count clock signal generation circuit 202, and every time four falling edges are counted, one clock is counted. This is a circuit that outputs a high level signal only for a period, and as a result, outputs a second latch clock signal S2B shown in FIG.

  In the present invention, two or more N variable display devices may be arranged. In that case, a circuit that latches the count value of one counter at different timings may be provided.

Further, for example, a special game executed by the first variable display device 4A and the second variable display device 4B. Further, for example, a special game executed by the first variable display device 4A and the second variable display device 4B. May have some linkage (one game affects the other).

  In addition, the gaming machine of the present invention is capable of variably displaying special symbols on the first and second variable display devices 4A and 4B based on, for example, winning of game balls on the first and second ordinary variable winning ball devices 5A and 5B. It is not limited to the pachinko gaming machine 1 that satisfies the conditions for starting the game machine, and includes at least two variable display units that variably display each of a plurality of types of identification information that can be identified. The present invention can be applied to any gaming machine that has a gaming state advantageous to the player when the display result of the variable display is a combination of specific identification information. For example, it is possible to start a game by setting the number of bets for one game, and the display result of the variable display device is derived and displayed, so that one game is completed, and the display result of the variable display device is displayed. In response to this, a slot machine or the like that can generate a predetermined prize may be used.

Note that the random number circuit shown in FIG. 3 may be used to generate a final stop symbol or a random number for generating a variable display pattern using the random number circuit of FIG.
In this case, the CPU 103 appropriately outputs a latch instruction signal to the first latch signal output circuit 204A or the second latch signal output circuit 204B, and latches the count value of the counter 203.
In this case, the CPU 103 appropriately outputs a latch instruction signal to the first latch signal output circuit 204A or the second latch signal output circuit 204B, and latches the count value of the counter 203.

  Further, in order to take timing, the signal rising etch is mainly used, but it is naturally possible to use a falling edge or the like.

  Further, the count value of the counter 203 may be an odd number, a multiple of 3 or a prime number, and different count values may be counted as the count is repeated.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the system configuration example in a pachinko gaming machine. It is a figure which shows the structure of a random number circuit. It is a figure which shows the structural example of a random value storage circuit. 6 is a timing chart for explaining the operation of the random number circuit shown in FIGS. 3 and 4. It is a block diagram which shows an example of the hardware constitutions in a display control board. It is a flowchart which shows a game control interruption process. It is a flowchart which shows a 1st special symbol process process. It is a flowchart of a winning process. It is a flowchart of jackpot determination processing. It is a flowchart which shows a 1st display control process process. It is a figure which shows the other structural example of a random number circuit. 13 is a timing chart for explaining the operation of the random number circuit shown in FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4A, 4B ... Variable display apparatus 5A, 5B ... Normal variable winning ball apparatus 6A, 6B ... Special variable winning ball apparatus 8L, 8R ... Speaker 9 ... Game effect lamp DESCRIPTION OF SYMBOLS 11 ... Main board 12 ... Display control board 70 ... Each winning prize switch 100 ... Microcomputer 101, 113 for game control ROM
102, 114 ... RAM
103, 112 ... CPU
104 ... random number circuit 105 ... I / O port 107 ... switch circuit 110 ... oscillation circuit 111 ... reset circuit 115A, 115B ... VDP
116A, 116B ... CGROM
117A, 117B ... VRAM

Claims (2)

First variable display means for variably displaying a plurality of types of identification information that can be identified based on the fact that the first start condition is satisfied after the first start condition is satisfied, and the first start condition A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the second start condition being satisfied after the second start condition different from the second start condition is satisfied, When the display result of variable display of identification information by the first variable display means is a combination of specific identification information determined in advance, or the display result of variable display of identification information by the second variable display means A gaming machine that controls a specific gaming state advantageous to the player when the combination of the specific identification information is provided,
Random number generating means for generating random numbers based on the establishment of the first start condition and the second start condition,
Game control means for controlling the progress of the game using the variable display of the first and second variable display means based on the random number value generated by the random number generation means;
With
The random number generating means includes
Numeric data updating means for updating and outputting numeric data at a predetermined cycle;
First random value storage means for storing numerical data output from the numerical data update means as a random value in response to a first latch signal;
Second random value storage means for storing numerical data output from the numerical data update means as a random value in response to a second latch signal;
Latch timing signal generating means for generating a first latch timing signal indicating an output timing of the first latch signal and a second latch timing signal indicating an output timing of the second latch signal;
A first start signal input based on the establishment of the first start condition is synchronized with the first latch timing signal generated by the latch timing signal generation means as a first latch signal. First latch signal output means for outputting to the first random value storage means;
A second start signal input based on the establishment of the second start condition is synchronized with the second latch timing signal generated by the latch timing signal generation means as a second latch signal. Second latch signal output means for outputting to the second random value storage means,
The latch timing signal generation means is configured to update the first latch timing signal and the second latch timing signal during each period from the time when the numerical data update means updates the numerical data until the next update. Each one is output periodically so that only one of the latch timing signals is output,
The game control means includes
The random number value stored in the first random value storage means and the random value stored in the second random value storage means are respectively stored in the first random value storage means and the second random value value storage. Storage means for reading and storing from the means;
Based on the establishment of the first start condition, the random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. By determining whether or not it matches the value data, it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the second start condition is satisfied Based on this, it is determined whether or not the random value generated by the establishment of the second start condition that triggered the second start condition and stored in the storage means matches the predetermined determination value data. Accordingly, it viewed including a display result determining means for determining whether a specific display results display result in the variable display in the second variable display means, and
The latch timing signal generation means includes the first latch timing signal, which is a signal having a period twice as long as a period in which the numerical data updating means updates the numerical data, and twice the predetermined period. Outputting the second latch timing signal having a period and having a phase shifted by 180 ° from the first latch timing signal;
A gaming machine characterized by that.   First variable display means for variably displaying a plurality of types of identification information that can be identified based on the fact that the first start condition is satisfied after the first start condition is satisfied, and the first start condition A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the second start condition being satisfied after the second start condition different from the second start condition is satisfied, When the display result of variable display of identification information by the first variable display means is a combination of specific identification information determined in advance, or the display result of variable display of identification information by the second variable display means A gaming machine that controls a specific gaming state advantageous to the player when the combination of the specific identification information is provided,
  Random number generating means for generating random numbers based on the establishment of the first start condition and the second start condition,
  Game control means for controlling the progress of the game using the variable display of the first and second variable display means based on the random number value generated by the random number generation means;
With
  The random number generating means includes
  Numeric data updating means for updating and outputting numeric data at a predetermined cycle;
  First random value storage means for storing numerical data output from the numerical data update means as a random value in response to a first latch signal;
  Second random value storage means for storing numerical data output from the numerical data update means as a random value in response to a second latch signal;
  Latch timing signal generating means for generating a first latch timing signal indicating an output timing of the first latch signal and a second latch timing signal indicating an output timing of the second latch signal;
  A first start signal input based on the establishment of the first start condition is synchronized with the first latch timing signal generated by the latch timing signal generation means as a first latch signal. First latch signal output means for outputting to the first random value storage means;
  A second start signal input based on the establishment of the second start condition is synchronized with the second latch timing signal generated by the latch timing signal generation means as a second latch signal. Second latch signal output means for outputting to the second random value storage means,
  The latch timing signal generation means is configured to update the first latch timing signal and the second latch timing signal during each period from the time when the numerical data update means updates the numerical data until the next update. Each one is output periodically so that only one of the latch timing signals is output,
  The game control means includes
  The random number value stored in the first random value storage means and the random value stored in the second random value storage means are respectively stored in the first random value storage means and the second random value storage. Storage means for reading and storing from the means;
  Based on the establishment of the first start condition, a random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. By determining whether or not it matches the value data, it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the second start condition is satisfied Based on this, it is determined whether or not the random value generated by the establishment of the second start condition that triggered the second start condition and stored in the storage means matches the predetermined determination value data. Display result determination means for determining whether or not the display result in the variable display by the second variable display means is the specific display result,
  The latch timing signal generating means includes the first latch timing signal, which is a signal having a period n times (n is a natural number) that the numerical data updating means updates the numerical data, and m ( m is a natural number different from n) and outputs the second latch timing signal which is a signal having a period that is twice as long.
A gaming machine characterized by that.

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