JP2005319051A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely and stably acquire a random number value and to prevent malfunctions in the generation and acquisition of the random number value in the case that reset occurs. <P>SOLUTION: A clock signal generation circuit 172 latches signals fed back from an opposite phase output terminal Q(bar) in response to the rising edge of reference clock signals S0. A counter 173 updates a count value C at a timing at which output signals from a positive phase output terminal Q rise to be high and a latch signal output circuit 174 outputs latch signals SL at a timing at which the output signals from the opposite phase output terminal Q(bar) rise to be high. Additionally, wiring for transmitting reset signals RST from a CPU 103 is connected to the direct reset terminal DR of the latch signal output circuit 174 and the latch signal output circuit 174 is reset by the reset signals RST. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays, and that is in a specific gaming state that is advantageous for a player when a display result of identification information becomes a specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  Currently, in game machines, a random number used to determine whether or not to make a “big hit” (a big hit determination random number) is generated by the CPU executing a predetermined application program. However, such a random number generation method has a problem that the processing load on the CPU at the time of generation increases.

As a solution to such a problem, a random number circuit is used to generate a jackpot determination random number, for example, a count value sequence consisting of count values updated cyclically within a predetermined range from a clock pulse is generated. A gaming machine or the like that outputs a random number after sampling based on a predetermined timing signal is disclosed (for example, see Patent Document 1).
JP-A-7-124296 (page 3-4, FIG. 1).

In addition, the count value updated in response to the rising edge of the clock pulse (or the inverted clock pulse obtained by inverting this clock pulse) is based on the latch signal synchronized with the rising edge of the inverted clock pulse (or clock pulse). A gaming machine or the like that stores a random number value is also disclosed (see, for example, Patent Document 2).
Japanese Patent Laying-Open No. 2003-190483 (page 5-12, FIG. 2).

  However, in the gaming machine described in Patent Document 1, since the clock pulse and the timing signal are output from different components, the count value being updated is output as a random value depending on the output timing of the timing signal. There is a possibility that the random number value cannot be acquired reliably and stably.

  Further, in the gaming machine described in Patent Document 2, when the falling edge of the clock pulse is gentle, the rising edge of the inverted clock pulse also becomes gentle. Therefore, the output of the latch signal synchronized with the rising edge of the inverted clock pulse There is a possibility that the timing becomes unstable, and acquisition of the random number value cannot be performed reliably and stably.

  Furthermore, the gaming machine described in any of Patent Document 1 and Patent Document 2 does not consider any operation when a reset occurs due to, for example, detecting a decrease in power supply voltage. Therefore, even when a reset occurs in the gaming machine, the latch signal output operation and random number value acquisition operation are performed in the same manner as when no reset occurs. For this reason, for example, an erroneous operation such as an erroneous count value being stored as a random number value or a stored random value being erroneously read occurs due to the influence of noise caused by a decrease in power supply voltage or the like. There was a thing.

  The present invention has been made in view of the above circumstances, and provides a gaming machine that can reliably and stably acquire a random value and prevent malfunction in generation and acquisition of a random value when a reset occurs. With the goal.

  In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4, a variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous variable display and the end of the big hit gaming state) A gaming machine (for example, a pachinko gaming machine 1) that has a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when the display result of the identification information is a specific display result, Game control means for controlling (for example, a game control microcomputer 100 mounted on the main board 11) and random number generating means for generating random numbers (for example, random R) (for example, random number generation) Path 17 and the like, and voltage monitoring means (for example, power supply voltage monitoring circuit 18 and the like) for monitoring a power supply voltage (for example, VSL) supplied to the gaming machine, and the random number generation means has a reference clock having a predetermined cycle Reference clock signal output means (for example, reference clock signal output circuit 171) for outputting a signal (for example, reference clock signal S0) and clock signal generation for generating a plurality of signals having the same period and different phases based on the reference clock signal Means (for example, a clock signal generation circuit 172), and the clock signal generation means includes a clock terminal (for example, an input terminal CK of the clock signal generation circuit 172) to which the reference clock signal is input from the reference clock signal output means. An input terminal to which the first signal is input (for example, an input terminal D of the clock signal generation circuit 172); The timing at which the change state of the first signal changes every predetermined cycle of the reference clock signal input from the clock terminal (for example, timings T10, T11, T10 when the reference clock signal S0 rises from a low level to a high level) A signal synchronized with T12,..., And the like is synchronized with the first output terminal (for example, the positive phase output terminal Q of the clock signal generation circuit 172) and the signal output from the first output terminal has the same period and phase. A second output terminal that outputs different signals (for example, a reverse phase output terminal Q (bar) of the clock signal generation circuit 172), and the clock signal generation means includes the second output terminal and the input terminal. By connecting, the first clock signal output from the first output terminal (for example, the clock signal for counting S1) and the second output terminal are output. And generating a second clock signal (for example, a latch count signal S2) having the same period and a different phase from the first clock signal, and the random number generating means is generated by the clock signal generating means. Numerical data is updated at a first timing when the first clock signal changes in the predetermined manner (for example, timing T10, T12, T14,..., When the counting clock signal S1 rises from a low level to a high level). Numerical data updating means (for example, a counter 173) that performs the second timing when the second clock signal generated by the clock signal generating means changes in the predetermined manner (for example, the latch clock signal S2 changes from low level to high level). At the timing of rising to the level T11, T13, T15,. In response to a latch signal output from the latch signal output means (for example, latch signal output circuit 174) and the latch signal output means, the numerical data updated by the numerical data update means is stored as a random value. Including the random value storage means (for example, the random value storage circuit 175), and the voltage monitoring means detects the occurrence of power interruption when the power supply voltage becomes a predetermined value or less (for example, VSL becomes + 22V or less). System reset signal output means for outputting a system reset signal (for example, system reset signal SRST) to the game control means (for example, a power supply lowering signal indicating that the power supply monitoring IC 301 has detected the occurrence of power interruption (power supply interruption) Signal) from the output terminal REST as the system reset signal SRST and supplied to the main board 11 The game control means reads a random value from the random value storage means based on the fact that the execution condition is satisfied, and the read random value is a predetermined determination value data (for example, “2001 to 2184”). Display result determining means for determining whether or not the display result in the variable display is set as the specific display result (for example, the CPU 103 receives the winning in step S102). And a latch output reset signal (for example, reset signal RST) to the latch signal output means in response to the system reset signal input from the system reset signal output means Latch output resetting means (for example, resetting the latch signal output means by outputting) For example, when the reset control circuit 105 causes the output signal of the system reset extension circuit 311 and the reset control signal RC output via the AND circuit 314 to fall from the high level to the low level, the CPU 103 executes the process of step S53. In response to this, the latch signal output circuit 174 is supplied with a reset signal RST).

  In the gaming machine according to claim 2, the game control means includes a game control microcomputer (for example, a game control microcomputer 100) for executing a game control process, and a predetermined abnormality process performed by the game control microcomputer. (For example, pressing the reset switch, executing the user program outside the designated area, falling of the user reset signal URST due to timeout in the watchdog timer (WDT), rising of the IWT signal, rising of the WDT timeout signal, etc.) Abnormality processing detection means (for example, AND circuits 313, 314 and user reset extension circuit 312 in the reset control circuit 105), and the latch output reset means is configured to detect the predetermined abnormality by the abnormality processing detection means. When it is detected that the processing has been performed, a latch output reset signal is output to the random number value storage means, thereby resetting the latch signal output means, for example, a latch output reset means (for example, a reset control circuit 105). When the reset control signal RC output from the user reset extension circuit 312 and the AND circuits 313 and 314 falls from the high level to the low level, the CPU 103 latches according to the execution of the process of step S53. The signal output circuit 174 includes a portion where the reset signal RST is output.

  In the gaming machine according to claim 3, a start signal output unit (for example, a start winning port switch 70) that outputs a start signal (for example, a start winning signal SS) to the random number generating unit based on the execution condition being satisfied. And the latch signal output means uses the start signal input from the start signal output means at a second timing when the second clock signal generated by the clock signal generation means changes in the predetermined manner. Output as a latch signal.

  In the gaming machine according to claim 4, the random number generation means measures a time during which a start signal is input from the start signal output means, and the measured time becomes a predetermined time (for example, 3 ms). A timer means (for example, a timer circuit 176) for outputting the start signal to the latch signal output means.

  6. The gaming machine according to claim 5, wherein the start signal output means outputs a start signal to the game control means, and the game control means receives an interrupt request signal periodically (for example, every 2 ms). In response to the timer interrupt processing execution means (for example, a portion where the CPU 103 executes the game control interrupt processing) for executing the timer interrupt processing, and the display result determination means is controlled by the timer interrupt processing execution means. Based on the fact that the start signal is continuously input from the start signal output means while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms), the random number value storage means A random number value is read, and the timer means sets setting time (for example, a time shorter than the time when the timer interruption process is executed by the timer interruption process execution means as the predetermined time). The timer circuit 176 includes a portion for setting 3 ms as a time shorter than 4 ms, which is the execution time of the two timer interruption processes, and the measured time is set to a time set as a predetermined time by the setting means When this happens, the start signal is output to the latch signal output means.

  7. The gaming machine according to claim 6, further comprising start signal output means (for example, a start prize opening switch 70) for outputting a start signal to the game control means on the basis that the execution condition is satisfied, And means for generating a latch start signal (for example, a latch start prize signal SN) based on the input of the start signal from the start signal output means and outputting the latch start signal output means to the random number generating means. (For example, the portion where the CPU 103 executes the winning process in step S102), the latch signal output means has generated the latch start signal input from the latch start signal output means by the clock signal generation means. A latch signal is output at a second timing when the second clock signal changes in the predetermined manner.

  8. The gaming machine according to claim 7, wherein the game control means executes a timer interrupt process in response to an interrupt request signal input periodically (for example, every 2 ms). (For example, the part where the CPU 103 executes game control interrupt processing) and the timer interrupt processing execution means is executing the timer interrupt processing a predetermined number of times (for example, twice) (for example, for 4 ms), the start Starting signal determining means for determining whether or not the starting signal is continuously input from the signal output means (for example, a portion where the CPU 103 executes the process of step S102), and the latch start signal output means includes the When it is determined by the start signal determination means that the start signal has been continuously input (for example, when the CPU 103 determines Yes in step S102), A latch start signal is output to the random number generation means, and the display result determination means outputs the latch start signal by the latch start signal output means, and then the random number value is stored from the random value storage means in a timer interrupt process. Is read.

  In the gaming machine according to claim 8, the game control means outputs an output control signal (for example, an output control signal) to the random value storage means before the display result determination means reads the random value from the random value storage means. SC) is output to control the random value storage means to be readable, and after the display result determination means reads the random value from the random value storage means, the output control signal is output to the random value storage means. It includes read control means (for example, a portion where the CPU 103 executes the processing of step S131 and step S134) that stops and controls the random number value storage means to an unreadable state.

  10. The gaming machine according to claim 9, wherein the random value storage means is incapable of receiving the output control signal output from the read control means when the latch signal is input from the latch signal output means. Output control signal reception control means (for example, an AND circuit 203).

  11. The gaming machine according to claim 10, wherein when the output control signal is input from the read control means, the random value storage means cannot receive a latch signal output from the latch signal output means. Includes latch signal reception control means (for example, an AND circuit 201).

  The present invention has the following effects.

  According to the configuration of the first aspect, the random number generation means does not invert the reference clock signal output from the reference clock signal output means, and does not invert the first clock signal having the same period and different phase. 2 at the first timing when the first clock signal changes in the predetermined manner, the numerical data is updated, and the second clock signal changes in the predetermined manner. At the second timing, a latch signal is output. In this way, the random number generation means can reliably change the update timing of the numerical data and the latch timing of the numerical data, so that the game control means can reliably acquire the random value. It can be performed stably. Further, according to this configuration, the game control means reads the random value from the random value storage means only when the execution condition is satisfied, and therefore it is possible to omit useless processing. Further, the latch output reset means outputs a latch output reset signal to the latch signal output means in response to a system reset signal input from the system reset signal output means upon detection of a voltage drop. Therefore, for example, the display result determination unit may read out the stored random number value by erroneously outputting a latch signal from the latch signal output unit to the random value storage unit due to the influence of noise or the like. Can be prevented.

  According to the configuration of claim 2, when the abnormal process random number storage reset means detects that the gaming control microcomputer has performed a predetermined abnormal process by the abnormal process detection means, Since the stored reset signal is output to the random value storage means and the random value storage means is reset, even when the gaming control microcomputer performs a predetermined abnormality process, for example, due to the influence of noise, etc. It is possible to prevent a malfunction such as the display result determining means reading out the random value stored in the random value storing means.

  According to the configuration of the third aspect, the latch signal output means can output the start signal input from the start signal output means as a latch signal at the second timing. For this reason, acquisition of the random number value can be performed reliably and stably. Further, since the start signal from the start signal output means is directly input to the latch signal output means, the difference between the output timing of the start winning signal and the output timing of the latch signal can be reduced, and the player is distrusted. There is no feeling.

  According to the configuration of claim 4, the random number generation unit does not directly output the start signal input from the start signal output unit to the latch signal output unit, but the input time of the start signal is Measurement is performed by the timer means, and when the measurement time reaches a preset time, the start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting a latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration of claim 5, the timer means is set as the predetermined time that is shorter than the execution time of a predetermined number of timer interrupt processes by the timer interrupt process execution means. The random number value read by the display result determining means from the random value storage means can be prevented from becoming the same value as the previously read random number value.

  According to the configuration of the sixth aspect, the latch signal output means can output the latch start signal input from the game control means as a latch signal at the second timing. For this reason, acquisition of the random number value can be performed reliably and stably. The latch start signal output means outputs the latch start signal to the latch signal output means based on the input of the start signal from the start signal output means. There is no need to provide a path for supplying the start signal to the random number generating means. For this reason, the hardware configuration of the gaming machine can be simplified.

  According to the configuration of claim 7, it is determined that the start signal is continuously input while the timer interrupt process execution unit is executing a predetermined number of timer interrupt processes. When it is made by the signal judging means, a latch start signal is outputted to the random number generating means. Therefore, it is possible to prevent the latch start signal output means from erroneously outputting the latch start signal to the random number generating means due to the influence of noise or the like. Further, the display result determination means outputs the latch start signal by the latch start signal output means, and then reads the random value from the random value storage means in the timer interruption process. It is possible to prevent the read random number value from being the same as the previously read random value.

  According to the configuration of claim 8, the game control unit can make the random value storage unit readable only when the display result determination unit reads the random value. Acquisition can be performed reliably and stably.

  According to the configuration of claim 9, the random number generation unit is configured to change the random number value stored in the random number value storage unit from the random value storage unit by the display result determination unit. Can be prevented from being read out, the random number value can be updated reliably and stably.

  According to the configuration of claim 10, the random number generation unit stores the random number value stored in the random value storage unit when the display result determination unit reads the random value from the random number storage unit. Therefore, it is possible to reliably and stably acquire a random value.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is disposed. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. A normal symbol display 40 is provided on the right side of the special variable winning ball apparatus 7.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information by a plurality of variable display units. For example, a game ball wins a normal variable winning ball device 6. In the special figure game where is the execution condition, the variable display of three display symbols (special symbols) composed of numbers, letters, symbols, etc. is started, and after a certain period of time, they are displayed in the order of left, right, and middle Confirm the design. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. In addition, in the special game with the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, the pachinko The gaming machine 1 enters a special gaming state (probability improvement state) following the end of the jackpot gaming state, and thereafter, the probability that the display result in the special figure game becomes a jackpot combination is increased until a predetermined condition is satisfied. In the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 is configured with a light emitting diode (LED) or the like, and is lit, flashing, colored, etc. in a normal diagram game where the starting condition is that a game ball passes through a pass gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are movable and controlled between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 4). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in the special figure holding memory 110 (FIG. 4) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 4). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2), which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an outlet, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10, a main board 11, a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and an information terminal board 16. And are arranged at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 is installed independently of control boards (electrical component control boards) such as the main board 11, the display control board 12, the sound control board 13, the lamp control board 14, the payout control board 15, and the information terminal board 16. A predetermined power supply voltage is supplied to each control board and component in the pachinko gaming machine 1. The power supply substrate 10 receives, for example, a transformer that converts an AC voltage from an AC power source into a predetermined voltage value (for example, AC 24 V), a rectifier circuit that generates a DC voltage from the AC voltage, and an output voltage from the rectifier circuit, and receives a plurality of types. A DC-DC converter or the like that generates a DC voltage is provided. The power supply board 10 includes a power supply voltage monitoring circuit 18 that monitors the power supply voltage generated by the rectifier circuit. FIG. 3 is a circuit diagram showing a configuration example of the power supply voltage monitoring circuit 18.

  The power supply voltage monitoring circuit 18 is equipped with a power supply monitoring IC 301 wired as shown in FIG. 3, for example. The power supply monitoring IC 301 introduces a VSL power supply voltage (for example, DC + 30V) generated by rectifying and boosting AC24V with a rectifying element in the rectifier circuit in the power supply substrate 10, and monitors the VSL power supply voltage to supply power. Detect the occurrence of disconnection. Specifically, when the VSL power supply voltage becomes a predetermined value (for example, +22 V) or less, a voltage drop signal (power cut-off signal) is output from the output terminal RSET because the power cut occurs. Note that the power supply voltage to be monitored is preferably higher than the power supply voltage (for example, +5 V) of the circuit element mounted on each control board. In the example shown in FIG. 3, a VSL power supply voltage that is a voltage immediately after being converted from alternating current to direct current using a rectifier circuit or the like is used. A power-off signal from the power monitoring IC is supplied to the main board 11 and the like as a system reset signal SRST.

  The predetermined value for the power monitoring IC 301 to detect the power interruption is lower than the normal voltage, but the voltage at which the CPU on each control board (for example, the CPU 103 on the main board 11) can operate for a while. It is. Further, the power supply monitoring IC 301 is configured to monitor a voltage that is higher than a voltage (for example, + 5V) for driving a circuit element such as a CPU and immediately after being converted from alternating current to direct current. The monitoring range can be expanded with respect to the voltage required. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, the voltage supplied to various switches such as the start winning port switch 70 in the pachinko gaming machine 1 is +12 V. We can expect prevention. That is, when the voltage of the + 30V power supply is monitored, a voltage drop can be detected at a stage before + 12V generated after creating + 30V starts to drop.

  Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the power supply is turned on before the switch output shows the on state. It is possible to enter a state of waiting for recovery and not detect switch output.

  The power monitoring IC 301 is mounted on a power supply board 10 that is separate from the control board such as the main board 11. For this reason, a power-off signal can be supplied from the power monitoring IC 301 to a plurality of control boards. Even when there are a plurality of control boards that require a power-off signal, it is only necessary to provide one power monitoring configuration, so even if each control board performs return control, the cost of the pachinko gaming machine 1 is It does n’t rise that much.

  Note that a power-off signal that is a detection output from the power monitoring IC 301 may be transmitted to each control board via a predetermined buffer circuit. Alternatively, the configuration may be such that one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each control board. Furthermore, a buffer circuit corresponding to the number of substrates that require a power-off signal may be provided.

  The main board 11 is a main-side control board, and various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  FIG. 4 is a block diagram showing a circuit configuration and the like in the main board 11. As shown in FIG. 4, wiring is connected to the main board 11 from the display control board 12 and the random number generation circuit 17. In addition, wiring from the power supply voltage monitoring circuit 18 mounted on the power supply board 10 is also connected to the main board 11.

  The start winning opening switch 70 generates a start winning signal (high level signal) SS with the main board 11 and a random number based on detecting the winning of a game ball to the ordinary variable winning ball apparatus 6 which is the starting winning opening. This is output to the circuit 17.

  The main board 11 is also connected with wiring from a special variable winning ball apparatus 7 which is a big winning opening and a predetermined winning opening switch for detecting a winning of a game ball to other winning openings. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The main board 11 is configured by mounting a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101 that stores a game control program, a RAM (Random Access Memory) 102 that is used as a work memory, and a control. A central processing unit (CPU) 103 that performs operations, an input / output (I / O) port 104, and a reset control circuit 105 are incorporated.

  FIG. 5 is a circuit diagram illustrating a configuration example of the reset control circuit 105. The reset control circuit 105 shown in FIG. 5 includes a system reset extension circuit 311, a user reset extension circuit 312, and two AND circuits 313 and 314. The system reset terminal XSRST of the reset control circuit 105 is connected to the wiring from the power supply voltage monitoring circuit 18 mounted on the power supply board 10 and receives the supply of the system reset signal SRST. In addition, the user reset terminal XURST of the reset control circuit 105 is connected to a reset switch (not shown) installed in the pachinko gaming machine 1 and receives the user reset signal URST.

  The system reset extension circuit 311 extends the system reset signal SRST supplied to the system reset terminal XSRST of the reset control circuit 105 for a predetermined time and supplies it to the input terminal of the AND circuit 314. The user reset extension circuit 312 extends the reset signal supplied from the output terminal of the AND circuit 313 for a predetermined time and supplies it to the input terminal of the AND circuit 314.

  At the input terminal of the AND circuit 313, a user reset signal URST supplied to the user reset terminal XURST of the reset control circuit 105 and a designation from an out-of-designated area run inhibition (IAT) circuit built in the game control microcomputer 100 are provided. An inversion signal of the out-of-area running prohibition (IAT) signal and an inversion signal of a timeout signal from a watchdog timer (WDT) built in the game control microcomputer 100 are supplied. With this configuration, the output of the AND circuit 313 is that the user reset signal URST is at a high level, the out-of-designated area travel prohibition (IAT) signal is at a low level, and the timeout signal from the watchdog timer (WDT) is at a low level. In some cases, it becomes high level, and in other cases, it becomes low level.

  The user reset signal URST supplied to the user reset terminal XURST of the reset control circuit 105 starts from a high level when a reset operation is detected, for example, when a reset switch installed in the pachinko gaming machine 1 is pressed. Fall to low level. The out-of-designated area travel prohibition (IAT) signal is low when the user program is executed within the address range set in the program management area, and when the execution of the user program outside the designated area is detected, Stand up from low level to high level. The time-out signal from the watchdog timer (WDT) rises from a low level to a high level when a time-out time in a predetermined watchdog timer (WDT) has elapsed. Thus, when the user reset signal URST falls from the high level to the low level, or when the out-of-designated area running prohibition (IAT) signal rises from the low level to the high level, or the watchdog timer (WDT). When the time-out signal from the signal rises from the low level to the high level, the output of the AND circuit 313 falls from the high level to the low level, thereby generating a user reset due to a factor different from the decrease in the VSL power supply voltage.

  The input terminal of the AND circuit 314 is connected to the output terminal of the system reset extension circuit 311 and the output terminal of the user reset extension circuit 312. Therefore, the output of the AND circuit 314 becomes high level when both the output of the system reset extension circuit 311 and the output of the user reset extension circuit 312 are at high level, and becomes low level at other times. Thereby, when either system reset or user reset occurs, the reset control signal RC output from the reset control circuit 105 falls from the high level to the low level. A reset control signal RC output from the reset control circuit 105 is supplied to the CPU 103.

  As shown in FIG. 6, the game control microcomputer 100 includes a special figure holding memory 110, a jackpot determination table memory 111, a flag memory 112, and a start winning opening switch timer memory 113. .

  In the special figure holding memory 110, a condition (execution condition) for executing a variable symbol display (special symbol game) for a game ball winning the normal variable winning ball device 6 is established. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 110 includes four entries, and each entry has a holding number and a random number value R read from the random value storage circuit 175 in accordance with the winning order in the order of winning to the ordinary variable winning ball device 6. Are stored in association with each other. Each time the special symbol confirmation command is sent from the main board 11 to the display control board 12 and the special symbol variable display is finished once or the big hit gaming state is finished, the variable display based on the highest level information is performed. The start condition is satisfied, and variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. Further, when a game ball newly wins the normal variable winning ball apparatus 6 during variable display of a special symbol or the like, the random number value R read from the random value storage circuit 175 based on the winning is the highest empty. Registered in the entry.

  The jackpot determination table memory 111 stores a plurality of jackpot determination tables set in order for the CPU 103 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the big hit determination table memory 111 stores a normal big hit determination table 121 shown in FIG. 7A and a probability change big hit determination table 122 shown in FIG. 7B.

  Whether the normal big hit determination table 121 shown in FIG. 7 (A) and the probability variation big hit determination table 122 shown in FIG. 7 (B) use the display result of the special figure game by the variable display device 4 as a big hit. It is a table for determining whether or not. In each of the jackpot determination tables 121 and 122, a random value R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 122, more random numbers R are associated with the display result of “big hit” than in the normal big hit determination table 121. That is, by determining the display result of the special figure game using the probability change big hit determination table 122, it is possible to achieve a probability improvement state in which the probability of being in the big hit gaming state is higher than in the normal gaming state.

  In this embodiment, in the normal big hit determination table 121 shown in FIG. 7A, among the big hit determination random numbers R “0 to 65335” generated from the random number generation circuit 17, “2001 to 2184” is “big hit”. Is associated with the display result. On the other hand, in the probability variation jackpot determination table 121 shown in FIG. 7B, among the jackpot determination random numbers R “0 to 65335” generated from the random number generation circuit 17, “2001 to 3104” is a display result of “big hit”. Is associated.

  In the flag memory 112 shown in FIG. 6, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 112 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a timer interrupt flag, and the like.

  The special symbol process flag indicates which process should be selected / executed in the special symbol process (described later) (FIG. 16). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

  The input status flag is a flag composed of a plurality of bits that are set or cleared according to the status of various signals input to the I / O port 104. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The start winning port switch timer memory 113 is for storing a timer value that is added or cleared in accordance with the start winning signal SS input from the start winning port switch 70.

  The switch circuit 107 shown in FIG. 4 takes in the start winning signal SS from the start winning port switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives the solenoids 21 and 22 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The display control board 12 performs display control for image processing in the variable display game independently of the main board 11. Based on the display control command output from the main board 11, the display control board 12 displays an image used for the variable display game on the variable display device 4, and controls turning on / off the normal symbol display 40. . In other words, the display control board 12 controls the display operation of the variable display device 4 based on the control command from the main board 11, thereby controlling the effect by the image display related to the progress of the game.

  The audio control board 13 and the lamp control board 14 are sub-side controls that execute the audio output control and the lamp output control independently of the main board 11 based on the control command transmitted from the main board 11. It is a substrate. That is, the sound control board 13 controls the sound output operation by the speakers 8L and 8R based on the control command from the main board 11, thereby controlling the effect by the sound related to the progress of the game. In addition, the lamp control board 14 controls the lighting / flashing operation of the game effect lamp 9 based on the control command from the main board 11, thereby controlling the effect of lighting, blinking or extinguishing of the lamp related to the progress of the game. . The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  FIG. 8 is a block diagram showing a configuration of the random number generation circuit 17. As shown in FIG. 8, the random number generation circuit 17 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, a random value storage circuit 175, a timer circuit 176, , Is composed of. The random number generation circuit 17 generates a big hit determination random number for generating a big hit and determining whether or not the pachinko gaming machine 1 is in the big hit gaming state.

  The reference clock signal output circuit 171 generates a reference clock signal S0 having a predetermined frequency (for example, 20 MHz), and outputs the generated reference clock signal S0 to the clock signal generation circuit 172 and the timer circuit 176.

  The clock signal generation circuit 172 is configured by a D-type lip flop circuit or the like. The clock terminal CK of the clock signal generation circuit 172 is connected to the output terminal of the reference clock signal output circuit 171, and the positive phase output terminal Q is connected to the counter 173. Further, the anti-phase output terminal (inverted output terminal) Q (bar) of the clock signal generation circuit 172 is connected to the input terminal D and the clock terminal CK of the latch signal output circuit 174.

  The clock signal generation circuit 172 outputs a signal fed back from the reverse phase output terminal Q (bar) to the input terminal D at a timing when the reference clock signal S0 input from the reference clock signal output circuit 171 to the clock terminal CK rises. In synchronization, the signal is output from the positive phase output terminal Q, and the negative phase signal (inverted signal) of the signal output from the positive phase output terminal Q is output from the negative phase output terminal Q (bar). In this way, the clock signal generation circuit 172 generates two clock signals (counting clock signal S1 and latching clock signal S2) having the same cycle and different phases, and outputs the counting clock signal S1 in the positive phase. From the terminal Q, the latch clock signal S2 and the negative phase output signal S2 can be outputted from the negative phase output terminal Q (bar).

  Specifically, a count clock signal S1 having a frequency of 10 MHz is output from the positive phase output terminal Q, and a negative phase signal of the count clock signal S1, that is, a count is output from the negative phase output terminal Q (bar). Similarly to the clock signal S1, a latch clock signal S2 having a frequency of 10 MHz and having a phase different from that of the counting clock signal S1 by π (= 180 °) is output.

  The counter 173 circulates the output count value C from a predetermined initial value to a predetermined final value in response to the rising edge of the count clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Update to

  In this embodiment, the counter 173 is a 16-bit binary counter, and counts up the count value C from “0” to “65535” by 1 each time the rising edge of the count clock signal S1 is input. Go. When the count value C is counted up to “65535”, the count value C is returned to “0” and counted up to “65535” again. That is, the count value C is cyclically updated as “0” → “1” →... → “65535” → “0” →... Each time the rising edge of the count clock signal S1 is input to the counter 173. The

  The latch signal output circuit 174 is configured by a D-type lip flop circuit or the like. The input terminal D of the latch signal output circuit 174 is connected to the output terminal of the timer circuit 176, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175. Further, a direct reset terminal DR of the latch signal output circuit 174 is connected to the CPU 103 built in the game control microcomputer 100 and receives a reset signal RST.

  The latch signal output circuit 174 generates the latch signal SL by synchronizing the start winning signal SS input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK, and generates the output terminal Q. Output from. The latch signal output circuit 174 is cleared asynchronously to the input from the clock terminal CK when the reset signal RST directly input from the reset terminal DR falls from the high level to the low level. That is, when the reset signal RST directly input from the reset terminal DR is at the low level, the latch clock signal S2 input from the clock terminal CK is at the low level while the start winning signal SS is input from the input terminal D. The signal output from the output terminal Q is always at the low level even when the signal rises from the high level to the high level.

  A random value storage circuit 175 shown in FIG. 8 is a 16-bit register, and stores a random value R that is read in a winning process in step S102 described later. The random value storage circuit 175 latches and stores the count value C input from the counter 173 as the random value R in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174. Thus, every time the start winning signal SS is input to the random number generation circuit 17, the stored random number value R is sequentially updated.

  FIG. 9 is a circuit diagram showing a configuration example of the random value storage circuit 175. As shown in FIG. 9, the random value storage circuit 175 includes two AND circuits 201 and 203, two NOT circuits 202 and 204, 16 Philip flop circuits 210 to 225, and 16 OR circuits. 230-245.

  The input terminal of the AND circuit 201 is connected to the output terminal Q of the latch signal output circuit 174 and the output terminal of the NOT circuit 204, and the output terminal is the input terminal of the NOT circuit 202 and the clock terminal CK0 of the Philip flop circuits 210 to 225. To CK15. The input terminal of the NOT circuit 202 is connected to the output terminal of the AND circuit 201, and the output terminal is connected to one input terminal of the AND circuit 203.

  The input terminal of the AND circuit 203 is connected to the output terminal of the NOT circuit 202 and the I / O port 104 of the game control microcomputer 100, and the output terminal is connected to the input terminal of the NOT circuit 204. The input terminal of the NOT circuit 204 is connected to the output terminal of the AND circuit 203, and the output terminal is connected to one input terminal of the AND circuit 201 and one input terminal of each of the OR circuits 230 to 245.

  The input terminals D0 to D15 of the Philip flop circuits 210 to 225 are connected to the output terminal of the counter 173. The clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 are connected to the output terminal of the AND circuit 201, and the output terminals Q0 to Q15 are connected to the other input terminals of the OR circuits 230 to 245, respectively. The direct reset terminal DR of the Philip flop circuits 210 to 225 is connected to the CPU 103 built in the game control microcomputer 100 and receives a reset signal RST.

  The input terminals of the OR circuits 230 to 245 are connected to the output terminal of the NOT circuit 204 and each of the output terminals of the flip-flop circuits 210 to 225, and the output terminals are connected to the I / O port 104 of the game control microcomputer 100. It is connected.

  FIG. 10 is a diagram for explaining the details of the connection between the output terminals of the OR circuits 230 to 245 and the I / O port 104 of the game control microcomputer 100. In this embodiment, the output terminals of the OR circuits 230 to 245 and the bits of the jackpot determination random number input port included in the I / O port 104 are switched and connected as shown in FIG. Yes. Thereby, the randomness of the random number input to the game control microcomputer 100 can be enhanced.

  The operation of the random value storage circuit 175 having the above configuration will be described with reference to a timing chart shown in FIG.

  When the output control signal SC (high level signal) is not input from the gaming control microcomputer 100 (when one input of the AND circuit 203 is low level), the output terminal Q of the latch signal output circuit 174 At the timing when the input latch signal SL rises from low level to high level (in the example shown in FIG. 11, timings T1, T2, and T7), the inputs of the AND circuit 201 both become high level and are output from their output terminals. The signal SR becomes high level. The signal SR output from the AND circuit 201 is input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225.

  The flip-flop circuits 210 to 225 respond to the rising edges of the signal SR input from the clock terminals CK0 to CK15, and the bit data C0 to C15 of the count value C input from the counter 173 via the input terminals D0 to D15. Are latched and stored as bit data R0 to R15 of the random number value, and the bit data R0 to R15 of the stored random number value R are output from the output terminals Q0 to Q15.

  When the output control signal SC is not input (in the example shown in FIG. 11, in the period up to the timing T3, the period after the timing T6), one of the inputs of the AND circuit 203 is at a low level, so that the output is output from the output terminal. The signal SG to be output becomes a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Thus, since one input of the OR circuits 230 to 245 is at the high level, regardless of whether the signal input to the other input terminal is at the high level or the low level, that is, the input random number value. Regardless of whether the values of the R bit data R0 to R15 are “0” or “1”, the signals SO0 to SO15 output from the OR circuits 230 to 245 are all at a high level (“1”). Become. As a result, the value output from the random value storage circuit 175 is always “635535 (= 1111h)”, and the random value R cannot be read from the random value storage circuit 175. That is, when the output control signal SC is not input, the random value storage circuit 175 is in a non-readable (disabled) state.

  When the output control signal SC is input from the game control microcomputer 100 when the latch signal SL input from the latch signal output circuit 174 is at the low level (in the example shown in FIG. 11, from the timing T4 to the timing T6). Since the inputs of the AND circuit 203 are both at a high level, the signal SG output from the output terminal is at a high level. The signal SG is inverted in the NOT circuit 204, and a low level signal is input to one input terminal of each of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 is at a low level in this way, when a signal input to the other input terminal is at a high level, a high level signal is output from the output terminal, and a low level signal is output. When a low level signal is output. That is, the value of the bit data R0 to R15 of the random value R input to the other input terminals of the OR circuits 230 to 245 is directly from the output terminal of the OR circuits 230 to 245 (the value of the bit data R0 to R15 is “1”). "1" is output when it is "," and "0" is output when it is "0." As a result, the random value R can be read from the random value storage circuit 175. In other words, when the output control signal SC is input, the random value storage circuit 175 enters a readable (enable) state.

  However, if the latch signal SL is input from the latch signal output circuit 174 before the output control signal SC is input from the game control microcomputer 100, one input of the AND circuit 203 becomes low level. After that, even if the output control signal SC is input in the state where the latch signal SL is input (in the example shown in FIG. 11, it is output from the output terminal). The signal SG remains at a low level. The signal SG is inverted in the NOT circuit 204, and a high level signal is input to one of the input terminals of the OR circuits 230 to 245.

  Since one input of the OR circuits 230 to 245 becomes high level in this way, the output from the OR circuits 230 to 245 is performed regardless of whether the signal input to the other input terminal is high level or low level. All of the signals SO0 to SO15 are at a high level, and the random value R cannot be read from the random value storage circuit 175 even though the output control signal SC is input. That is, when the latch signal SL is input, the random value storage circuit 175 becomes incapable of receiving the output control signal SC.

  Further, when the output control signal SC is input from the game control microcomputer 100 before the latch signal SL input from the latch signal output circuit 174 becomes high level, one input of the AND circuit 201 is low level. Therefore, after that, even when the input latch signal SL becomes high level (in the example shown in FIG. 11, timing T5) while the output control signal SC is being input, the output is output from the output terminal. The signal SR to be kept remains at a low level. For this reason, the signal SR input to the clock terminals CK0 to CK15 of the Philip flop circuits 210 to 225 does not rise from the low level to the high level, and the bit data R0 of the random value R stored in the Philip flop circuits 210 to 225. ˜R15 are not updated even when the latch signal SL input from the latch signal output circuit 174 rises. That is, when the output control signal SC is input, the random value storage circuit 175 becomes incapable of receiving the latch signal SL.

  Further, when the reset signal RST directly input from the CPU 103 to the reset terminals DR0 to DR15 falls from the high level to the low level, the Philip flop circuits 210 to 225 are asynchronous with the signal SR input to the clock terminals CK0 to CK15. It is cleared with. Accordingly, when the reset signal RST output from the CPU 103 falls from the high level to the low level, the random number value storage circuit 175 is reset, and the stored random number value R is erased.

  The timer circuit 176 shown in FIG. 8 measures the time during which the start winning signal SS is input from the start winning port switch 70. When the measured time reaches a predetermined time (for example, 3 ms), the timer winning signal SS is displayed. The data is output to the latch signal output circuit 174.

  In this embodiment, the timer circuit 176 is constituted by, for example, an up counter or a down counter, and is activated in response to the input of a high level signal. While the input is at a high level, the timer circuit 176 counts up or down a predetermined timer value every time the reference clock signal S0 is input from the reference clock signal output circuit 171. When the timer value counted up or down reaches a value corresponding to 3 ms, the timer circuit 176 determines that the input signal is the start winning signal SS, and latches the start winning signal SS as a latch signal. Output to the output circuit 174.

  FIG. 12 is a timing chart for explaining the operation of the random number generation circuit 17.

  As shown in FIG. 12A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  In response to the rising edge of the reference clock signal S0 input from the clock terminal CK, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 12B, the positive-phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 12D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 12C, the counter 173 updates the count value C in response to the rising edge of the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 inputs the start winning signal SS shown in FIG. 12E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 12F is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as the random value R, the stored random value R is updated as shown in FIG.

  In this way, the random number generation circuit 17 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 13 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, register setting of a CTC (counter / timer circuit) built in the game control microcomputer 100 is performed. Thereby, thereafter, an interrupt request signal is sent from the CTC to the CPU 103 every predetermined time (for example, every 2 milliseconds), and the CPU 103 can periodically execute a timer interrupt process. When the initial setting is completed, interrupt processing is permitted (step S3), and then loop processing is started.

  CPU103 which performed the game control main process shown in FIG. 13 will perform the game control interruption process shown in the flowchart of FIG. 14, if the interruption request signal from CTC is received and an interruption request | requirement is received.

  When the game control interrupt process is started, the CPU 103 first executes a predetermined reset process (step S11). In the reset process, various settings are made to put each electrical component controlled by the main board 11 into an appropriate operation stop state in response to detection of occurrence of a system reset or a user reset.

  After executing the reset process, a predetermined switch process is executed (step S12). In the switch process, it is determined whether or not the start winning signal SS input from the start winning port switch 70 via the switch circuit 107 is in an ON state. When the start winning signal SS is on, the timer value is incremented by “1” and stored in the start winning port switch timer memory 113. On the other hand, when the start winning signal SS is in an off state, the timer value is cleared.

  Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary according to the diagnosis result (step S13). Thereafter, a determination random number update process for updating a predetermined determination random number (step S14) and a display random number update process for updating a predetermined display random number (step S15) are sequentially executed.

  Next, the CPU 103 executes special symbol process processing (step S16). In the special symbol process, the corresponding process is selected and executed according to the special symbol process flag provided in the flag memory 112 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state. Following the special symbol process, the CPU 103 executes a normal symbol process (step S17). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag provided in the flag memory 112 in order to control the normal symbol display 40 in a predetermined order.

  Furthermore, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the display control board 12 and perform operations such as an effect operation according to the gaming state. Control is instructed (step S18). For example, the CPU 103 controls the signal output operation from the I / O port 104 based on the control data set in the predetermined command transmission table, and so on, for the sub-side control board such as the display control board 12. A control signal for controlling the progress of the game is transmitted. The display control command sent from the main board 11 by the command control process is received by the CPU of the display control board 12, and the display control of the variable display device 4 and the lighting control of the normal symbol display 40 are performed according to the display control command. .

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S19). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to control the movable blade piece in the normal variable winning ball device 6 and open / close the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied. Driving is performed (step S20). Thereafter, by executing predetermined prize ball processing, the number of prize balls is set based on the start winning signal SS input from the start winning opening switch 70, and a payout control command is output to the payout control board 15. It is possible (step S21).

  FIG. 15 is a flowchart illustrating an example of the reset process executed in step S11. When the reset process is started, the CPU 103 first determines whether any one of the system reset and the user reset has occurred in the pachinko gaming machine 1 in the reset control signal RC input from the reset control circuit 105. A determination is made by checking the signal level (step S51). In step S51, when the reset signal supplied from the reset control circuit 105 is at a high level, the CPU 103 determines that no reset has occurred (step S51; No), and ends the reset process as it is. .

  On the other hand, when the reset signal from the reset control circuit 105 falls from the high level to the low level, it is determined that a reset has occurred (step S51; Yes). For example, the parity data for the data in the backup RAM area Is generated and stored in the RAM 102, or the RAM 102 is placed in an access-prohibited state, and a predetermined reset setting process corresponding to the occurrence of reset is executed (step S52). At this time, the CPU 103 sends a reset signal RST that falls from the high level to the low level to the latch signal output circuit 174 and the random value storage circuit 175 mounted in the random number generation circuit 17 (step S53). In response to the reset signal RST, the random number generation circuit 17 resets the latch signal output circuit 174 and the random value storage circuit 175.

  FIG. 16 is a flowchart showing the special symbol process executed in step S16. When the special symbol process is started, the CPU 103 first checks whether or not the game ball has won the normal variable winning ball device 6 by checking the timer value stored in the start winning port switch timer memory 113. It discriminate | determines (step S101). In step S101, the CPU 103 loads the timer value stored in the start winning a prize opening switch timer memory 113, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). As a result, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is performed a predetermined number of times (for example, twice) (for example, 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. When the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won a prize (step S101; Yes), the winning process is executed (step S102), and the timer value is set. clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S101; No), and the winning process is skipped.

  FIG. 17 is a flowchart showing the winning process in step S102. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S121). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S121; Yes), the start detection by the current winning is invalidated, and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S121; No), an output control signal SC is sent to the random value memory circuit 175, and the random value memory circuit 175 is controlled to be readable (enabled). (Step S122).

  Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S123), and stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S124). The transmission of the output control signal SC to the numerical value storage circuit 175 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S125). Then, the CPU 103 adds “1” to the starting winning memory number (step S126), and sets the random value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S127).

  Thereafter, the CPU 103 selects one of the nine processes of steps S110 to S118 shown in FIG. 16 based on the value of the special symbol process flag stored in the flag memory 112. Below, each process of step S110-S118 is demonstrated.

  The special symbol normal process of step S110 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the special figure reservation memory 110 is “0”. Here, in the special figure holding memory 110, when various data such as the random number R corresponding to the holding number “1” is not stored, it is determined that the holding memory number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S111 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 18, the CPU 103 first reads the random value R stored in correspondence with the hold number “1” from the special figure hold memory 110 (step S131). At this time, “1” is subtracted from the reserved storage number, and the random number R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory 110 is increased by one entry. (Step S132).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S133). If the probability change is not in progress (step S133; No), it is determined that the game state is the normal game state, and the special game As a table for determining whether or not the display result is a big hit, a normal big hit determination table 121 as shown in FIG. 7A is set (step S134). On the other hand, if the probability change is in progress (step S133; Yes), the probability change big hit determination table 122 as shown in FIG. 7B is set (step S135).

  Based on the random number value R read out in step S131, the CPU 103 determines whether or not to display the special game display result as a jackpot using the jackpot determination table 121 or 122 set in step S134 or S135 ( Step S136). If it is determined to be a big hit (step S136; Yes), the big hit state flag provided in the flag memory 112 is set to the on state (step S137), and if it is determined to be lost. (Step S136; No), the big hit state flag is cleared and turned off (Step S138). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S139).

  The confirmed symbol determination process in step S112 shown in FIG. 16 is a process executed when the value of the special symbol process flag is “2”. In this process, the CPU 103 determines whether or not the big hit state flag provided in the flag memory 112 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S113 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 103 first determines whether or not the big hit state flag provided in the flag memory 112 is turned on, and whether or not reach is determined in the determined symbol determination process in step S112. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in this special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 103 updates the value of the special symbol process flag to “4” which is a value corresponding to the variable display command process.

  The variable display command process of step S114 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 103 controls the variable display device 4 to start variable display for all the special symbols. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S112 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S113 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S115 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 103 makes settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be able to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether to return from the probability improved state to the normal gaming state, and if it is determined to return, the gaming state in the pachinko gaming machine 1 is changed from the probability improved state to the normal state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S116 is a process executed when the value of the special symbol process flag is “6”. In this processing, the CPU 103 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S117 is a process executed when the value of the special symbol process flag is “7”. In this process, the CPU 103 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number display of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S118 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 103 ends the jackpot gaming state by making a setting for sending a predetermined jackpot end command to the display control board 12. In addition, the CPU 103 clears the big hit state flag provided in the flag memory 112 and turns it off. Then, the value of the special symbol process flag is updated to “0”.

  As described above, according to this embodiment, the clock signal generation circuit 172 inputs the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  When a game ball wins the normal variable winning ball device 6 which is a starting winning port, the starting winning port switch 70 sends a starting winning signal SS to the main board 11 and the random number generating circuit 17, and the random number generating circuit. The start winning signal SS sent to 17 is input to the input terminal D of the latch signal output circuit 174 via the timer circuit 176. The latch signal output circuit 174 receives the start winning signal SS input to the input terminal D as the latch clock signal S2 input from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timing T11, T13, T15,... Rising from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  In this way, the random number generation circuit 17 can reliably vary the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Since the random number generation circuit 17 updates the count value C and outputs the latch signal SL without inverting the reference clock signal S0, the random number generation circuit 17 can update even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  On the other hand, on the main board 11 side, the CPU 103 continues the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). When it is detected that the input has been made, a winning process is executed.

  In this winning process, the CPU 103 sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 in a readable (enable) state, and then reads the random value R from the random value storage circuit 175. . Then, the CPU 103 stops sending the output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a non-readable state, and then the read random value R is set to a predetermined determination value “ It is determined whether or not the display result of the special game by the variable display device 4 is set to the big hit gaming state by determining whether or not it matches with “2001 to 2184” or the like.

  In this way, the pachinko gaming machine 1 can acquire the random number value more reliably and stably by controlling the random number value storage circuit 175 to the readable state only when the CPU 103 reads the random number value R. Can do. Further, since the CPU 103 reads the random value R from the random value storage circuit 175 only when the game ball wins the normal variable winning ball device 6 which is the start winning opening, the pachinko gaming machine 1 omits useless processing. be able to.

  The power supply voltage monitoring circuit 18 provided in the power supply board 10 is equipped with a power supply monitoring IC 301 that outputs a power-off signal as a system reset signal SRST when the VSL power supply voltage becomes a predetermined value (for example, +22 V) or less. A system reset signal SRST from the power monitoring IC 301 is input to the game control microcomputer 100 of the main board 11. In response to the fall of the system reset signal SRST from the high level to the low level, the reset control signal RC generated by the reset control circuit 105 mounted on the game control microcomputer 100 changes from the high level to the low level. Fall down to. When the reset control signal RC falls from the high level to the low level, the CPU 103 of the game control microcomputer 100 resets the reset signal RST to the latch signal output circuit 174 and the random value storage circuit 175 of the random number generation circuit 17. Is output.

  Here, the wiring for transmitting the reset signal RST from the CPU 103 is connected to the direct reset terminal DR of the latch signal output circuit 174 and the direct reset terminals DR0 to DR15 of the Philip flop circuits 210 to 225 included in the random value storage circuit 175. When the signal level of the reset signal RST falls from the high level to the low level, the latch signal output circuit 174 and the random value storage circuit 175 are reset.

  As described above, since the latch signal output circuit 174 is reset when a system reset or a user reset occurs, a random value is output from the latch signal output circuit 174 due to, for example, the influence of noise caused by a decrease in power supply voltage. When the latch signal SL is erroneously output to the storage circuit 175, the random value storage circuit 175 latches and stores the count value C input from the counter 173 to the input terminal D as the random value R at an incorrect timing. And erroneous operation such as reading out the random value R stored in the random value storage circuit 175 by mistake can be prevented.

  Further, since the random value storage circuit 175 is reset when a system reset or a user reset occurs, the random value storage circuit 175 erroneously inputs from the counter 173 to the input terminal D due to the influence of noise, for example. Even when the count value C to be stored is latched and stored as the random number value R, the stored random number value R can be erased, so that the random number value R stored in the random number storage circuit 175 is erroneously read out. Can prevent malfunctions.

  The random number generation circuit 17 does not directly input the start winning signal SS output from the start winning port switch 70 to the latch signal output circuit 174, but once inputs it to the timer circuit 176 to input the start winning signal SS. Time is measured, and when the measured time reaches a preset time (3 ms), the start winning signal SS is input to the latch signal output circuit 174. For this reason, the pachinko gaming machine 1 can prevent the latch signal output circuit 174 from erroneously outputting the latch signal SL to the random value storage circuit 175 due to the influence of noise or the like. Since the timer circuit 176 is set to “3 ms” which is shorter than “4 ms” between the executions of the two timer interrupt processes, the random number value R read out from the random value storage circuit 175 by the CPU 103 is the previous value. It is possible to prevent the same value as the random value R read at the time of winning a prize.

  In addition, when the latch signal SL is input from the latch signal output circuit 174, the random value storage circuit 175 converts the output control signal (high level signal) SC input from the game control microcomputer 100 into a low level signal. By converting to, the output control signal SC is controlled so as not to be received. This prevents the CPU 103 from reading the random value R from the random value storage circuit 175 when the random value R stored in the random value storage circuit 175 is updated. 1 can reliably and stably update the random value R.

  Furthermore, when the output control signal SC is input from the game control microcomputer 100, the random value storage circuit 175 converts the latch signal (high level signal) SL input from the latch signal output circuit 174 into a low level signal. By converting to, the latch signal SL is controlled so as not to be received. Thereby, when the game control microcomputer 100 reads the random value R from the random value storage circuit 175, it is possible to prevent the random value R stored in the random value storage circuit 175 from being updated. Therefore, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above-described embodiment, the start winning port switch 70 generates a random number for the start winning signal SS and the main board 11 based on detecting the winning of a game ball to the ordinary variable winning ball device 6 which is the starting winning port. The random number generation circuit 17 measures the time during which the start winning signal SS is input from the start winning port switch 70 in the timer circuit 176, and the measured time is a predetermined time (for example, 3 ms). ), The start winning signal SS is output to the latch signal output circuit 174.

  However, the present invention is not limited to this, and the start winning opening switch 70 outputs the start winning signal SS only to the main board 11, and the CPU 103 mounted on the main board 11 is set a predetermined number of times (for example, 2 ) Timer interruption process is being executed (for example, for 4 ms), the start winning signal SN for latch is latched based on the fact that the start winning signal SS is continuously input from the start winning opening switch 70. You may send to the output circuit 174.

  A gaming machine according to such a modification will be described below with reference to the drawings. FIG. 19 is a block diagram showing a circuit configuration and the like in the main board 11 according to this modification, and FIG. 20 is a block diagram showing a configuration of a random number generation circuit 27 according to this modification. In addition, in the random number generation circuit 27, about the same structure as the random number generation circuit 17 which concerns on the said embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted as needed.

  As shown in FIG. 20, the random number generation circuit 27 includes a reference clock signal output circuit 171, a clock signal generation circuit 172, a counter 173, a latch signal output circuit 174, and a random value storage circuit 175. Yes.

  The input terminal D of the latch signal output circuit 174 is connected to the I / O port 104, and the clock terminal CK is connected to the reverse phase output terminal Q (bar) of the clock signal generation circuit 172. The output terminal Q of the latch signal output circuit 174 is connected to the random value storage circuit 175. Further, the direct reset terminal DR of the latch signal output circuit 174 is connected to the CPU 103 built in the game control microcomputer 100 and receives the supply of the reset signal RST. The latch signal output circuit 174 generates and outputs a latch signal SL by synchronizing the latch start winning signal SN input from the input terminal D with the rising edge of the latch clock signal S2 input from the clock terminal CK. Output from terminal Q. The latch signal output circuit 174 is cleared asynchronously to the input from the clock terminal CK when the reset signal RST directly input from the reset terminal DR falls from the high level to the low level.

  FIG. 21 is a timing chart for explaining the operation of the random number generation circuit 27.

  As shown in FIG. 21A, the reference clock signal output circuit 171 receives a reference clock signal S0 having a frequency of 20 MHz that rises from a low level to a high level at timings T10, T11, T12,. Output to CK.

  The clock signal generation circuit 172 responds to the rising edge of the reference clock signal S0 input from the clock terminal CK with the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D. Latch and output from the positive phase output terminal Q. As a result, as shown in FIG. 21B, the positive phase output terminal Q outputs a counting clock signal S1 having a frequency of 10 MHz that rises from a low level to a high level at timings T10, T12, T14,. The

  The clock signal generation circuit 172 inverts the count clock signal S1 output from the normal phase output terminal Q and outputs the inverted signal from the reverse phase output terminal Q (bar). As a result, from the negative phase output terminal Q (bar), as shown in FIG. 21D, at a timing T11, T13, T15,..., A latch clock signal S2 having a frequency of 10 MHz rising from the low level to the high level. Is output.

  Then, as shown in FIG. 21C, the counter 173 updates the count value C in response to the rising edge of the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172. Output. On the other hand, the latch signal output circuit 174 receives the latch start winning signal SN shown in FIG. 21E input from the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. The latch signal SL shown in FIG. 21 (F) is generated and output from the output terminal Q in synchronization with the rising edge of the latch clock signal S2 input.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. Then, by latching and storing as a random value R, the stored random value R is updated as shown in FIG.

  In this way, the random number generation circuit 27 can reliably make the update timing of the count value C different from the latch timing of the count value C.

  In addition, the reset signal RST from the CPU 103 is supplied not only to the latch signal output circuit 174 but also to the random value storage circuit 175. When the reset control signal RC falls from the high level to the low level, the random value The storage circuit 175 is reset, and the random value R stored in the random value storage circuit 175 is erased.

  In this modification, the flag memory 112 shown in FIG. 6 is provided with a random value read flag in addition to the above-described flags. This random number read flag is set to an on state when the latch start winning signal SN is sent to the latch signal output circuit 174, and is cleared when the random number value R is read from the random value storage circuit 175 to be in an off state. Become.

  FIG. 22 is a flowchart showing the special symbol process executed in step S16 in this modification. When the special symbol process is started, the CPU 103 first determines whether or not the random number read flag provided in the flag memory 112 is on (step S201).

  When the random number read flag is off (step S201; No), the timer value stored in the start winning port switch timer memory 113 is checked to determine whether or not the game ball has won the normal variable winning ball device 6. Thus, the determination is made (step S202). In step S202, the CPU 103 loads the timer value stored in the start winning a prize opening switch timer memory 113, and compares the loaded timer value with a predetermined switch-on determination value (for example, “2”). Here, the switch-on determination value is determined in advance corresponding to the number of times the timer interrupt process is executed (for example, “2”). Thereby, the CPU 103 determines whether or not the start winning signal SS is continuously input from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, for 4 ms). Can be determined.

  Based on the comparison result, the CPU 103 determines whether or not the timer value is equal to or greater than the switch-on determination value “2”. If the timer value is greater than or equal to the switch-on determination value “2”, it is determined that the game ball has won (step S202; Yes), and a winning process is executed (step S203). clear. On the other hand, if the timer value is less than the switch-on determination value “2”, it is determined that the game ball has not won (step S202; No), and the winning process is skipped.

  FIG. 23 is a flowchart showing the winning process in step S203. In this winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the special figure reservation memory 110 is the maximum value “4” (step S221). Here, in the special figure reservation memory 110, when the random number value R corresponding to the start winning storage number “4” is stored, it is determined that the starting winning storage number is “4”.

  When the start winning memory number is “4” (step S221; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memorized number is less than “4” (step S221; No), the latch start winning signal SN is sent to the latch signal output circuit 174 (step S222), and the random number read flag is set to the ON state. (Step S223).

  When the random value read flag is on in step S201 (step S201; Yes), random number read processing is executed (step S204).

  FIG. 24 is a flowchart showing the random number value reading process in step S204. In this random value reading process, the CPU 103 first sends an output control signal SC to the random value storage circuit 175 to control the random value storage circuit 175 to a readable (enable) state (step S231). Subsequently, the CPU 103 reads the random value R from the random value storage circuit 175 (step S232), stores the read random value R in, for example, a predetermined buffer area provided in the RAM 102 (step S233), and then performs random processing. The transmission of the output control signal SC to the numerical value storage circuit 175 is stopped, and the random number value storage circuit 175 is controlled to be unreadable (disabled) (step S234).

  Then, the CPU 103 adds “1” to the starting winning memory number (step S235), and sets the random number value R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory 110 (step S236). Thereafter, the CPU 103 clears the random number read flag and turns it off (step S237).

  As described above, according to this modification, the clock signal generation circuit 172 receives the latch clock signal S2 fed back from the negative phase output terminal Q (bar) to the input terminal D from the clock terminal CK. The count clock signal S1 is generated and latched in response to the rising edge of the reference clock signal S0 to be output from the positive phase output terminal Q. The clock signal generation circuit 172 inverts the generated count clock signal S1 and outputs the latch clock signal S2 from the reverse phase output terminal Q (bar).

  The counter 173 sequentially updates the count value C at timings T10, T12, T14,... At which the counting clock signal S1 input from the positive phase output terminal Q of the clock signal generation circuit 172 rises from the low level to the high level. Go.

  Then, when a game ball wins the normal variable winning ball apparatus 6 which is a starting winning port, the starting winning port switch 70 sends a starting winning signal SS only to the main board 11. The CPU 103 of the main board 11 continuously inputs the start winning signal SS from the start winning port switch 70 while the timer interruption process is executed a predetermined number of times (for example, twice) (for example, 4 ms). Based on this, it is determined that the game ball has won the normal variable winning ball apparatus 6, and a latch start winning signal SN is sent to the random number generation circuit 27.

  The latch start winning signal SN sent to the random number generation circuit 27 is inputted to the input terminal D of the latch signal output circuit 174. The latch signal output circuit 174 receives the latch start winning signal SN input to the input terminal D from the reverse phase output terminal Q (bar) of the clock signal generation circuit 172 to the clock terminal CK. At the timings T11, T13, T15,... At which S2 rises from the low level to the high level, the latch signal SL is output from the output terminal Q.

  The random value storage circuit 175 responds to the count value C input from the counter 173 to the input terminal D in response to the rising edge of the latch signal SL input from the output terminal Q of the latch signal output circuit 174 to the clock terminal CK. And latched and stored as a random value R.

  Thereafter, in the first timer interruption process, the CPU 103 reads the random value R from the random value storage circuit 175, and whether or not the read random value R matches a predetermined determination value “2001 to 2184” or the like. It is determined whether or not the display result of the special figure game by the variable display device 4 is set to the big hit gaming state.

  In this way, the random number generation circuit 27 can reliably vary the update timing of the count value C by the counter 173 and the output timing (latch timing) of the latch signal SL by the latch signal output circuit 174. Further, since the random number generation circuit 27 performs the updating of the count value C and the output of the latch signal SL without inverting the reference clock signal S0, the update is performed even when the falling edge of the reference clock signal S0 is gradual. Timing and latch timing can be stabilized. As a result, the pachinko gaming machine 1 can reliably and stably acquire the random value R.

  In addition, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 outputs the latch start winning signal SN to the latch signal output circuit 174 of the random number generation circuit 27. Therefore, the pachinko gaming machine 1 It is not necessary to provide a path for supplying the start winning signal SS from the start winning port switch 70 to the random number generating circuit 27, and the hardware configuration can be simplified.

  In addition, the wiring for transmitting the reset signal RST from the CPU 103 is connected to the direct reset terminal DR of the latch signal output circuit 174, and the reset signal RST from the CPU 103 is also input to the random value storage circuit 175. When the signal level of the reset signal RST falls from the high level to the low level, the latch signal output circuit 174 and the random value storage circuit 175 are reset. As a result, the latch signal output circuit 174 can be reset when a system reset or a user reset occurs. For example, the latch signal output circuit 174 may change the random value storage circuit due to the influence of noise caused by a decrease in the power supply voltage. The latch signal SL is erroneously output to 175 to prevent the random value storage circuit 175 from latching and storing the count value C input from the counter 173 to the input terminal D as the random value R at an incorrect timing. Thus, it is possible to prevent malfunction such as the random value R stored in the random value storage circuit 175 being erroneously read. In addition, since the random value storage circuit 175 can be reset when a system reset or a user reset occurs, the random value storage circuit 175 may be erroneously deleted from the counter 173 due to, for example, the influence of noise caused by a decrease in power supply voltage. Even when the count value C input to the input terminal D is latched and stored as the random number value R, the stored random number value R can be erased, so that it is erroneously stored in the random value storage circuit 175. It is possible to prevent malfunction such as reading of the random value R.

  Further, the CPU 103 determines that the game ball has won the normal variable winning ball device 6 based on the continuous input of the start winning signal SS while the two timer interruption processes are being executed. Therefore, the pachinko gaming machine 1 can prevent the latch start winning signal SN from being erroneously output to the random number generation circuit 27 due to the influence of noise or the like.

  In addition, when the CPU 103 determines that the game ball has won the normal variable winning ball apparatus 6, the CPU 103 reads the random value R from the random value storage circuit 175 in the first timer interruption process. It is possible to prevent the read random value R from being the same as the previously read random value R.

  In the above embodiment, the positive phase output terminal Q of the clock signal generation circuit 172 is connected to the input terminal of the counter 173, and the negative phase output terminal Q (bar) is connected to the input terminal D of the latch signal output circuit 174. Was connected. However, the present invention is not limited to this, and the positive phase output terminal Q of the clock signal generation circuit 172 is the input terminal Q of the latch signal output circuit 174, and the negative phase output terminal Q (bar) is the input terminal of the counter 173. , Each may be connected.

  In the above embodiment, the CPU 103 periodically determines whether any reset has occurred among system reset and user reset by executing the reset process in step S11 of the game control interrupt process shown in FIG. In the above description, the reset signal RST is transmitted when a reset occurs. However, the present invention is not limited to this, and when the CPU 103 detects that the reset control signal RC input from the reset control circuit 105 has fallen from a high level to a low level, Alternatively, a reset process as shown in FIG. 15 may be executed by executing a preset interrupt process separately. As a result, when a reset such as a system reset or a user reset occurs, the reset signal RST can be generated and sent asynchronously with the timing at which the game control interrupt process is executed. Immediately, the stored contents of the latch signal output circuit 174 and the random value storage circuit 175 can be erased.

  Alternatively, in the reset process executed in step S11 of the game control interrupt process shown in FIG. 14, it is possible to determine whether a user reset has occurred and to send the reset signal RST, while reducing the VSL power supply voltage. When the occurrence of a system reset is detected, a preset interrupt process is executed separately from the game control interrupt process, thereby generating a reset signal RST asynchronously with the timing at which the game control interrupt process is executed. It may be generated and sent out. Here, the priority of the interrupt process executed when the occurrence of the system reset due to the decrease in the VSL power supply voltage is detected may be set to be higher than the priority of the game control interrupt process. For example, in the CPU 103, a wiring that transmits a reset control signal RC that notifies the occurrence of a system reset that is output from the reset control circuit 105 via the system reset extension circuit 311 is connected to the non-maskable interrupt terminal (NMI terminal). In response to the reset control signal RC, the CPU 103 executes non-maskable interrupt processing (NMI processing). On the other hand, the CPU 103 may execute the game control interrupt process as a maskable interrupt process (INT process). As a result, when the operation of the pachinko gaming machine 1 becomes unstable due to a decrease in the VSL power supply voltage or the like, the game control interrupt process executed by the CPU 103 to manage the operation of each electrical component is prioritized. The latch signal output circuit 174 and the random value storage circuit 175 can be reset, and the random value R stored in the random value storage circuit 175 can be reliably prevented from being read.

  In the above embodiment, the reset signal RST generated by the CPU 103 is supplied to both the latch signal output circuit 174 and the random value storage circuit 175 provided in the random number generation circuit 17, but the present invention is not limited to this. The reset signal RST from the CPU 103 may be supplied to only one of the latch signal output circuit 174 and the random value storage circuit 175 included in the random number generation circuit 17 to perform reset. In addition to the latch signal output circuit 174 and the random value storage circuit 175, a reset signal RST may be supplied to the counter 173 so that the count operation of the count value C in the counter 173 can be reset. As a result, the count value C of the counter 173 is erased when a system reset or a user reset occurs. For example, the count value C erroneously counted by the counter 173 due to noise or the like is input to the random number value storage circuit 175. It is possible to prevent the random number value R that is input to D and latched and stored as the random number value R, and to prevent erroneous operations such as reading the random number value R stored in the random number value storage circuit 175 by mistake.

  Further, after the CPU 103 has sent the reset signal RST in step S53 shown in FIG. 15, it does not end the reset process and return to the game control interrupt process, but executes a predetermined loop process to enter the loop state. You may make it enter. In this case, when the occurrence of the reset is detected by the CPU 103, the reset state is entered in the loop state. That is, the operation of the CPU 103 is completely stopped. As a result, the CPU 103 sends out the reset signal RST and outputs the latch signal output circuit 174 and the normal signal until the normal operation cannot be ensured due to, for example, a decrease in the VSL power supply voltage (that is, a state in which the operation cannot be managed occurs). Since the resetting of the random value storage circuit 175 can be finished, and thereafter, the process enters the reset state without executing the process for managing the operation of each electrical component (the process of steps S12 to S21 shown in FIG. 14). It is possible to prevent abnormal operation based on indefinite data.

  In the above embodiment, the power supply voltage monitoring circuit 18 is described as being installed on the power supply board 10, but the present invention is not limited to this, and the main board 11, the display control board 12, the sound control board 13, the lamp control board 14, Each control board such as the payout control board 15 may be installed independently. Further, the reset control circuit 105 is not limited to the one built in the game control microcomputer 100, but a reset control signal is sent from the outside of the game control microcomputer 100 to the CPU 103 built in the game control microcomputer 100. It may output RC.

  The wiring for transmitting the reset signal RST from the CPU 103 to the latch signal output circuit 174 and the random value storage circuit 175 branches from the same input terminal in the random number generation circuit 17 to the latch signal output circuit 174 and the random value storage circuit 175. The reset signal RST may be transmitted between the CPU 103 and the random number generation circuit 17 using a common wiring. Alternatively, separate input terminals in the random number generation circuit 17 are installed corresponding to either the latch signal output circuit 174 or the random value storage circuit 175, and separate wiring is used between the CPU 103 and the random number generation circuit 17. The reset signal RST may be transmitted.

  Further, in the above embodiment, the counter 173 is an up counter, but the present invention is not limited to this, and may be a down counter. Further, the numerical value updating means is not limited to the counter 173, and may be a pseudo random number generation circuit. In addition, the connection between the output terminal of the bit data C0 to C15 of the count value C of the counter 173 and the input terminal of the bit data C0 to C15 of the count value C of the random number storage circuit 175 may be changed. Then, the randomness of the count value C input to the random value storage circuit 175 can be improved.

  In the above embodiment, the random value storage circuit 175 uses the logic circuits such as the AND circuits 201 and 203 and the OR circuits 230 to 245 to control the reception of the latch signal SL and the output control signal SC and output the random value R. Enable / disable control such as control was performed. However, the present invention is not limited to this, and the random value storage circuit 175 is provided with a switching element such as an FET (Field Effect Transistor) between the I / O port 104 and the latch signal output circuit 174, and the latch signal SL. In response to the input of the output control signal SC and the path to the I / O port 104 and the latch signal output circuit 174, the latch signal SL and the enable / disable control of the output control signal SC are performed. Also good.

  Further, in the above embodiment, the timer circuit 176 is activated in response to the input of the high level signal, and the reference clock signal from the reference clock signal output circuit 171 while the input is at the high level. In response to the input of S0, the timer value is counted up or down, and when the timer value reaches a value corresponding to a predetermined time, it is determined that the input signal is a high level signal. The signal is output to the latch signal output circuit 174. However, the present invention is not limited to this, and the timer circuit 176 measures the time during which the start winning signal SS is input from the start winning port switch 70, and starts when the measured time reaches a predetermined time. Any signal may be used as long as it outputs the winning signal SS to the latch signal output circuit 174.

  In the above embodiment, the timer circuit 176 measures the signal input time using the reference clock signal S0 sequentially input from the reference clock signal output circuit 171, but the present invention is not limited to this. Instead, the timer circuit 176 may use a clock signal obtained by dividing the reference clock signal S0 or a clock signal output from a clock signal output circuit different from the reference clock signal output circuit 171. In the above embodiment, the timer circuit 176 is set to 3 ms as the predetermined time. However, the present invention is not limited to this, and from the 4 ms that is the execution time of the two timer interrupt processes. Can be arbitrarily set as long as the time is short.

  Further, in the above embodiment, the CPU 103 executes the winning process based on the continuous input of the start winning signal SS while the timer interruption process is executed twice. However, the present invention is not limited to this, and the number of executions of the above-described timer interrupt process is arbitrary. For example, the CPU 103 performs the start winning signal SS while the three timer interrupt processes are being executed. The winning process may be executed based on the fact that is continuously input. In this case, the timer circuit 176 may be set to a time shorter than 6 ms, which is the execution time of the three timer interruption processes.

  Further, in the above-described embodiment, the gaming machine can perform the variable display start condition (for example, the previous variable display and the variable display device 4 after the variable display execution condition (for example, winning the normal variable winning ball device 6)). A variable display device (for example, the variable display device 4) that variably displays a plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the end of the big hit gaming state is established, This is a pachinko gaming machine that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the result is a predetermined specific display result.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, a big prize opening) from a disadvantageous state (for example, a closed state) to a player (for example, an open state). Possible pachinko machines may be used.

  Furthermore, the gaming machine of the present invention can start a game by setting the number of bets for one game shown in FIG. 25, and the display result of a variable display device (for example, the variable display device 1002) is derived. It may be a slot machine (for example, slot machine 1000) in which one game is completed by being displayed and a predetermined winning can be generated according to the display result of the variable display device. The slot machine 1000 shown in FIG. 25 uses a game control means (for example, main board) or random number generation means as a start winning signal output means according to the present invention based on a start lever 1011 operated by a player. A start switch (not shown) for outputting to (for example, a random number generation circuit) is provided. Note that the liquid crystal display 1001 shown in FIG. 25 functions as a rendering means.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. That is, any form of game machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  1, 2, and 25, the block configurations shown in FIGS. 4, 6, 8, 10, 19, and 20, and the timing charts shown in FIGS. 11, 12, and 21. The configuration shown in FIGS. 3, 5 and 9, the table shown in FIG. 7, and the flowchart shown in FIGS. 13 to 18 and FIGS. 22 to 24 are arbitrarily set within the scope of the invention. Changes and modifications are possible.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of a winning ball, but encloses a game ball and gives a score in response to detection of the winning ball It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a circuit diagram which shows one structural example of the power supply voltage monitoring circuit with which a power supply board is provided. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a circuit diagram which shows one structural example of the reset control circuit built in the microcomputer for game control. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows the structural example of the table for jackpot determination. It is a block diagram which shows the structural example of a random number generation circuit. It is a circuit diagram which shows the structural example of a random value storage circuit. It is a figure for demonstrating the connection of the output terminal of an OR circuit of a random value memory circuit, and an I / O port. 3 is a timing chart for explaining the operation of a random value storage circuit. 3 is a timing chart for explaining the operation of a random number generation circuit. It is a flowchart which shows a game control main process. It is a flowchart which shows a game control interruption process. It is a flowchart which shows a reset process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a block diagram which shows the modification of circuit configurations etc. in the main board | substrate shown in FIG. It is a block diagram which shows the modification of a structure of the random number generation circuit shown in FIG. 21 is a timing chart for explaining the operation of the random number generation circuit shown in FIG. 20. It is a flowchart which shows the modification of the special symbol process process shown in FIG. It is a flowchart which shows the detail of the winning process in FIG. It is a flowchart which shows the detail of the random value reading process in FIG. It is a front view of a slot machine.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machines
4 ... Variable display device
6 ... Ordinary variable winning ball device
7 ... Special variable winning ball device 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board 17, 27 ... Random number generation circuit
18 ... Power supply voltage monitoring circuit 21, 22 ... Solenoid
40 ... Normal symbol display
70 ... Start prize opening switch 100 ... Microcomputer for game control 101 ... ROM
102 ... RAM
103 ... CPU
104 ... I / O port 105 ... Reset control circuit 107 ... Switch circuit 108 ... Solenoid circuit 110 ... Special figure hold memory 111 ... Table game for big hit judgment 112 ... Flag memory 113 ... Start winning prize switch timer memory 121 ... Normal big hit judgment Table 122 ... Table for determining jackpot upon probability change 171 ... Reference clock signal output circuit 172 ... Clock signal generation circuit 173 ... Counter 174 ... Latch signal output circuit 175 ... Random value storage circuit 176 ... Timer circuits 201, 203, 313, 314 ... AND circuits 202, 204 ... NOT circuits 210-225 ... Philip flop circuits 230-245 ... OR circuit 301 ... Power supply monitoring IC
311 ... System reset extension circuit 312 ... User reset extension circuit 1000 ... Slot machine 1001 ... Liquid crystal display 1002 ... Variable display device 1011 ... Start lever

Claims (10)

Based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, a variable display device that variably displays a plurality of types of identification information, each of which can be identified, is provided, and the display result of the identification information is specified. A gaming machine that is in a specific gaming state that is advantageous to the player when the result is achieved,
Game control means for controlling the progress of the game;
Random number generating means for generating a random number;
Voltage monitoring means for monitoring a power supply voltage supplied to the gaming machine;
With
The random number generating means includes
Reference clock signal output means for outputting a reference clock signal of a predetermined period;
A clock signal generating means for generating a plurality of signals having the same period and different phases based on the reference clock signal;
Including
The clock signal generation means includes
A clock terminal to which the reference clock signal is input from the reference clock signal output means;
An input terminal to which the first signal is input;
A first output terminal that outputs a signal in which a change state of the first signal is synchronized with a timing of changing the reference clock signal input from the clock terminal for each predetermined period;
A second output terminal that outputs a signal having the same period and a different phase as the signal output from the first output terminal;
Including
The clock signal generation means includes
By connecting the second output terminal and the input terminal, the first clock signal output from the first output terminal and the first clock signal output from the second output terminal are provided. And a second clock signal having the same period and different phases,
The random number generating means includes
Numerical data updating means for updating numerical data at a first timing when the first clock signal generated by the clock signal generating means changes in the predetermined manner;
Latch signal output means for outputting a latch signal at a second timing at which the second clock signal generated by the clock signal generating means changes in the predetermined manner;
Random value storage means for storing numerical data updated by the numerical data update means as random values in response to a latch signal input from the latch signal output means;
Including
The voltage monitoring means includes
System reset signal output means for outputting a system reset signal to the game control means when it is detected that the power supply voltage has become a predetermined value or less,
The game control means includes
Based on the fact that the execution condition is satisfied, the random number value is read from the random value storage means, and it is determined whether or not the read random number value matches predetermined determination value data. Display result determining means for determining whether or not the display result is a specific display result;
In response to a system reset signal input from the system reset signal output means, a latch output reset means for resetting the latch signal output means by outputting a latch output reset signal to the latch signal output means;
including,
A gaming machine characterized by that. The game control means includes
A game control microcomputer for executing a game control process;
Including abnormality processing detection means for detecting that the gaming control microcomputer has performed predetermined abnormality processing;
The latch output reset means includes
At the time of abnormality processing for resetting the latch signal output means by outputting a latch output reset signal to the random number storage means when the abnormality processing detection means detects that the predetermined abnormality processing has been performed. Including latch output reset means,
The gaming machine according to claim 1. A start signal output means for outputting a start signal to the random number generating means based on the execution condition being satisfied;
The latch signal output means outputs a start signal input from the start signal output means as a latch signal at a second timing when the second clock signal generated by the clock signal generation means changes in the predetermined manner. To
The gaming machine according to claim 1 or 2, characterized in that. The random number generating means measures a time during which a start signal is input from the start signal output means, and outputs a start signal to the latch signal output means when the measured time reaches a predetermined time. Including means,
The gaming machine according to claim 3. The start signal output means outputs a start signal to the game control means,
The game control means includes a timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal input periodically.
The display result determining means is based on the fact that a start signal is continuously input from the start signal output means while the timer interrupt process executing means is executing a predetermined number of timer interrupt processes. Read the random value from the random value storage means,
The timer means includes
Setting means for setting, as the predetermined time, a time shorter than a time for which a predetermined number of timer interrupt processes are executed by the timer interrupt process executing means;
When the measured time reaches a time set as a predetermined time by the setting means, the start signal is output to the latch signal output means.
The gaming machine according to claim 4, wherein: A start signal output means for outputting a start signal to the game control means based on the execution condition being satisfied;
The game control means includes
A latch start signal output means for generating a latch start signal based on the input of the start signal from the start signal output means and outputting the latch start signal to the random number generating means;
The latch signal output means uses a latch start signal input from the latch start signal output means at a second timing when the second clock signal generated by the clock signal generation means changes in the predetermined manner. Output as a latch signal,
The gaming machine according to claim 1 or 2, characterized in that. The game control means includes
A timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal periodically input;
Start signal determination means for determining whether a start signal is continuously input from the start signal output means while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes;
Including
The latch start signal output means outputs a latch start signal to the random number generation means when it is determined by the start signal determination means that the start signal is continuously input.
The display result determination means reads the random value from the random value storage means in a timer interruption process after outputting the latch start signal by the latch start signal output means.
The gaming machine according to claim 6. The game control means outputs an output control signal to the random value storage means so that the random number value storage means can be read before the display result determination means reads the random value from the random value storage means. Read control means for stopping the output of the output control signal to the random value storage means and controlling the random value storage means to an unreadable state after the display result determining means reads the random value from the random value storage means including,
The gaming machine according to any one of claims 1 to 7, characterized in that: The random value storage means includes an output control signal reception control means for controlling the output control signal output from the read control means to be in an unreceivable state when a latch signal is input from the latch signal output means. ,
The gaming machine according to claim 8, wherein: The random value storage means includes a latch signal reception control means for controlling the latch signal output from the latch signal output means in an unreceivable state when an output control signal is input from the read control means.
The gaming machine according to claim 8 or 9, characterized in that.

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