JP2006020812A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the winning with a simple structure by arranging one random number circuit for outputting the random numbers for a plurality of variable display devices. <P>SOLUTION: The game balls winning the prize winning slots 61A and 62A flow down to a common passage-way 1103 from passages 1101 and 1102. When the prize ball detection signals SDA and SDB are supplied from prize winning slot switches 70A and 70B, the CPU103 judges which of the prize winning slot switches 70A and 70B the signals come from and the information on the prize winning slot is stored corresponding to the order thereof. A starter prize winning detector 1111 disposed in the common passage-way 1103 outputs the starter prize winning detection signal SSN when detecting the prize balls. A latch circuit latches the counts of a counter, engaged in the periodic updating of the counts, as the jackpot random number in response to the starter prize winning signal SSN. The CPU103 inputs the jackpot random number from the latch circuit and the special pattern game is processed by judging which of the prize winning slots 61A and 62A is won based on the information on the prize winning slot. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more specifically, a first variable display means for variably displaying a plurality of types of identification information that can be identified based on the first start condition being satisfied, A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the establishment of a second start condition different from the first start condition, and the identification information by the first variable display means When the display result of the variable display is a combination of predetermined specific identification information, or when the display result of the variable display of the identification information by the second variable display means is the combination of the specific identification information The present invention also relates to a gaming machine that controls a specific gaming state that is advantageous to the player.

  In gaming machines such as pachinko machines, variable display is performed by displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (LCD: Liquid Crystal Display) or by scrolling and displaying it. There are a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on the display result.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In the game, the “hit” is defined as a case where the stop symbol form when the display is completely stopped is a predetermined specific display form. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won very easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

  The selection and determination of the display pattern variable display mode is based on the detection of the game ball passing through the start winning opening and the random number value (mainly including the big hit random number and other random numbers for determining the figure stop symbol). Based on the extracted random number value, it is determined by determining whether or not to enter the big hit gaming state, the variation mode, and the like. As an example of a random number circuit for enabling such processing, Patent Document 1 discloses a configuration in which a counter is updated by a clock signal and a count value is acquired based on a predetermined timing signal. .

  Also, some pachinko gaming machines have a plurality of start winning openings and a variable display unit corresponding to each starting winning opening, and one clock count circuit and two pieces are provided so as to correspond to this type of gaming machine. Patent Document 2 discloses a circuit including a count value storage circuit and two latch signal generation circuits. Further, in a gaming machine having a plurality of start winning openings and a variable display portion corresponding to each start winning opening, in order to prevent a situation where the player's joyfulness is intensified, it is possible that a plurality of variable display portions are simultaneously hit. To prevent the variable display on one variable display unit from winning, or when one variable winning slot is in a specific game state, until the symbol variation of the other variable display device starts Patent Document 3 discloses a method for delaying the above time.

In addition, it is determined that the variable display on one of the variable display devices is winning, or it is determined that one variable winning opening is in a specific gaming state and the variable display on the other variable display device is winning. In such a case, Patent Document 4 discloses that the start of the variable display is delayed until the specific gaming state of one of the variable winning awards ends.
Further, Patent Document 5 discloses that a winning ball of two thinking winning ports is guided to a common passage for discharging, and a winning is detected at this joining position.
JP 7-124296 A JP 2003-190483 A JP 2001-62080 A JP 2001-62081 A JP 2002-35263 A

  In the gaming devices described in Patent Documents 1 to 5, a random number value is latched in order to determine a variable display result in a special figure game on a plurality of variable display devices. For this purpose, a random number for each variable display device is used. Therefore, a latch circuit for latching is required. The hardware configuration is increased by the arrangement of a plurality of latch circuits, and the substrate is forced to be enlarged.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine that can acquire random numbers for a plurality of variable display areas with a small amount of hardware.

In order to achieve the above object, a gaming machine according to claim 1 of the present application,
A first start condition is established when a game medium (for example, a game ball) passes through a first start area (for example, the first ordinary variable winning ball device 61) provided in the game area (for example, the game board 2). The first start condition (for example, the end of the special-purpose game on the previous first variable display device 41) is established after the winning of the game ball to the first starting winning ball device 61 is established (for example, the first variable display device 41 is terminated). Based on this, a first variable display means (for example, the first variable display device 61) for variably displaying a plurality of types of identification information (for example, special symbols) each identifiable, and a game area (game board 2) ) Provided in a second starting area (for example, the second ordinary variable winning ball apparatus 62), the second starting condition (for example, the second starting condition different from the first starting condition by passing the game medium). Winning of a game ball to the normal variable winning ball device 62) is established. A plurality of types of identification information (for example, special symbols) that can be identified based on the fact that the second start condition (for example, the end of the special figure game on the previous second variable display device 42) has been established. ) Variable display means (for example, the second variable display device 62), and a display result of variable display of the identification information by the first variable display means is determined in advance. When a combination of identification information is obtained (for example, the same symbol's gaze), or a display result of variable display of identification information by the second variable display means is a combination of the specific identification information (for example, the same symbol) A gaming machine (for example, pachinko gaming machine 1) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when
A common flow path (for example, game medium flow path 1103) through which the game medium that has passed through the first start area and the game medium that has passed through the second start area pass in common;
A first game medium path (for example, a game medium flow path 1101) for guiding the game medium that has passed through the first start area to the common flow path;
A second game medium path (e.g., game medium flow path 1102) that guides the game medium that has passed through the second starting area to the common flow path;
Start detection means (for example, a start winning detector 1111) that is disposed in the common flow path and detects a game medium passing through the common flow path and outputs a start detection signal (for example, a start winning detection signal SSN);
A game medium detecting means that is arranged in at least one of the first game medium path and the second game medium path and detects a game medium and outputs a game medium detection signal (for example, a winning ball detection signal SDA, SDB). (For example, the first and second start winning opening switches 70A and 70B),
Numerical data update means (for example, numerical data update circuit 1211) that updates and outputs numerical data within a predetermined update range (for example, a range of 0 to 65535) at a predetermined cycle;
Storage means (for example, a latch signal) that stores numerical data output from the numerical data update means as a random value when the start detection signal is output from the start detection means (for example, start winning detector 1111) Generation circuit 1204 and latch circuit 1205),
Game control means (for example, CPU 103, game control interrupt processing) for controlling the progress of the game using the variable display of the first and second variable display means based on the numerical data output from the numerical data update means; With
The game control means includes
Reading means (for example, CPU 103, step S203) for reading the numerical data stored in the storage means when the start detection signal is output from the start detection means;
When the start detection signal is output from the start detection means, based on the game medium detection signal, it is determined whether the first start condition or the second start condition is satisfied. Discrimination means (for example, CPU 103, winning order memory 1221, step S102);
When the starting condition satisfaction determining means determines that the first start condition is satisfied, the random value stored in the numerical data reading means is registered in predetermined determination value data (for example, the big hit determination tables 120 and 121). To determine whether the display result in the variable display by the first variable display means is the specific display result, and the start condition establishment determining means is When it is determined that the second start condition is satisfied, whether the random number value stored in the storage means matches predetermined determination value data (for example, determination values registered in the jackpot determination tables 120 and 121) By determining whether or not the display result in the variable display by the second variable display means is determined as the specific display result (for example, CPU 103, And step S226),
When the first start condition is satisfied, variable display of the identification information in the first variable display means is started, and a display result based on the determination result of the display result determination means is derived and displayed, Display control means for starting the variable display of the identification information in the second variable display means and deriving and displaying the display result based on the determination result of the display result determination means when the second start condition is satisfied (For example, the CPU 103, the display control board 12, the processing of FIGS. 26 to 30 and FIGS. 32 to 39),
It is characterized by providing.

In order to achieve the above object, in the gaming machine according to claim 2 of the present application,
The numerical data updating means includes
A reference clock signal output means (for example, a reference clock signal generation circuit 1201) for outputting a reference clock signal (for example, a reference clock signal S0) having a reference period;
A clock terminal (for example, clock terminal Clk) to which the reference clock signal is input from the reference clock signal output means, an input terminal (for example, data terminal D) to which a first signal is input, and the first signal A first output terminal (for example, a Q output terminal) that outputs a signal that is synchronized with a timing at which the change state of the reference clock signal that is input from the clock terminal is changed at every predetermined period. A second output terminal (for example, a Q bar terminal) that outputs a signal having the same period and a different phase from the signal output from the output terminal, and means for connecting the second output terminal and the input terminal; And a first clock signal (for example, signal S1) output from the first output terminal and a second clock output from the second output terminal, and have the same period and a different phase from the first clock signal. Second Clock signal (e.g., signal S2) and a clock signal generating means for generating (e.g., the count clock signal generation circuit 1202),
A counter (e.g., counter 1203) that updates numerical data at a first timing (e.g., rising edge timing) at which the first clock signal generated by the clock signal generation unit changes in a predetermined manner;
Including
The storage means
The start detection signal (for example, the start winning detection signal SSN) is output as a latch signal in synchronization with the second timing at which the second clock signal generated by the clock signal generation means changes in the predetermined manner. Latch signal output means (for example, latch signal generation circuit 1204);
A latch circuit (for example, a latch circuit 1205) that latches output data of the numerical data updating means in response to an output signal of the latch signal output means;
including.

In order to achieve the above object, in the gaming machine according to claim 3 of the present application,
The game control means includes
Before the numerical data reading means reads a random number value from the storage means, it outputs an output control signal (for example, a read control signal SRC) to the storage means (for example, the latch circuit 1205), and the storage means can be read. After the numerical data reading means reads the random value from the storage means, the output of the output control signal (for example, the read control signal SRC) to the storage means is stopped and the storage means cannot be read. It is further characterized by further comprising a read control means (for example, CPU 103) for controlling the above.

In order to achieve the above object, in the gaming machine according to claim 4 of the present application,
The storage means (eg, latch circuit 1205) is output from the read control means when a latch signal (eg, latch signal SL) is input from the latch signal output means (eg, latch signal generation circuit 1204). Output control signal reception control means (for example, logic circuits 1301 to 1304) for controlling the output control signal (for example, read control signal SRC) to be incapable of receiving.

In order to achieve the above object, in the gaming machine according to claim 5 of the present application,
When the output control signal (for example, the read control signal SRC) is input, the storage unit (for example, the latch circuit 1205) controls the latch signal output from the latch signal output unit to be in an unreceivable state. Latch signal reception control means (for example, logic circuits 1301 to 1304).

In order to achieve the above object, in the gaming machine according to claim 6 of the present application,
The game medium detection means (for example, the CPU 103, steps S101 and S102) is a first game medium detection means (for example, the first game medium detection means (for example, the first game medium flow path 1101)) disposed in the first game medium path (for example, the game medium flow path 1101). A start winning award opening switch 70A) and a second game medium detecting means (for example, a second start winning award opening switch 70B) disposed in a second game medium path (for example, the game medium flow path 1102). .

  The inventions according to claims 1 to 6 of the present application have the following effects.

  According to the invention described in claim 1 of the present application, it is possible to extract random numbers for a plurality of variable display means by using one numerical data updating means and further by using one storage means, and the circuit efficiency is improved. Well, the amount of hardware can be reduced.

  According to the configuration of the second aspect, the timing at which the numerical data is updated and the timing at which the numerical data is latched as a random number have different phases in the same cycle, and the numerical data is stabilized while the numerical data is stable. Can be latched.

  According to the configuration of claim 3, the game control means can make the previous storage means readable only when the display result determining means reads the random value, so that the random number value is acquired. It can be carried out reliably and stably.

  According to the configuration of claim 4, the storage unit can prevent the display result determination unit from reading out the random number value when updating the stored random number value. The random number value can be updated reliably and stably.

  According to the configuration of claim 5, the storage unit prevents the random number value stored in the storage unit from being updated when the display result determination unit reads the random value. Therefore, the random value can be acquired reliably and stably.

  According to the gaming device of the sixth aspect, the start winning detection means is arranged in each of the first game medium path and the second game medium path, and the first winning medium is output based on both of the start winning signals output from them. Since it is determined whether the game medium has passed through either the starting area or the second starting area, the determination can be made reliably.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and a card reader (CR: Pachinko) gaming machine that lends a ball with a prepaid card, or an LCD. It is a gaming machine such as a slot machine installed.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. At approximately the center position of the game area, a first variable display device 41 that variably displays the first special symbol as identifiable identification information and a second special symbol that can be variably displayed. A second variable display device 42 is provided. In addition, below the first variable display device 41 and the second variable display device 42, a third decorative display that can perform variable display of a first decorative design different from the first special design, respectively. A variable display device 43 and a fourth variable display device 44 capable of performing variable display of a second decorative design different from the second special design are provided.

  On the lower side of the third variable display device 43 and the fourth variable display device 44, a first ordinary variable winning ball device (start winning port) 61 and a second ordinary variable winning ball device 62 are arranged, respectively. Has been. Below the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62, a first special variable winning ball device (large winning opening) 71 and a second special variable winning ball device ( A grand prize award) 72 is provided. In addition, a first normal symbol display 51 and a second normal symbol display 52 are provided below the first special variable winning ball device 71 and the second special variable winning ball device 72, respectively. ing.

  The first and second variable display devices 41 and 42 are composed of 7-segment LEDs and the like. In the first variable display device 41, a game ball wins the first ordinary variable winning ball device 61. However, in the second variable display device 42, a variable display game (special game) in which a game ball winning in the second ordinary variable winning ball device 62 becomes a variable display execution condition (starting condition). ), Display symbols that are composed of numbers, characters, and symbols, each functioning as a plurality of types of identification information that can be identified, are variably displayed in a plurality of variable display areas. In this embodiment, three variable display portions are respectively arranged on the first variable display device 41 and the second variable display device 42, and in each variable display portion, left, middle, and right Special symbols shall be variably displayed.

  In a special game played by the first variable display device 41 or the second variable display device 42, after a specific time has elapsed after starting the variable symbol variable display, the special symbol display results are derived in a predetermined order. Display and stop display the finalized symbol (final stop symbol). And when the combination of a fixed symbol becomes a predetermined specific display result (a big hit combination), this pachinko gaming machine 1 becomes a specific gaming state (also called a big hit gaming state). In the big hit gaming state, the first special variable winning ball device 71 and the second special variable winning ball device 72 generate a predetermined number (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls. The game ball that falls on the surface of the game board 2 is received. The opening cycle can be repeated up to a predetermined upper limit number (for example, 16 times).

  In this embodiment, the first left symbol variably displayed as a special symbol on the left variable display portion, the first middle symbol variably displayed as a special symbol on the middle variable display portion, and the special symbol on the right variable display portion 1st right symbol variably displayed, 2nd left symbol variably displayed as a special symbol on the left variable display portion, 2nd middle symbol variably displayed as a special symbol on the middle variable display portion, right variable display portion The second right symbols displayed as special symbols are 9 symbols, and symbols “1” to “9” are assigned to the symbols. For example, in each of the left, middle, and right variable display sections, when variable display of a special symbol is started during a special symbol game, an updated display is performed from a special symbol with a smaller symbol number to a special symbol with a larger symbol number. When the special symbol with “9” is displayed, the special symbol with the symbol number “1” is displayed next.

  In addition, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is a probability variable jackpot symbol. That is, in the special game by the first variable display device 41 or the second variable display device 42, after the variable symbol display is started, the same special symbol is displayed on the left, middle and right variable display units. When it is derived and displayed as a display result and confirmed, the pachinko gaming machine 1 enters a big hit gaming state. Also, in the special game by the first variable display device 41 or the second variable display device 42, after the variable display of the special symbol is started, the same probability variation big hit symbol is displayed on each of the left, middle and right variable display units. Is displayed and confirmed as a display result, the pachinko gaming machine 1 enters the special game state (probability improvement state) following the end of the big hit game state, and thereafter, the display result in the special game is displayed until a predetermined condition is satisfied. The probability of a big hit combination is improved. In the probability improvement state, the opening time of the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 is longer than that in the normal gaming state, and the number of times of opening is higher than that in the normal gaming state. It becomes an advantageous state for a player different from the big hit gaming state, such as increasing. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The third and fourth variable display devices 43 and 44 are composed of, for example, an LCD or the like, and three variable display portions are arranged respectively. In each variable display area of the third variable display device 43, left, middle, and right decorative symbols are variably displayed. The left, middle, and right decorative symbols are displayed on the left and middle of the first variable display device 41, respectively. It corresponds to the special symbols that are variably displayed in the middle and right variable display areas. The left, middle, and right decorative symbols are also variably displayed in the variable display areas of the fourth variable display device 44, and the left, middle, and right decorative symbols are displayed on the second variable display device 42. It corresponds to each special symbol variably displayed in the left, middle and right variable display areas.

  The 1st normal symbol display 51 and the 2nd normal symbol display 52 are provided with a light emitting diode (LED) etc., and are provided with the 1st passage gate and the 2nd passage gate which were provided in the game field. Lighting, blinking, coloring, and the like are controlled in a normal game where the starting condition is that each game ball passes through. When display is performed with a predetermined winning pattern in the normal game, the display result in the normal game is “winning”, and the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 are configured. The movable wing piece of the electric tulip is controlled to tilt until a predetermined time elapses.

  The first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 are tilted (enlarged and opened) by the solenoid 21 (FIG. 2) and the solenoid 22 (FIG. 2), respectively. A tulip-shaped accessory (ordinary electric accessory) having a pair of movable blades controlled to move between positions is configured. The variable display of the special symbol based on the winning of the game ball on the first ordinary variable winning ball device 61 and the variable display of the special symbol based on the winning of the game ball on the second ordinary variable winning ball device 62 are a predetermined number of times. (In this embodiment, it is stored in a first special figure reservation memory 111 (FIG. 5) and a second special figure reservation memory 112 (FIG. 5), which will be described later, up to four times. Here, two normal symbol displays are provided and two ordinary variable winning ball devices corresponding to these are provided. However, as one normal symbol display and one ordinary variable winning ball device, For example, the normal variable winning ball apparatus may be a start winning opening in which a non-tulip entrance does not open.

  The first special variable winning ball device 71 and the second special variable winning ball device 72 have opening / closing plates for opening and closing the winning area by the solenoid 23 (FIG. 3) and the solenoid 24 (FIG. 3), respectively. Prepare. The opening / closing plate is normally closed, and based on the winning of the game ball to the first ordinary variable winning ball device 61, the special game by the first variable display device 41 and the second ordinary variable winning ball device 62. As a result of the special game played by the second variable display device 42 based on the winning of the game ball to the game, when the big hit gaming state is achieved, the solenoid 23 or the solenoid 24 sets the winning area for a predetermined period (for example, 29 Second) or a predetermined number (for example, 10) of winning balls is set to be in a state of being opened (opening cycle), and a game ball falling in the game area is received during the opening. The opening cycle can be repeated up to 16 times, for example. The game balls that have won the first special variable winning ball device 71 or the second special variable winning ball device 72 are detected by a predetermined detection unit. In response to the detection of the winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (not shown).

  A first start prize memory display 45 and a second start prize memory display 46 are provided above the first variable display device 41 and the second variable display device 42, respectively. The first and second start winning memory indicators 45 and 46 are constituted by LEDs, for example. The first start winning memory display 45 is based on the stored contents of the first special figure holding memory 111 (FIG. 4), and the first variable display is performed when a game ball wins the first ordinary variable winning ball device 61. Although the start condition for executing the special figure game by the device 41 is established, the start prize for starting the variable display is not established due to the reason that the previous special figure game is being executed, etc. The number of memories (the number of reserved memories) is displayed. For example, in the first start winning memory display 45, a number of LEDs corresponding to the number of reserved memories of the special figure game by the first variable display device 41 are turned on. Further, the second start winning memory display 46 displays the second variable when the game ball wins the second ordinary variable winning ball device 62 based on the stored contents of the second special figure holding memory 112 (FIG. 4). Start where the start condition for executing the special display game by the display device 42 is established, but the start condition for starting the variable display is not satisfied due to the reason that the previous special figure game is being executed, etc. The number of winning memories (the number of reserved memories) is displayed. For example, in the second start winning memory display 46, the LED corresponding to the number of reserved games stored in the special figure game by the second variable display device 42 is turned on.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or blinks and speakers 8L and 8R that generate sound effects.

  Further, inside the pachinko gaming machine 1, a game ball flow path (collection route) as shown in FIG. 2 is arranged. The collection route includes a pipe-shaped first flow path 1101 having one end connected to the winning opening 61A of the first ordinary variable winning ball apparatus 61, and one end to the winning opening 62A of the second ordinary variable winning ball apparatus 62. Are connected to each other, and a pipe-shaped second flow path 1102 and a first flow path 1101 and a third flow path 1103 from which the game balls flowing down the second flow path 1102 flow together.

  A winning opening 61A of the first ordinary variable winning ball apparatus 61 in the first flow path 1101 is a first switch constituted by a microswitch or the like that detects a winning ball and outputs a first winning ball detection signal SDA. The start winning port switch 70A is arranged, and a winning ball 62A of the second ordinary variable winning ball device 62 in the second flow path 1102 is detected and a second winning ball detection signal SDB is output. A second start winning a prize opening switch 70B composed of a microswitch or the like is disposed. As will be described later with reference to FIG. 10, the first winning ball detection signal SDA and the second winning ball detection signal SDB are sent to the CPU 103 via edge trigger type RS (reset set) flip-flops 75A and 75B, respectively. To be supplied.

  The third flow path 1103 includes a microswitch for detecting a winning ball in the vicinity of the junction of the first flow path 1101 and the second flow path 1102, and starts when a winning ball is detected. A start winning detector 1111 that outputs a winning detection signal SSN is arranged.

  The pachinko gaming machine 1 is equipped with a main board 11 and a display control board 12 as shown in FIG. The main board 11 and the display control board 12 are arranged at appropriate positions on the back surface of the pachinko gaming machine 1, and, for example, eight signal lines of display control signals CD0 to CD7 are wired between the two boards. Further, a signal line for a display control INT signal for transmitting and receiving a strobe signal is also wired between the main board 11 and the display control board 12. In addition, various control boards such as a power supply board, a sound control board, a lamp control board, a payout control board, and an information terminal board are arranged on the back surface of the pachinko gaming machine 1. The display control board 12 may constitute one board together with the voice control board, the lamp control board, etc., or may be provided independently of these boards.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function for setting random numbers used in a special game, a function for inputting a signal from a switch or the like arranged at a predetermined position, and a sub-side control comprising a display control board 12 and a payout control board. Each board has a function of outputting and transmitting a control command as an example of command information as a control signal, and a function of outputting various kinds of information to a hall management computer. The control command transmitted from the main board 11 to the display control board 12 is a display control command transmitted as an electrical signal using, for example, display control signals CD0 to CD7.

  FIG. 4 is an explanatory diagram showing an example of the contents of a display control command sent from the main board 11 to the display control board 12 used in this embodiment. The display control command is composed of 2 bytes. The first byte represents MODE (command classification), the second byte represents EXT (command type), and each is represented in hexadecimal. The first bit of MODE data is always “1”, and the first bit of EXT data is “0”. The command form shown in FIG. 3 is an example, and other command forms may be used. In this example, one control command is composed of two control signals. However, the number of control signals constituting one control command may be one or a plurality of three or more. May be.

  In the example shown in FIG. 4, the command A0XX (h) is a variable display start command for instructing start of variable display of decorative symbols by the third variable display device 43, and the command A1XX (h) is a fourth variable. This is a variable display start command for instructing the display device 44 to start variable display of decorative symbols. In the following, it is assumed that XX (h) is an unspecified hexadecimal number, and is a value that is arbitrarily set according to the instruction content by the display control command. On the display control board 12 side, it is possible to specify a variable display device that performs variable display of decorative symbols corresponding to the MODE data included in the variable display start command. Also, decorative symbols corresponding to the EXT data can be specified. The total variable display time, the determination result of whether or not the display result of the variable display becomes the specific display result, the determination result of whether or not to reach, and the like can be specified.

  The commands B0XX (h), B1XX (h), and B2XX (h) are symbol designation commands for designating the left / middle / right fixed symbols of the decorative symbols variably displayed on the third variable display device 43. C0XX (h), C1XX (h), and C2XX (h) are symbol designation commands for designating the left / middle / right determined symbols of the decorative symbols variably displayed on the fourth variable display device 44. In each symbol designating command, the symbol numbers of the first and second decorative symbols are set in XX (h). The command D000 (h) is a decoration design confirmation command for instructing stop of variable display of the first decorative design, and the command D100 (h) is a design for instructing stop of variable display of the second decorative design. This is a symbol confirmation command. The command D000 (h) is a jackpot end command for instructing the end of the jackpot gaming state.

  Other display control commands include a jackpot start command indicating that the jackpot gaming state is started, a probability change start command indicating that the probability variation control is started when the jackpot gaming state is ended, and when the jackpot gaming state is ended. In addition, a time-short start command indicating that the time-short control is started, a probability change end command indicating that the time-varying control is ended, a time-short end command indicating that the time-short control is ended may be prepared.

  As shown in FIG. 3, the main board 11 has first and second ordinary variable winning ball devices 61 and 62 that are start winning ports, and first and second special variable winning ball devices 71 that are large winning ports. In addition, each winning port switch 70 for detecting a winning of a game ball to 72 or other winning ports and wiring from the start winning detector 1111 are also connected. Further, on the main board 11, the movable wing piece movement control in the first and second ordinary variable winning ball devices 61 and 62 and the opening / closing control in the first and second special variable winning ball devices 71 and 72 are provided. Wirings to solenoids 21, 22, 23 and 24 for performing the above are connected.

  The main board 11 is configured by mounting a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101 for storing a game control program, a RAM (Random Access Memory) 102 used as a work memory, and a game control. A CPU (Central Processing Unit) 103 that performs control operations according to the application program 110, an I / O (Input / Output) port 104, and a random counter 113 are included.

  As shown in FIG. 5, the game control microcomputer 100 includes a first special figure reservation memory 111, a second special figure reservation memory 112, a jackpot determination table memory 114, and a symbol determination function. A table memory 115, a variable display pattern determination table memory 116, a probability variation counter 117, a flag memory 118, a variable display time timer 119, and a winning order memory 1221 are provided.

  The first special figure holding memory 111 has established a condition (starting condition) for a game ball to win the first ordinary variable winning ball apparatus 61 and execute a special symbol variable display (special game). This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as executing the previous variable display. The second special figure holding memory 112 is a memory for storing a holding state in which the start condition is satisfied when the game ball wins the second ordinary variable winning ball apparatus 62 but the start condition is not satisfied. .

  Each of the first special figure reservation memory 111 and the second special figure reservation memory 112 is provided with four entries and a reading area. In each entry of the first special figure holding memory 111, a holding number and a random value (random R1 value to be described later) extracted by the winning order in the winning order to the first ordinary variable winning ball apparatus 61 are stored in the second order. Each entry in the special figure holding memory 112 stores a holding number and a random value extracted by the winning order in association with the second ordinary variable winning ball apparatus 62 in association with each other. Each time the variable display of the variable display of special symbols and decorative symbols ends or the big hit gaming state ends, the variable display start condition based on the highest level information is established, and the highest level information is displayed. Based on the variable display is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball is newly won in the first ordinary variable winning ball device 61 or the second ordinary variable winning ball device 62 during the variable display of special symbols and decorative symbols, the random value resulting from the winning is the highest. Registered in the upper empty entry.

The game control microcomputer 100 generates random numbers R1 to R5 which are random numbers for determination and display used for game control as shown in FIG.
Among them, the random R1 is generated by the random counter 113 shown in FIG. 3 and is a big hit determination random number that determines whether or not the pachinko gaming machine 1 is brought into a specific gaming state by generating a big hit, It takes a value in the range of “0” to “65535”. The configuration and operation of the random counter 113 will be described later with reference to FIGS.

  The random numbers R2 to R5 are generated when the CPU 103 executes random number software. Random R2 is a reach determination random number that determines whether or not to reach when lost, and takes a value in the range of “0” to “1530”. Random R3 is a display random number for determining a variable display pattern used for variable display of the special symbol, and takes a value in the range of “0” to “149”.

  Random R4-1 is a random number that determines a fixed symbol of the special symbol at the time of big hit and a fixed symbol of the left symbol at the time of losing, and takes a value in the range of “0” to “106”. Random R4-2 is a random number that determines a fixed symbol in the middle symbol at the time of losing, and takes a value in the range of “0” to “162”. Random R4-3 is a random number that determines a definite symbol in the right symbol at the time of normal losing without reach, and takes a value in the range of “0” to “72”. Random R5 is a random number for determining whether or not to perform probability variation control (probability variation control) for shifting to the probability improvement state after putting the pachinko gaming machine 1 into the big hit gaming state, and is “0” to “9”. Takes a value in the range.

  In this embodiment, the random R1 to R5 are commonly used for both the special game by the first variable display device 41 and the special game by the second variable display device 42. Note that it is possible to use separate random numbers for the special game by the first variable display device 41 and the special game by the second variable display device 42, but in this way, a random number is generated. As the circuit configuration increases, the number of random numbers counted by the random counter 113 increases, and the processing load on the CPU 103 due to the management of random numbers such as updating of random numbers and shifting to initial values increases, which is not appropriate.

  The big hit determination table memory 114 shown in FIG. 5 stores a plurality of big hit determination tables set for the CPU 103 to determine whether or not the display result in the special figure game is a big hit. Specifically, the big hit determination table memory 114 stores a normal time big hit determination table 120 shown in FIG. 7A and a probability change big hit determination table 121 shown in FIG. 7B.

  The normal big hit determination table 120 shown in FIG. 7A and the probability variation big hit determination table 121 shown in FIG. 7B are based on the first variable display device 41 and the second variable display device 42. It is a table for determining whether the display result of a special figure game is a big hit. In each of the big hit determination tables 120 and 121, the value of the random R1 and the setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 121, more random R1 values are associated with the display result of “big hit” than the normal big hit determination table 120. That is, by determining the display result of the special figure game using the probability change jackpot determination table 121, it is possible to achieve a probability improvement state in which the probability of becoming a big hit gaming state is higher than in the normal gaming state.

  The symbol determination table memory 115 shown in FIG. 5 determines a plurality of types of symbols used to determine a fixed symbol of a special symbol variably displayed on the first variable display device 41 or the second variable display device 42. Store the table. Specifically, the symbol determination table memory 115 includes a normal jackpot symbol determination table 130 shown in FIG. 8 (A), a probability variation jackpot symbol determination table 131 shown in FIG. 8 (B), and FIG. 8 (C). The left symbol determination table 132 shown in FIG. 8A, the middle symbol determination table 133 shown in FIG. 8D, and the right symbol determination table 134 shown in FIG. 8E are stored.

  The normal jackpot symbol determination table 130 shown in FIG. 8A derives and displays the same normal jackpot symbol on the left, middle and right as the display result of the special game of the first and second variable display devices 41 and 42. This is a table for determining a definite symbol (first normal jackpot symbol) for each special symbol. For example, in the normal jackpot symbol determination table 130, a symbol number of a special symbol as a normal jackpot symbol that is selected and determined as a confirmed symbol and a value of random R4-1 are stored in association with each other.

  The probability variation jackpot symbol determination table 131 shown in FIG. 8B derives and displays the same probability variation jackpot symbol on the left, middle, and right as the display result of the special figure game by the first and second variable display devices 41 and 42. It is a table for determining the fixed symbol (probability big hit symbol) of each special symbol when doing. For example, in the probability variation jackpot symbol determination table 131, a symbol number of a special symbol as a probability variation jackpot symbol selected and determined as a confirmed symbol and a value of random R4-1 are stored in association with each other.

  The left symbol determination table 132 shown in FIG. 8C is displayed when the display result of the loss is derived and displayed without making a big hit in the special game by the first and second variable display devices 41 and 42. It is a table for determining the fixed symbol (1st left fixed symbol) in a variable display part. For example, in the left symbol determination table 132, a symbol number of a special symbol that is a fixed symbol in the first and second left variable display portions and a value of random R4-1 are stored in association with each other.

  The middle symbol determination table 133 shown in FIG. 8D is determined in the middle variable display unit when the display result of the losing is derived and displayed in the special game by the first and second variable display devices 41 and 42. It is a table for determining a symbol (medium fixed symbol). For example, in the middle symbol determination table 133, the addition value for the symbol number of the left determined symbol and the value of random R4-2 are stored in association with each other. That is, at the time of losing without a big hit, the left value determined using the left symbol determining table 132 is the added value determined using the middle symbol determining table 133 based on the value of the random R4-2 extracted from the random counter 113. By adding to the symbol number of the confirmed symbol, the medium confirmed symbol can be determined. In addition, when the display result of the loss is derived and displayed without reaching a big hit after reaching, if the added value determined using the middle symbol determination table 133 is “0”, the derived display In order to lose the result, the symbol number of the medium fixed symbol may be incremented by one.

  The right symbol determination table 134 shown in FIG. 8 (E) is confirmed in the right variable display section when the display result of the losing is derived and displayed in the special game by the first and second variable display devices 41 and 42. It is a table for determining a symbol (right decision symbol). For example, in the right symbol determination table 134, an addition value for the symbol number of the left determined symbol and a value of random R4-3 are stored in association with each other.

  The variable display pattern determination table memory 116 shown in FIG. 5 stores a plurality of variable display patterns used in the special figure game. Specifically, the variable display pattern determination table memory 116 includes a normal loss variable display pattern determination table 150 shown in FIG. 9A, a reach loss variable display pattern determination table 151 shown in FIG. The big hit variable display pattern determination table 152 shown in (C) is stored.

  The normal-losing variable display pattern determination table 150 shown in FIG. 9A derives and displays the fixed symbols of the losing without reaching in the special game by the first and second variable display devices 41 and 42. It is a table for selecting a variable display pattern. The reach-losing variable display pattern determination table 151 shown in FIG. 9B shows the final symbol of the lose without making a hit after reaching the special figure game by the first and second variable display devices 41 and 42. It is a table for selecting the variable display pattern to derive and display.

  The big hit time variable display pattern determination table 152 shown in FIG. 9C is a variable display in which the display result of the special symbol variable display in the special figure game by the first and second variable display devices 41 and 42 is a big hit. It is a table for selecting a pattern.

  Each of the variable display pattern determination tables 150 to 152 includes, for example, a plurality of variable display patterns, a random R3 value, a total variable display time of a special symbol measured by the variable display time timer 119, and a variable display start command. A control code set as EXT data is stored in association with each other. Based on the value of the random R3, a variable display pattern to be executed when the special symbol is variably displayed in the special game is selected from the variable display pattern determination tables 150 to 152.

  The variable display start command sent from the main board 11 to the display control board 12 specifies a variable display pattern in the special symbol variable display by EXT data. Different variable display patterns are used depending on whether the display result is lost or a big hit. For this reason, on the display control board 12 side, it corresponds to a special symbol variably displayed on the first variable display device 41 or the second variable display device 42 by the variable display start command transmitted from the main board 11. The decorative design can be variably displayed on the third variable display device 43 or the fourth variable display device 44, and whether or not the display result in the variable display of the decorative design is used as the specific display result is specified. can do.

  Different variable display pattern determination tables are used depending on whether the first variable display device 41 performs variable display of special symbols or the second variable display device 42 performs variable display of special symbols. Is set. Therefore, on the display control board 12 side, the variable display device that performs the special figure game can be specified by the variable display start command transmitted from the main board 11.

  The normal A and normal B variable display patterns selected using the normal loss variable display pattern determination table 150 are variable display patterns that do not involve a reach mode. The variable display pattern of reach A (losing) selected using the reach-change variable display pattern determination table 151 is a variable display pattern that includes a reach mode but does not cause a variable display result (determined symbol) to cause a big hit. is there. The variable display pattern of reach A (big hit) selected using the big hit hour variable display pattern determination table 152 is a variable display pattern that accompanies the reach mode and the variable display result causes a big hit.

  The variable display pattern of reach B is a variable display pattern having a reach form different from reach A. Here, different reach modes mean that different variable display modes (variable display speed and rotation direction of special symbols, etc.), characters, etc. appear after reaching reach. For example, in the reach A, the reach mode is realized by only one type of variable display mode, whereas in the reach B, the reach mode including a plurality of variable display modes having different variable display speeds and rotation directions of special symbols is provided. Realized.

  In addition, the variable display pattern of reach C is a variable display pattern having a reach form different from reach A and reach B. Unlike the reach A to reach C, the variable display pattern of reach D is a variable display pattern in which reach effect display by moving images is performed. In Reach A to Reach D, there are cases where a big hit and cases where a big hit is not made.

  Further, when the reach-losing variable display pattern determination table 151 and the big hit variable display pattern determination table 152 are compared, the assignment of the random R3 value to each variable display pattern (reach type) is different. That is, the ratio of reach types to be selected differs depending on whether or not the display result in the special figure game is a big hit. Accordingly, the probability that the display result is a big hit differs depending on the type of reach that appears in the special figure game.

  For example, in the example shown in FIG. 9, in the special game, when the display result is lost, the ratio that the reach A variable display pattern is used is higher than the ratio that the reach D variable display pattern is used. . On the other hand, when the display result is a big hit, the ratio at which the reach display variable display pattern is used is lower than the ratio at which the reach D variable display pattern is used. For this reason, when the reach by the variable display pattern of reach D appears in the special figure game, the probability that the display result will be a big hit is higher than when the reach by the variable display pattern of reach A appears.

  The probability variation counter 117 shown in FIG. 5 is for counting the remaining number of special figure games that can be executed in the probability improvement state in which probability variation control is performed. The probability variation counter 117 is predetermined to be executable in the probability improvement state when the display result of the special figure game by the first variable display device 41 or the special figure game by the second variable display device 42 is a probable big hit. Data indicating “100”, which is the number of times of the special figure game, is set as an initial value. Each time the special symbol variable display in the special figure game is finished without the display result being a big hit in the probability improvement state, the count value of the probability variation counter 117 is decremented by one.

  The flag memory 118 is for setting a plurality of types of flags used for controlling the progress of the game in the pachinko gaming machine 1. For example, the flag memory 118 includes first and second special symbol process flags, first and second normal symbol process flags, first and second jackpot state flags, first and second probability change confirmation flags, A probability changing flag, a probability changing end flag, first and second variable display time timer stop flags, an input status flag, an error flag, a timer interrupt flag, and the like are provided.

  The first special symbol process flag indicates which process should be selected and executed in a first special symbol process (described later in step S16 in FIG. 19 (FIG. 21)). The second special symbol process flag indicates which process should be selected and executed in a second special symbol process (described later in step S16 in FIG. 19 (FIG. 21)). The first normal symbol process flag indicates which process should be selected and executed in the first normal symbol process. The second normal symbol process flag indicates which process should be selected and executed in the second normal symbol process.

  The first big hit state flag is set to an on state when the display result of the special figure game by the first variable display device 41 is a big hit (when the big hit state is established), and when the big hit gaming state is ended ( It is cleared and turned off when the big hit state ends. The second big hit state flag is set to an on state when the display result of the special figure game by the second variable display device 42 is a big hit (when the big hit state is established), and when the big hit gaming state is ended ( It is cleared and turned off when the big hit state ends.

  The first certainty change confirmation flag is set to the on state when it is determined that the variable display result in the special figure game is a probable big hit when the special variable game is started by the first variable display device 41. And cleared when the big hit gaming state ends. The second certainty change confirmation flag is set to the on state when it is determined that the variable display result in the special figure game is a probable big hit when the special variable game is started by the second variable display device 42. And cleared when the big hit gaming state ends.

  The probability variation flag is set to an on state when either the first or second probability variation confirmation flag is on when the big hit gaming state ends, and the count value of the probability variation counter 117 is “0”. It is cleared and turned off when it becomes a big hit gaming state based on a normal big hit. The probability variation end flag is set to the on state when it is determined in the first and second winning processes (i = 1 or 2 in FIG. 22) to end the probability improvement state, and the probability improvement state is set. Is cleared and turned off when exits.

  The input state flag is a flag composed of a plurality of bits that are set or cleared in accordance with the state of various signals input to the I / O port 104, the state of the detection signal input from each winning port switch 70, and the like. The error flag is a flag composed of a plurality of bits in which bits corresponding to the type of error that has occurred are set when various errors occur in the pachinko gaming machine 1. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The first variable display time timer stop flag is displayed when a big hit symbol is derived and displayed on the second variable display device 42 during execution of the special figure game by the first variable display device 41 (a big hit state is established). At the time), it is set to the on state, and when the big hit gaming state is finished (at the time the big hit state is finished), it is cleared and turned off. The second variable display time timer stop flag is displayed when a big hit symbol is derived and displayed on the first variable display device 41 during execution of the special figure game by the second variable display device 42 (a big hit state is established). At the time), it is set to the on state, and when the big hit gaming state is finished (at the time the big hit state is finished), it is cleared and turned off.

  The variable display time timer 119 shown in FIG. 5 includes a first variable display time timer and a second variable display time timer. The first variable display time timer is a down counter for measuring on the main side the variable display time that is the execution time of the special figure game by the first variable display device 41, and the second variable display time timer is It is a down counter for measuring the variable display time which is the execution time of the special figure game by the 2nd variable display apparatus 42 by the main side. When the variable display start command is sent from the main board 11 to the display control board 12, the first and second variable display time timers have a count value corresponding to the total variable display time specified by the variable display pattern. Set as initial value.

  The winning order memory 1221 shown in FIG. 5 is a game ball in any of the first and second ordinary variable winning ball devices in the winning order to the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62. Information indicating whether or not has won. This information is used to determine which normal variable winning ball apparatus has won when the start winning detector 1111 detects the start winning.

  When determining that the first winning ball detection signal SDA is at a high level in the winning opening switch process shown in FIG. 20, the CPU 103 determines that the first ordinary variable winning ball device 61 has won, and the first When the flag (“1” in the figure) indicating the normal variable winning ball device 61 is set in the first entry among the empty entries and it is determined that the second winning ball detection signal SDB is at the high level, the second It is determined that the ordinary variable winning ball device 62 has won, and a flag (“2” in the figure) indicating the second ordinary variable winning ball device 62 is set in the head entry of the empty entries. In the special symbol process of FIG. 21, the CPU 103 determines the value of the first entry when determining that the start winning signal from the start winning detector 1111 is SS high level and some start winning match has been achieved. It is determined which of the ordinary variable winning ball apparatus 61 and the second ordinary variable winning ball apparatus 62 has won, and a winning process is executed as appropriate. When the winning process is completed, the first entry is cleared, and the stored data after the second entry is advanced by one entry.

  Note that the number of entries in the winning order memory 1221 is appropriately selected based on the period of game control interrupt processing (to be described later) of the CPU 103, the time required for the game ball to flow down the game medium flow paths 1101 and 1102, etc. For example, if the interrupt cycle is about several milliseconds, the number of entries can be two.

  The switch circuit 107 shown in FIG. 3 takes in the detection signal from each winning opening switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives each of the solenoids 21, 22, 23 and 24 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the first ordinary variable winning ball apparatus 61 via a link mechanism. The solenoid 22 is connected to the movable wing piece of the second ordinary variable winning ball apparatus 62 via a link mechanism. The solenoid 23 is connected to the opening / closing plate of the first special variable winning ball apparatus 71 through a link mechanism. The solenoid 24 is connected to the opening / closing plate of the second special variable winning ball device 72 through a link mechanism.

Next, the details of the random counter 113 will be described with reference to FIG.
As shown in FIG. 10, the random counter 113 includes a reference clock signal generation circuit 1201, a count clock signal generation circuit 1202, a counter 1203, a latch signal generation circuit 1204, and a latch circuit 1205.

  The reference clock signal generation circuit 1201 includes a crystal resonator or the like and supplies an operation clock S0 of 20 MHz, for example.

  The count clock signal generation circuit 1202 is composed of a D-type flip-flop, the reference clock signal S0 is supplied to the clock terminal Clk, and the negative phase output (Q bar) signal S2 is fed back to the D input terminal.

With such a configuration, the count clock signal generation circuit 1202 divides the reference clock signal S0 by ½, and outputs the normal phase output Q to the counter 1203 as the count clock signal S1, and the reverse phase output (Q bar). The signal S2 is supplied to the clock terminal Clk of the latch signal generation circuit 1204.
The count clock signals S1 and S2 are signals having the same frequency (10 MHz) and opposite phases.

  The counter 1203 is composed of an up counter, and counts up the count value C from “0” to “65535” one by one in response to the rising edge of the count clock signal S1. When the counter 1203 counts up the count value C to “65535”, the counter 1203 returns to “0” and again counts up to “65535”.

  A reference clock signal generation circuit 1201, a count clock signal generation circuit 1202, a counter 1203, and a numerical data update circuit that updates and outputs numerical data within a predetermined update range of 0 to 65535 at a predetermined cycle. 1211 is configured.

  The latch signal generation circuit 1204 includes a D-type flip-flop, the count clock signal S2 is supplied to the clock terminal Clk, and the start prize signal SSN is supplied from the start prize detector 1111 disposed in the third flow path 1103. When this occurs, it is supplied to the clock terminal of the latch circuit 1205 as a latch signal SL in synchronization with the count clock signal S2.

  The latch circuit 1205 latches numerical data output from the counter 1203 in response to the latch signal SL from the latch signal generation circuit 1204. Since the count clock signal S1 and the latch timing signal S2 are opposite in phase, the latch circuit 1205 stabilizes the numerical data at a substantially intermediate point in time from when the counter 1203 updates the numerical data until the next update. When in the state, numerical data is latched.

  On the other hand, the first start winning opening switch 70A disposed in the winning opening 61A of the first ordinary variable winning ball apparatus 61 outputs a low level signal in a normal state, and when a winning ball is detected, the first start winning opening switch 70A is at a high level for a predetermined period. The first winning ball detection signal SDA is output. The first winning ball detection signal SDA is supplied to an edge trigger type first RS flip-flop. The first RS flip-flop 75A is set when the first winning ball detection signal SDA changes from the low level to the high level, and the first winning ball detection signal SDA ′ at the high level is sent from the Q output terminal to the CPU 103. Output.

    The second start winning port switch 70B disposed in the winning port 62A of the second ordinary variable winning ball device 62 outputs a low level signal in a normal state, and when a winning ball is detected, the second start winning port switch 70B is in a high level for a predetermined period. 2 winning ball detection signal SDB is output. The second winning ball detection signal SDB is supplied to a second RS flip-flop of the edge trigger type. The second RS flip-flop 75B is set when the second winning ball detection signal SDB changes from the low level to the high level, and the high winning level second winning ball detection signal SDB ′ is sent from the Q output terminal to the CPU 103. Output.

  As the latch circuit 1205, for example, a configuration as shown in FIG. 11 can be adopted. As illustrated, the latch circuit 1205 includes two AND circuits 1301 and 1303, two NOT circuits 1302 and 1304, 16 flip-flop circuits 1311 to 1326, and 16 OR circuits 1331 to 1346. , Is composed of.

  The input terminal of the AND circuit 1301 is connected to the output port of the CPU 103 and the output terminal of the NOT circuit 1304, and the output terminal is connected to the input terminal of the NOT circuit 1302 and the clock terminals Clk1 to Clk16 of the flip-flop circuits 1311 to 1326. It is connected. The input terminal of the NOT circuit 1302 is connected to the output terminal of the AND circuit 1301, and the output terminal is connected to one input terminal of the AND circuit 1303.

  The input terminal of the AND circuit 1303 is connected to the output terminal of the NOT circuit 1302 and the output port of the CPU 103, and the output terminal is connected to the input terminal of the NOT circuit 1304. The input terminal of the NOT circuit 1304 is connected to the output terminal of the AND circuit 1303, and the output terminal is connected to one input terminal of the AND circuit 1301 and one input terminal of each of the OR circuits 1331 to 1338.

  The flip-flop circuits 1311 to 1326 are composed of D flip-flops, and each of the input terminals D1 to D16 is connected to the output terminal of the counter 1203, and any of the 16-bit bit data constituting the count value C is supplied. Yes. The clock terminals Clk1 to Clk16 of the flip-flop circuits 1311 to 1326 are connected to the output terminal of the AND circuit 1301, and the output terminals Q1 to Q16 are connected to the other input terminal of each of the OR circuits 1331 to 1346.

  The input terminals of the OR circuits 1331 to 1346 are connected to the output terminal of the NOT circuit 1304 and the corresponding output terminals of the flip-flop circuits 1311 to 1326, and the output terminals are connected to the input port of the CPU 103.

  In this configuration, in the initial state, both the latch signal SL and the read control signal SRC are at a low level. The output of the AND gate 1301 is low level, the output of the NOT circuit 1302 is high level, the output of the AND gate 1303 is low level, the output of the NOT circuit 1304 is high level, and the OR gates 1331 to 1346 all output high level signals. To do. In this state, when a start winning is generated, the start winning signal SSN becomes high level, and the CPU 103 sets the latch signal SL to high level, the output of the AND gate 1301 also becomes high level, and each of the flip-flops 1311 to 1326 becomes The corresponding bits C1 to C16 of the count value (random value) are latched. On the other hand, the output of the NOT circuit 1302 becomes a low level. Therefore, the read control signal SRC from the CPU 103 is not accepted while the first latch signal SLA (or SLB) is at the high level. Therefore, while the D flip-flops 1311 to 1326 are updating the count value, the CPU 103 does not read the unstable (incomplete) random number value being updated.

  On the other hand, in the initial state (start winning signal SSN is at low level), if the read control signal SRC is set to high level in order for the CPU 103 to read the random number value, the output of the NOT circuit 1304 becomes low level, and the OR gates 1331 to 1346 outputs the output data (stored value) of the flip-flops 1311 to 1326 to the I / O port of the CPU 103 as it is. In addition, since one input of the AND gate 1301 is at a low level, the AND gate 1301 does not accept the latch signal SL. Therefore, while the CPU 103 reads the random number value by setting the read control signal SRC to the high level, the random number value is not updated, and the random value can be read stably.

  FIG. 12 is a timing chart for explaining the operation of the random counter 113.

  As shown in FIG. 12A, the reference clock signal generation circuit 1201 has a frequency of 1 kHz, rises from a low level to a high level at timings T11, T12,..., And changes from a high level to a low level at the midpoint of one cycle. The falling reference clock signal S0 is output to the count clock signal generation circuit 1202.

  The count clock signal generation circuit 1202 substantially divides the reference clock signal S0 by ½, and the count clock signal S1 of 10 MHz as shown in FIGS. 12B and 12C and its inverted signal are counted. The clock signal S2 is converted and output from the positive phase output terminal (Q) and the negative phase output terminal (Q bar).

  As shown in FIG. 12D, the counter 1203 updates and outputs the count value (count value data) C in response to the rising edge of the count clock signal S1.

  Here, for example, when a game ball wins the first ordinary variable winning ball device 61, as shown in FIG. 12E, the first winning port switch 70A outputs the first winning ball detection signal SDA. . Almost in synchronization with the rising edge of the first winning ball detection signal SDA, the Q output SDA 'of the first RS flip-flop 75A also goes high. In this case, the second winning ball detection signal SDB output from the second winning opening switch 70B remains at a low level as shown in FIG. 12 (F), and the Q output of the second RS flip-flop 75B. (Second winning ball detection signal) SDB ′ maintains a low level.

  The game ball that has won the first ordinary variable winning ball device 61 rolls (flows down) in the first flow path 1102, enters the first common flow path 1103, and is started by the start winning detector 1111 near the junction. Detected. For this reason, as shown in FIG. 12 (G), the start winning detection signal SSN is slightly delayed from the first winning ball detection signal SDA (normally 2 s to 100 ms depending on the length of the first flow path 1101). Is output.

  As shown in FIG. 12H, the latch signal generation circuit 1204 synchronizes the start winning detection signal SSN with the rising edge of the count clock signal S2, and outputs it as a latch signal SL. The latch circuit 1205 As shown in (I), the count value of the counter 1203 is latched. The CPU 103 takes in the latch value of the latch circuit 1205 in a special symbol process process, which will be described later, and uses this to advance the special symbol game.

  The display control board 12 shown in FIG. 3 performs display control for image processing in the variable display game independently of the main board 11. The display control board 12 displays an image used in the variable display game on the third variable display device 43 and the fourth variable display device 44 based on the display control command output from the main board 11. That is, the display control board 12 controls the display operation of the third variable display device 43 and the fourth variable display device 44 based on a control command from the main board 11, thereby displaying images related to the progress of the game. Control the production.

  FIG. 13 is a block diagram illustrating a hardware configuration example of the display control board 12. The display control board 12 includes an oscillation circuit 200, a reset circuit 201, a CPU 202 for display control, a ROM 203, a RAM 204, a GCL (Graphic Control LSI) 205, a CGROM 206, and a VRAM (Video RAM) 207. I have.

  The oscillation circuit 200 outputs a reference clock signal to the CPU 202 and the GCL 205, and the reset circuit 201 outputs a reset signal for resetting the CPU 202 and the GCL 205. When the CPU 202 receives a display control command from the main board 11, the CPU 202 reads control data for performing display control from the ROM 203 while using the RAM 204 as a work area. Further, the CPU 202 sends a drawing command to the GCL 205 based on the read control data. The ROM 203 is a semiconductor memory that stores various control programs used by the CPU 202, and the RAM 204 is a semiconductor memory used as a work area by the CPU 202.

  The GCL 205 has a display device control function for performing image display and a high-speed drawing function, and operates in accordance with a drawing command from the CPU 202. Further, it has a two-dimensional address space independent of the CPU 202, and the VRAM 207 is mapped there. The CGROM 206 is for storing various image data for displaying images on the third variable display device 43 and the fourth variable display device 44. For example, in the CGROM 206, character image data frequently used among images displayed on the third variable display device 43 and the fourth variable display device 44, specifically, a person, an animal, or a character, Figures or symbols are stored in advance. A VRAM 207 is a frame buffer memory for expanding image data generated by the GCL 205.

  The display control board 12 includes a random counter 211, a display control pattern table memory 212, a flag memory 214, and various timers 215, as shown in FIG.

  The random counter 211 counts a random R10, which is a random number used to determine the content of the effect produced by the display on the third variable display device 43 or the fourth variable display device 44. As shown in FIG. 15, the random R10 is a random number for determining which one of the plurality of types of display control patterns stored in the display control pattern table memory 212 is to be used in the current decorative symbol game. "Takes a value in the range of" 9 ".

  The display control pattern table memory 212 shown in FIG. 16 stores a plurality of display control pattern tables selected based on the display control command received from the main board 11. Specifically, the display control pattern table memory 212 includes a symbol display control pattern table 220 and the like as shown in FIG.

  The symbol display control pattern table 220 shown in FIG. 17 stores a plurality of types of symbol display control patterns. As shown in FIG. 17, each symbol display control pattern includes data for controlling the display state of a decorative symbol such as a symbol display control process timer setting value, symbol display control data, and the like. The display speed, the size of the pattern to be displayed, the display period in the display state, the character switching timing, and the like are set.

  The flag memory 214 is for setting a plurality of types of flags that are set or cleared in accordance with the display state of the third and fourth variable display devices 43 and 44 and the reception of a command from the main board 11. For example, the flag memory 214 includes first and second display control process flags, first and second notification effect start flags, first and second variable display start flags, first and second valid flags, Third and fourth variable display time timer stop flags, a timer interrupt flag, and the like are provided.

  The first display control process flag indicates which process should be selected / executed in the first decorative symbol display control process (described later when i = 1 in the i-th decorative symbol display control process in FIG. 33). Instruct. The second display control process flag indicates which process should be selected / executed in a second decorative symbol display control process (described later when i = 2 in the i-th decorative symbol display control process of FIG. 33). Instruct.

  The first notification effect start flag is set to an on state when the first notification effect start command 8000 (h) is received from the main board 11, and the second notification effect start flag is set to the second value from the main board 11. Is turned on when the notification effect start command 8100 (h) is received. The first notification effect end flag is set to the on state when the first notification effect end command 9000 (h) is received from the main board 11, and the second notification effect end flag is set to the second value from the main board 11. When the notification effect end command 9100 (h) is received, it is set to the on state.

  The first variable display start flag is set to an on state when the first variable display start command A0XX (h) is received from the main board 11, and the second variable display start flag is set to the second variable display start flag. Set to ON when command A1XX (h) is received. The first valid flag is set to the on state when the first left / middle / right symbol designation commands B0XX (h), B1XX (h) and B2XX (h) are received from the main board 11, and the second valid flag The valid flag is set to ON when the second left / middle / right symbol designation commands C0XX (h), C1XX (h), and C2XX (h) are received from the main board 11.

  The third variable display time timer stop flag is set to an on state when a big hit symbol is derived and displayed on the fourth variable display device 44 during execution of the special game by the third variable display device 43. When the big hit gaming state is finished, it is cleared and turned off. The fourth variable display time stop flag is set to an on state when a big hit symbol is derived and displayed on the third variable display device 43 during execution of the special figure game by the fourth variable display device 44. When the jackpot gaming state ends, it is cleared and turned off. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  Various timers 215 shown in FIG. 14 are configured to include a plurality of types of timers used for display control of the third variable display device 43 and the fourth variable display device 44. For example, the various timers 215 include first and second symbol display control process timers, third and fourth variable display time timers, and first and second monitoring timers. The first symbol display control process timer variably displays the ornament symbol in a manner according to the display control pattern on the third variable display device 43 by counting down the process timer value set in the symbol display process table. The second symbol display control process timer measures the variable display period in which the fourth variable display device 44 variably displays the decorative symbols in a manner according to the display control pattern.

  The third variable display time timer included in the various timers 215 is a down counter for measuring the variable display time, which is the execution time of the decoration drawing game by the third variable display device 43, on the sub side. The variable display time timer is a down counter for measuring the variable display time, which is the execution time of the decoration drawing game by the fourth variable display device 44, on the sub side. The first monitoring timer is for measuring an elapsed time after the third variable display time timer times out, and the second monitoring timer is after the fourth variable display time timer times out. It is for measuring the elapsed time. The first and second monitoring timers time out when a display control command is not received from the main board 11 for a predetermined time or more.

  In addition, the gaming machine 1 performs the audio output control and the lamp output control independently of the main board 11 based on the control command transmitted from the main board 11, respectively, and the sub-side audio control board and lamp control board Is provided. The sound control board controls the sound output operation by the speakers 8L and 8R based on the control command from the main board 11, thereby controlling the sound effect related to the progress of the game. Further, the lamp control board controls the lighting / flashing operation of the game effect lamp 9 based on the control command from the main board 11, thereby controlling the effect by the lighting, blinking or extinguishing of the lamp related to the progress of the game. The payout control board 15 performs payout control for game balls, prize balls, and the like. Further, the gaming machine 1 includes an information terminal for outputting various game-related information to the outside.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 18 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Also, various periodic timer interrupts are generated by setting a register of a CTC (counter / timer circuit) built in the game control microcomputer 100 (step S2). The mask is released and the interruption is permitted, and for example, the game control interruption process (FIG. 19) can be executed every 2 milliseconds (step S3). Thereafter, the loop processing is started.

  The CPU 103 executes the game control interrupt process shown in the flowchart of FIG. 19 every 2 ms by the processes of steps S2 and S3.

  When the game control interrupt process shown in the flowchart of FIG. 19 is started, the CPU 103 first executes a predetermined switch process, thereby changing the state of the detection signal input from each winning port switch 70 via the switch circuit 107. Determination is made (step S11). Of these switch processes, the processes related to the first and second prize opening switches 70A and 70B will be described later with reference to FIG. Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and if necessary, warning can be generated according to the diagnosis result (step S12). Thereafter, a process of extracting random R1 which is a random number for determination counted by the random counter 113, and a random number update process for determination for updating random R2 and R5 which are random numbers generated by software processing (step S13) Then, the display random number update process for updating the random numbers R3 and R4, which are display random numbers generated by the software process, is sequentially executed (step S14).

  Next, the CPU 103 adds 1 to a pointer i for distinguishing between the first special symbol process process and the second special symbol process process (for example, reserved on the RAM 102), and updates the pointer i. (Step S15). The pointer i takes a value of 1 or 2, and is reset to 1 when the update result is 3.

  Subsequently, the CPU 103 executes the i-th special symbol process (step S16). That is, according to the value of the pointer i, the first special symbol process and the second special symbol process are alternately executed in units of interrupt processing. In the special symbol process, according to the first special symbol process flag and the second special symbol process flag provided in the flag memory 118 in order to control the pachinko gaming machine 1 in a predetermined order according to the gaming state, The corresponding process is selected and executed.

  Subsequently, the CPU 103 sequentially executes the i-th ordinary symbol process (step S17). In the i-th normal symbol process, in order to control the first normal symbol display 51 and the second normal symbol display 52 in a predetermined order, the first normal symbol process flag and the second normal symbol process The corresponding process is selected and executed according to the flag.

  Further, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the display control board 12 and instruct operation control according to the gaming state. (Step S18). The CPU 202 of the display control board 12 receives the display control command sent from the main board 11 by this command control processing, and the display control of the third and fourth variable display devices 43 and 44 is performed according to the display control command.

  Further, the CPU 103 outputs the contents of the storage area for various output data to each output port included in the I / O port 104 by executing predetermined information output processing (step S19). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to perform the movable control of the movable blade pieces in the first and second ordinary variable winning ball devices 61 and 62 when the predetermined condition is satisfied. The opening / closing drive of the opening / closing plate in the second special variable winning ball devices 71 and 72 is performed (step S20). After that, by executing predetermined prize ball processing, it is possible to set the number of prize balls based on the detection signal input from each prize opening switch 70 and to output a payout control command to the payout control board 15. (Step S21).

  FIG. 20 is a flowchart for explaining processing relating to the first and second start winning opening switches 70A and 70B in the switch processing of FIG.

  The CPU 103 starts the process of FIG. 20 within the switch process. First, it is determined whether or not the first winning ball detection signal SDA ′ is at a high level (ON), that is, the first ordinary variable winning ball device 61. It is determined whether or not there has been a win (step S31).

  If the first winning ball detection signal SDA 'is low level (off) (step S31; No), the process jumps to step S34 described later.

  On the other hand, if the first winning ball detection signal SDA ′ is at the high level (ON) (step S31; Yes), the game ball has won the first ordinary variable winning ball device 61, so that the winning order memory 1221 is obtained. A flag “1” indicating the first ordinary variable winning ball device 61 is set in the first entry among the empty entries in FIG. 5 (step S32).

  Thereafter, the CPU 103 sends a reset signal to the first RS flip-flop 75A to reset the first winning ball detection signal SDA '(step S33). Accordingly, it is not erroneously recognized that the first ordinary variable winning ball apparatus 61 has won a prize in the next game control interruption process after 2 ms. Note that since the first RS flip-flop 75A is an edge trigger type, even if the first winning ball detection signal SDA is maintained at a high level for a while, it is not reset.

  Subsequently, the CPU 103 determines whether or not the second winning ball detection signal SDB ′ is at a high level (ON), that is, whether or not there is a winning in the second ordinary variable winning ball device 62 (step S34). ).

  If the second winning ball detection signal SDB 'is low level (off) (step S34; No), the current process is terminated and the process returns to the main process.

  On the other hand, if the second winning ball detection signal SDB ′ is at the high level (ON) (step S34; Yes), the game ball has won the second ordinary variable winning ball device 62, so that the winning order memory 1221 is obtained. The flag “2” indicating the second ordinary variable winning ball device 62 is set in the first entry among the empty entries in FIG. 5 (step S35).

  Thereafter, the CPU 103 sends a reset signal to the second RS flip-flop 75B to reset the second winning ball detection signal SDB '(step S36).

  FIG. 21 is a flowchart showing the i-th special symbol process executed in step S16. When the i-th special symbol process is started, the CPU 103 first determines whether or not the start winning detection signal SSN output from the start winning detector 1111 is at a high level (step S101). When the start winning detection signal SSN is at a low level (step S101; No), it is not necessary to process the start winning, so steps S102 and S103 are skipped.

  On the other hand, when the start winning detection signal SDN is at a high level (step S101; Yes), it is necessary to process the start winning, so whether the game ball has won the first ordinary variable winning ball device 61, The first winning ball detection signal SDA ′ output from the first RS flip-flop 75A and the second winning ball detection output from the second RS flip-flop 75B are used to determine whether the two ordinary variable winning ball devices 62 have been won. It is determined by checking the signal SDB ′, and it is determined whether or not it is the i-th ordinary variable winning ball device (step S102). When it is determined that it is not “i” (step S102; No), the i-th winning process (step S103) is skipped, and it is determined that it is “i” (step S102; Yes). The i-th winning process (step S103) is executed.

  FIG. 22 is a flowchart showing the i-th winning process in step S103. In this i-th winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the i-th special figure holding memory 111 or 112 is a maximum value of 4 (step S201).

When the start winning memory number is 4 (step S201; Yes), the start detection by the current winning is invalidated and the process jumps to step S205 described later.
On the other hand, when the starting winning memory number is less than 4 (step S201; No), the starting winning memory number of the i-th special figure holding memory 111 or 112 is incremented by 1 (step S202), and the random counter 113 determines the random R1. A value is read (step S203). That is, the CPU 103 sets the read control signal SRC to a high level, enables reading of the data stored in the latch circuit 1205, takes in the numerical data stored in the latch circuit 1205, and then turns off the read control signal SRC (step S103). S203).

Subsequently, the CPU 103 sets the read random R1 at the head of the empty entry in the i-th special figure reservation memory 111 or 112 (step S204). At this time, the i-th start-up memory display 45 or 46 turns on one of the LEDs that are turned off (for example, the leftmost LED among the turned-off LEDs). Lighting control of the winning memory display 45 or 46 is performed.
Subsequently, the CPU 103 clears the contents of the first entry in the winning order memory 1221 and shifts the contents after the second entry up by one entry (step S205).
This is the end of the winning process.

  When it is determined as Yes (no winning) in step S201, or after step S204, the CPU 103 performs steps shown in FIG. 21 based on the value of the i-th special symbol process flag provided in the flag memory 118. One of the nine processes of S110 to S118 is selected. Below, each process of step S110-S118 is demonstrated.

  The i-th special symbol normal process in step S110 is a process executed when the value of the i-th special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the i-th special figure reservation memory 111 or 112 is “0”. Here, in the i-th special figure reservation memory 111 or 112, when various data such as a random number value corresponding to the reservation number “1” is not stored, it is determined that the storage number is “0”. The If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the (i + 2) th variable display device 43 or 44 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the i-th special symbol process flag is updated to “1”, which is a value corresponding to the i-th jackpot determination process.

  The i-th jackpot determination process in step S111 is a process executed when the value of the i-th special symbol process flag is “1”. In this process, as shown in FIG. 23, the CPU 103 first reads the value of the random R1 stored in correspondence with the hold number “1” from the i-th special figure hold memory 111 or 112 (step S221). . At this time, the value of the random R1 stored in the second to fourth entries (holding numbers “2” to “4”) of the i-th special figure holding memory 111 or 112 is subtracted by 1 from the holding memory number. One entry is shifted up (step S222).

  Subsequently, the CPU 103 determines whether or not it is in a probability improvement state (probability change) (step S223). If it is not in a probability change state (step S223; No), the CPU 103 determines that it is a normal game state, and the i th A normal big hit determination table 120 as shown in FIG. 7A is set as a table for determining whether or not the display result of the special figure game by the variable display device 41 or 42 is a big hit (step S224). ). On the other hand, if the probability change is in progress (step S223; Yes), the probability change big hit determination table 121 as shown in FIG. 7B is set (step S225).

  The CPU 103 uses the jackpot determination table 120 or 121 set in the process of step S224 or S225 based on the value of the random R1 read in the process of step S221, and performs the special processing by the i-th variable display device 41 or 42. It is determined whether or not the display result of the figure game is a big hit (step S226). If it is determined to be a big hit (step S226; Yes), the i-th big hit state flag provided in the flag memory 118 is set to the on state (step S227), and it is determined to be lost. In this case (step S226; No), the i-th big hit state flag is cleared and turned off (step S228). Thereafter, the value of the i-th special symbol process flag is updated to “2” which is a value corresponding to the i-th confirmed symbol determination process (step S229).

  The i-th determined symbol determination process in step S112 shown in FIG. 21 is a process executed when the value of the i-th special symbol process flag is “2”. In this process, the CPU 103 executes the processes shown in FIGS. 24 and 25, and first determines whether or not the i-th big hit state flag provided in the flag memory 118 is on (step S231). When the i-th big hit state flag is off (step S231; No), a random number program is executed to generate a random R2, extract its value (step S232), and determine whether or not to reach. (Step S233). For example, when the value of random R2 extracted in the process of step S232 is any one of “105” to “1530”, it is determined not to reach, and when it is any one of “0” to “104”. And decide to reach.

  When it is determined not to reach in the process of step S233 (step S233; No), the CPU 103 clears the i-th reach state flag provided in the flag memory 118 and sets it to the off state (step S234). Then, the random number program is executed to generate random R4-1, and based on this value, the i-th left confirmed symbol is determined using the left symbol determining table 132 shown in FIG. 8C (step S235). . Further, the random number program is executed to generate random R4-2, and based on this value, the middle symbol determination table 133 shown in FIG. 8D is used to determine the i-th medium fixed symbol (step S236). ), A random R4-3 is generated by the random number program, and based on this value, the first right determined symbol is determined using the right symbol determining table 134 shown in FIG. 8C (step S237). Thereafter, the process proceeds to step S251.

  Further, when it is determined to reach in the process of step S233 (step S233; Yes), the CPU 103 sets the i-th reach state flag to the on state (step S238), and the random number extracted from the random counter 113 is set. Based on the value of R4-1, the i-th left determined symbol is determined using the left symbol determining table 132 (step S239). Further, it is determined that a special symbol having the same symbol number as the i-th left determined symbol is set as the i-th right determined symbol (step S240), and any special symbol different from the i-th left / right determined symbol is determined. Is determined to be the i-th medium-determined symbol (step S241). Thereafter, the process proceeds to step S251.

  When it is determined in step S231 described above that the big hit state flag is on (step S231; Yes), the CPU 103 executes a random number program to generate a random R5 (step S242), and based on this value Then, it is determined whether or not to perform probability variation control for shifting to the probability improvement state after the big hit gaming state is ended (step S243). For example, it is determined that the probability variation control is performed when the value of the random R5 is an odd number, and it is determined that the probability variation control is not performed when the value of the random R5 is an even number.

  When it is determined that the probability variation control is not to be performed in the process of step S243 (step S243; No), the CPU 103 clears the first probability change confirmation flag provided in the flag memory 118 and sets it to the off state (step S244). ), A first normal jackpot symbol determination table 130 shown in FIG. 7A is set as a table for determining the fixed symbol of the special symbol that is a variable display result of the jackpot (step S245). When it is determined that the probability variation control is to be performed in the process of step S243 (step S243; Yes), the i-th probability variation flag is set to the on state (step S246), and the fixed symbol of the special symbol is determined. As a table for this purpose, a first probability variation big hit symbol determination table 131 shown in FIG. 7B is set (step S247).

  After executing the process of step S245 or S247, the CPU 103 generates a random R4-1 (step S248), and based on the value of the random R4-1, the symbol determination table 130 set in the process of step S245 or S247. Alternatively, 131 is used to determine a decisive symbol for jackpot that is the same for the left, middle, and right (step S249).

  The i-th left / middle / right symbol designation commands B0XX (h), B1XX are set by setting control data corresponding to the confirmed symbol of the special symbol determined in the process of step S249 in a predetermined command transmission table. (H) and B2XX (h) are set to be sendable to the display control board 12 (step S250). Thereafter, the CPU 103 updates the value of the i-th special symbol process flag to “3”, which is a value corresponding to the i-th variable display pattern setting process, and ends the i-th confirmed symbol determination process (step S100). S251).

  The first variable display pattern setting process in step S113 shown in FIG. 21 is a process executed when the value of the first special symbol process flag is “3”. In this process, the CPU 103 executes the process shown in FIG. 26, and first determines whether or not the i-th big hit state flag provided in the flag memory 118 is on (step S261). When the i-th big hit state flag is OFF (step S261; No), it is determined whether or not reach is determined in the i-th determined symbol determination process in step S112 (step S262).

  When not reaching (step S262; No), a normal loss variable display pattern determination table 150 shown in FIG. 9A is set as a table for selecting a variable display pattern (step S263). In the case of reaching (step S262; Yes), a reach-losing variable display pattern determination table 151 shown in FIG. 9B is set as a table for selecting a variable display pattern (step S264).

  Further, when the i-th big hit state flag is ON in the process of step S261 (step S261; Yes), the i-th big hit time variable shown in FIG. 9C is used as a table for selecting a variable display pattern. The display pattern determination table 152 is set (step S265).

  The CPU 103 extracts the value of random R3 from the random counter 113 (step S266), and based on the extracted value of random R3, among the variable display pattern determination tables set in the processing of step S263, S264, or S265. From this, the variable display pattern used in this special figure game is determined (step S267).

  Thereafter, the CPU 103 performs display control of the i-th variable display start command A0XX (h) by setting control data corresponding to the variable display pattern determined in the process of step S267 in a predetermined command transmission table. It is set to be able to send to the substrate 12 (step S268). Then, the variable display of the special symbol is started by the i-th variable display device 41 or 42 (step S269), and the total variable display time corresponding to this variable display pattern is set in the i-th variable display time timer 119. The variable display time timer is set (step S270). Thereafter, the CPU 103 updates the value of the i-th special symbol process flag to “4”, which is a value corresponding to the i-th variable display control process (step S271).

  The i-th variable display control process of step S114 shown in FIG. 21 is a process executed when the value of the i-th special symbol process flag is “4”. In this process, as shown in FIG. 27, the CPU 103 first determines whether or not the i-th variable display time timer stop flag provided in the flag memory 118 is on (step S291). When the i-th variable display time timer stop flag is off (step S291; No), the timer value is updated by subtracting 1 from the timer value of the i-th variable display time timer (step S292).

  Then, it is determined whether or not the timer value of the updated i-th variable display time timer is “0” (step S293). When the timer value of the i-th variable display time timer becomes “0” (step S293; Yes), the value of the i-th special symbol process flag is a value corresponding to the variable display stop process “5”. To "" (step S294). On the other hand, if it is determined in step S293 that the timer value of the first variable display time timer is other than “0” (step S293; No), the i-th special symbol process flag is not updated. The variable display control process of i is terminated.

  When the first variable display time timer stop flag is turned on in the process of step S291 (step S291; Yes), the processes of steps S292 to S294 are skipped and the i-th variable display control process is performed as it is. Exit. Thus, the countdown of the timer value of the i-th variable display time timer can be stopped until the i-th variable display time timer stop flag is turned on again after being turned on. As a result, the first variable display time can be stopped. While the variable display of the special symbol by the device 41 is continued, the variable display time of the special symbol can be extended.

  The i-th variable display stop process in step S115 of FIG. 21 is a process executed when the value of the i-th special symbol process flag is “5”. In this processing, as shown in FIG. 28, the CPU 103 derives and displays a special symbol fixed symbol by the i-th variable display device 41 or 42 and changes the special symbol by the i-th variable display device 41 or 42. The display is terminated (step S301), and settings are made to send the i-th decorative symbol confirmation command D000 (h) from the main board 11 to the display control board 12 (step S302). Specifically, the control data corresponding to the i-th decorative symbol determination command D00 (h) is set in a predetermined command transmission table, and the i-th decorative symbol determination command D000 (h) is displayed on the display control board. 12 is set to be sendable. The CPU 103 transmits one or more commands set in the command transmission table to the display control board 12 in a subsequent command control process (step S18).

  Subsequently, the CPU 103 determines whether or not the i-th big hit state flag provided in the flag memory 118 is turned on (step S303). When the i-th big hit state flag is off (step S303; No), it is subsequently determined whether or not the probability changing flag provided in the flag memory 118 is on (step S304). When the probability changing flag is off (step S304; No), the process proceeds to step S310.

  On the other hand, when the probability change flag is on (step S304; Yes), it is determined whether or not the probability change end flag is on (step S305). If the probability variation end flag is on (step S305; Yes), the probability variation in progress flag, the probability variation end flag, and the probability variation counter are cleared (step S306), and the process proceeds to step S310.

  If the probability variation end flag is off in step S305 (step S305; No), the count value of the probability variation counter 117 is decremented by 1 (step S307), and the count value of the probability variation counter 117 is “0”. It is determined whether or not (step S308). When the count value of the probability variation counter 117 is not “0” (step S308; No), the process proceeds to step S310.

  On the other hand, when the count value of the probability variation counter 117 is “0” (step S308; Yes), the probability variation flag is cleared (step S309). Thereafter, the CPU 103 updates the value of the i-th special symbol process flag to “0” (step S310).

  Further, when the i-th big hit state flag is on in step S303 (step S303; Yes), the (i + 1) th variable display time timer stop flag provided in the flag memory 118 is set to the on state. After that, the value of the i-th special symbol process flag is updated to “6”, which is a value corresponding to the i-th big winning opening opening pre-processing (step S312).

  The i-th pre-opening pre-opening process in step S116 of FIG. 21 is a process executed when the value of the i-th special symbol process flag is “6”. In this process, the CPU 103 performs setting for starting control for opening the i-th special variable winning ball device 71 or 72 as a big winning opening. Then, control for opening the i-th special variable winning ball device 71 or 72 is started, and the value of the i-th special symbol process flag is a value corresponding to the first big winning opening opening process “7”. Update to

  Further, the i-th big winning opening opening process in step S117 is a process executed when the value of the i-th special symbol process flag is “7”. In this process, the CPU 103 displays a game ball winning detection to the opened i-th special variable winning ball device 71 or 72, a winning ball payout command, a measurement of the opening time, and a display for displaying the round number of the opening cycle. Set control commands. Then, for example, with respect to one big hit, the number of opening times of the i-th special variable winning ball device 71 or 72 is counted, and if the number of opening times reaches, for example, 16 times, a specific gaming state (big hit gaming state) is determined. Assuming that the condition to end is completed, the value of the i-th special symbol process flag is updated to “8”, which is a value corresponding to the jackpot end process. On the other hand, if the number of opening times has not reached 16, the i-th special variable winning ball device 71 or 72 is once closed and then opened again after a predetermined time has elapsed.

  The i-th jackpot end process in step S118 is a process executed when the value of the i-th special symbol process flag is “8”. In this process, as shown in FIG. 29, the CPU 103 first ends the jackpot gaming state by making a setting for sending a jackpot end command E000 (h) to the display control board 12 ( In step S321), the i-th big hit state flag and the (i + 1) -th variable display time timer stop flag provided in the flag memory 118 are cleared and turned off (step S322). Thereby, the countdown of the timer value of the (i + 1) th variable display time timer provided in the flag memory 118 is resumed.

  As described above, the (i + 1) th variable display time timer stop flag is in the ON state from the i-th variable display stop time process in step S115 to the i-th jackpot end process in step S118. The variable display device 42 or 41 of i + 1) derives the display result until the big hit gaming state ends after the big hit symbol is derived and displayed by the i-th variable display device 41 or 42. Display is regulated. As a result, the jackpot symbol is also displayed on the (i + 1) th variable display device 42 or 41 while the jackpot gaming state is based on the fact that the jackpot symbol is derived and displayed on the i-th variable display device 41 or 42. Thus, two big hit gaming states can be prevented from occurring at the same time.

  Subsequently, the CPU 103 determines whether or not the i-th probability change confirmation flag is on (step S323), and when it is on (step S323; Yes), clears the i-th probability change confirmation flag. The probability changing flag is set to the ON state (step S324). Further, a count initial value that is a variable display count initial value during probability variation is set in the probability variation counter 117 (step S325). Here, the initial value of the variable display count during probability change is the initial value (for example, “100”) of the remaining number of special figure games that can be executed in a high probability state.

  On the other hand, when the i-th probability variation confirmation flag is off in the process of step S323 (step S323; No), the probability variation flag is cleared and turned off, and the probability variation counter 117 is cleared and the count value is set to “ It is initialized to “0” (step S326). That is, when the big hit gaming state based on the normal big hit is reached, the high probability state ends and the normal gaming state is restored. Then, the value of the i-th special symbol process flag is updated to “0” (step S327).

  Here, in this embodiment, when the big hit is not accompanied by a probability fluctuation, the probability changing flag is cleared at the end of the big hit, but when the big hit is started, the probability changing flag is always set once. It is cleared, and at the end of the big hit, it is determined whether or not the big hit is accompanied by a probability fluctuation, and if the result of the determination is accompanied, the probability changing flag may be set again.

  Next, the operation in the display control board 12 will be described. FIG. 30 is a flowchart showing a display control main process executed by the display control CPU 202 mounted on the display control board 12. When the display control main process is started, first, a predetermined initialization process is executed to clear the RAM 204, set various initial values, and initialize a 33 millisecond timer for determining the display control activation interval. This is performed (step S31).

  Thereafter, the CPU 202 monitors a timer interrupt flag provided in the flag memory 214, and executes a loop process until the timer interrupt flag is set (step S32; No). In this embodiment, a timer interrupt occurs every 33 milliseconds in the CPU 202, and when this timer interrupt occurs, a predetermined timer interrupt process is executed, so that a timer interrupt flag provided in the flag memory 214 is obtained. Is set.

  In the CPU 202, an interrupt for receiving a display control command from the main board 11 is generated separately from the timer interrupt generated every 33 milliseconds. This interrupt is an interrupt that occurs when the display control INT signal from the main board 11 is turned on. When an interrupt occurs due to the display control INT signal being turned on, the CPU 202 automatically sets the interrupt disabled state. However, if a CPU that does not automatically enter the interrupt disabled state is used, the CPU 202 It is preferable to issue an insertion prohibition instruction (DI instruction).

  When the display control INT signal from the main board 11 is turned on, an interruption occurs in the CPU 202, so that the CPU 202 reads data from an input port assigned to input of display control command data. Then, MODE data and EXT data of a display control command having a 2-byte structure are sequentially received, and the received command is stored in a predetermined reception command buffer. In this way, the display control command transmitted from the main board 11 is stored in the reception command buffer, while the occurrence of the timer interrupt is confirmed in step S32 shown in FIG. When the occurrence of this timer interrupt is confirmed (step S32; Yes), the CPU 202 clears the timer interrupt flag provided in the flag memory 214 and turns it off, and then executes a command analysis process. The received display control command is analyzed (step S33).

  When the command analysis process ends, the CPU 202 executes a counter update process for updating the random R10 counted by the random counter 211 (step S34), and then performs the first decorative symbol display control process process (step S35) and the first process. The decorative pattern display control process process 2 (step S36) is sequentially executed. In the first decorative symbol display control process, a first display control process flag provided in the flag memory 214 in order to control the display operation in the first variable display device 41 in a predetermined order according to the display state. The corresponding process is selected and executed according to the value of. Further, in the second decorative design control process, a process corresponding to the value of the second display control process flag in order to control the display operation in the second variable display device 42 in a predetermined order according to the display state. Is selected and executed. When the first and second decorative symbol display control process processes are completed, the process returns to the process of step S32.

  31 and 32 are flowcharts showing the command analysis processing in step S33. When the command analysis process is started, the CPU 202 first checks whether or not there is a display control command received from the main board 11 (step S601). For example, when it is confirmed that there is a received command because the received command is stored in the received command buffer (step S601; Yes), the received command is read (step S602). It is determined whether or not the middle / right symbol designation commands B0XX (h), B1XX (h), and B2XX (h) (step S603).

  If the received command read in the process of step S602 is the first left / middle / right symbol designation command B0XX (h), B1XX (h) and B2XX (h) (step S603; Yes), the EXT of the command The data is stored in the first left / middle / right symbol storage area for decorative symbols secured in the RAM 204 (step S604), and the first valid flag provided in the flag memory 214 is set to the on state (step S604). Step S605). The EXT data of the first left / middle / right symbol designation commands B0XX (h), B1XX (h), and B2XX (h) is data indicating the symbol number of the decorative symbol. On the other hand, when the received command read in the process of step S602 is not the first left / middle / right symbol designation command B0XX (h), B1XX (h) and B2XX (h) (step S603; No) Then, it is determined whether or not the command is the second left / middle / right symbol designation command C0XX (h), C1XX (h) and C2XX (h) (step S606).

  If the received command read in the process of step S602 is the second left / middle / right symbol designation C0XX (h), C1XX (h), and C2XX (h) (step S606; Yes), the EXT data of the command Are stored in the second left / middle / right symbol storage area for decorative symbols secured in the RAM 204 (step S607), and the second valid flag provided in the flag memory 214 is set to ON (step S607). S608). The EXT data of the second left / middle / right symbol designation commands C0XX (h), C1XX (h) and C2XX (h) is data indicating the symbol number of the decorative symbol. On the other hand, when the received command read in step S602 is not the second left / middle / right symbol designation C0XX (h), C1XX (h) and C2XX (h) (step S606; No), the command It is determined whether or not the command is the first variable display start command 90XX (h) (step S609).

  If the received command read in the process of step S602 is the first variable display start command 90XX (h) (step S609; Yes), the first variable display pattern storage in which the EXT data of the command is secured in the RAM 204 is stored. The area is stored and saved (step S610), and the first variable display start reception flag provided in the flag memory 214 is set to an on state (step S611). On the other hand, when the received command read in step S602 is not the first variable display start command 90XX (h) (step S609; No), the command is the second variable display start command 91XX (h). It is determined whether or not there is (step S612).

  If the received command read in the process of step S602 is the second variable display start command 82XX (h) (step S612; Yes), the second variable display pattern storage in which the EXT data of the command is secured in the RAM 204 is stored. The area is stored and saved (step S613), and the second variable display start reception flag provided in the flag memory 214 is set to the on state (step S614). When the received reception command is another display control command (for example, the first and second decorative symbol determination commands) (step S612; No), the command corresponding to the display control command received by the flag memory 214 The reception flag is set (step S615), and the process returns to the process of step S601.When all reception commands are read in this way (step S601; No), the command analysis process ends.

FIG. 33 is a flowchart showing details of the first and second decorative symbol display control process processes in steps S35 and S36. The contents of the first and second decorative symbol display control process are the same except for the difference between whether the object of processing is for the third variable display device 43 or the fourth variable display device 44. Substantially the same.
Therefore, in the following, description will be made collectively using the variable j (j = 1, 2).
In the jth decorative symbol display control process, the CPU 202 selects one of the seven processes of steps S620 to S626 shown in FIG. 33 based on the value of the jth display control process flag provided in the flag memory 214. Select. Below, each process of step S620-S626 is demonstrated.

  The jth variable display start command reception waiting process in step S620 is a process executed when the value of the jth display control process flag is the initial value “0”. In this process, as shown in FIG. 34, the CPU 202 first determines whether or not the jth variable display start flag provided in the flag memory 214 is set (step S701). That is, in the command analysis process described above, when the jth variable display start command A0XX (h) that can specify the variable display time is read from the reception command buffer, the jth variable display start flag is set.

  When the jth variable display start flag is not set (step S701; No), the jth variable display control start command reception waiting process is ended as it is.

  When the i-th variable display start flag is set in the process of step S701 (step S701; Yes), the value of the j-th display control process flag is a value corresponding to the display control setting process “1”. (Step S702).

  The i-th display control setting process in step S621 is a process executed when the value of the j-th display control process flag is “1”. In this process, the CPU 202 selects and determines a symbol display control pattern corresponding to the variable display pattern saved in the variable display pattern storage area of the RAM 204, and reads it from the symbol display control pattern table 220. Then, the value of the jth display control process flag is updated to “2”, which is a value corresponding to the jth variable display start pre-process.

  The j-th variable display start pre-process in step S622 is a process executed when the value of the j-th display control process flag is “2”. In this process, the CPU 202 sends a command to the GCL 205 and the variable display section of the (j + 2) th (the third variable display device 43 when j is 1 and the fourth variable display device 44 when j is 2). The decorative design is displayed in a manner that gradually accelerates to start variable display of the decorative design. In addition, the count initial value corresponding to the total variable display time corresponding to the variable display pattern is set in the (j + 2) th variable display time timer included in the various timers 215 to start the countdown operation, so that the variable display time Start measuring. Then, the value of the j-th display control process flag is updated to “3”, which is a value corresponding to the i-th variable display process.

  The i-th variable display process in step S623 is a process executed when the value of the j-th display control process flag is “3”. In this processing, first, as shown in FIG. 35, the CPU 202 first determines whether or not the (j + 2) th variable display time timer stop flag provided in the flag memory 214 is on (step S711). ). When the (j + 2) th variable display time timer stop flag is off (step S711; No), the timer value is updated by subtracting 1 from the timer value of the (j + 2) th variable display time timer (step S711). S712).

  Then, it is determined whether or not the timer value of the updated (j + 2) th variable display time timer is “0” (step S713). When the timer value of the (j + 2) th variable display time timer becomes “0” (step S713; Yes), the count initial value determined in advance for the jth monitoring timer included in the various timers 215 (Step S714), the countdown of the j-th monitoring timer is started, and the value of the j-th display control process flag is updated to “4” which is a value corresponding to the j-th decorative symbol stop waiting process. (Step S715). On the other hand, when it is determined in step S713 that the timer value of the third variable display time timer is other than “0” (step S713; No), the jth display control process flag is not updated. The j variable display in-process is terminated.

  When the (j + 2) th variable display time timer stop flag is turned on in the process of step S711 (step S711; Yes), the processes of steps S712 to S715 are skipped and the jth variable display is performed as it is. End the middle process. Thus, the countdown of the timer value of the (j + 2) th variable display time timer can be stopped until the (j + 2) th variable display time timer stop flag is turned on again after being turned on. Similarly to the variable symbol display time of the special symbol by the i-th variable display device 41 or 42, the variable symbol display time by the variable display device 43 or 44 of (j + 2) can be extended. When the count of the (j + 2) th variable display time timer is stopped (step S711; Yes), a step for combining and displaying a message for notifying that to the variable display of the decorative symbol is arranged. May be.

  The jth decorative symbol stop waiting process in step S624 shown in FIG. 33 is a process executed when the value of the jth display control process flag is “4”. In this process, as shown in FIG. 36, the CPU 202 first determines whether or not the i-th decorative symbol determination command D000 (h) transmitted from the main board 11 has been received as a display control command (step S721). ). The j-th decorative symbol determination command D000 (h) is a command that is prepared for transmission in the above-described step S302 and is then transmitted in step S19. When the j-th decorative symbol confirmation command D000 (h) has not been received (step S721; No), it is determined whether or not the j-th monitoring timer has timed out (step S722). S722; No), the j-th decorative symbol stop waiting process is finished as it is.

  On the other hand, when the j-th monitoring timer times out (step S722; Yes), the CPU 202 determines that some abnormality has occurred and displays a predetermined error screen on the (j + 2) -th variable display device 43 or 44. Control is performed (step S723). Thereafter, the process proceeds to step S727.

  When it is determined in step S721 that the j-th decorative symbol confirmation command has been received (step S721; Yes), the CPU 202 performs the decoration being executed by the (j + 2) -th variable display device 43 or 44. The variable display of the symbols is terminated, and the control for stopping and displaying the fixed symbols in each symbol is performed (step S724), and it is determined whether or not the display result of each symbol is a big hit that is the specific display result (step S725). If it is not a big hit (step S725; No), the process proceeds to step S727. If it is a big win (step S725; Yes), the (j + 2) th variable display time timer stop flag provided in the flag memory 214 is turned on. The state is set (step S726). Thereafter, the CPU 202 proceeds to the process of step S728.

  In the process of step S727, the CPU 202 updates the value of the jth display control process flag to “0”, and ends the jth decorative symbol stop waiting process. In step S728, the value of the jth display control process flag is updated to “5”, which is a value corresponding to the jth jackpot display process, and the jth decorative symbol stop waiting process ends.

  The j-th jackpot display process in step S625 of FIG. 33 is a process executed when the value of the j-th display control process flag is “5”. In this process, the CPU 202 controls to display an image corresponding to the big hit gaming state by controlling the (j + 2) th variable display device 43 or 44. For example, by displaying the number of rounds corresponding to a predetermined jackpot round number command sent from the main board 11 on the (j + 2) th variable display device 43 or 44, it is possible to notify the player. . When the round game executed in the big hit gaming state becomes the final round (for example, the 16th round), the value of the jth display control process flag is set to “6”, which is a value corresponding to the jth big hit end display process. Update.

  The j-th jackpot end display process in step S626 is a process executed when the value of the j-th display control process flag is “6”. In this processing, as shown in FIG. 37, the CPU 202 first receives a big hit at the (j + 2) th variable display device 43 or 44 in response to receiving the big hit end command E000 (h) from the main board 11. An effect display for notifying that the gaming state has ended is controlled (step S731). The CPU 202 also provides a (j + 3) variable display time timer stop flag provided in the flag memory 214 (a fourth variable display time timer stop flag when j = 1, and a third variable display time timer stop flag when j = 2. The variable display time timer stop flag) is cleared and turned off (step S732). As a result, the countdown of the timer value of the (j + 3) th variable display time timer provided in the flag memory 214 is resumed. When the effect display for notifying that the big hit gaming state has ended, the value of the jth display control process flag is updated to “0” (step S733).

Subsequently, a display control example for controlling the display operation in each of the variable display devices 41 to 44 will be described.
Here, after the first variable display device 41 starts a special figure game with a display result as a normal big hit, the second variable display device 42 starts a special figure game with a display result as a probable big hit. An example of display control in the case of failure will be described.

  FIG. 38 is a timing chart showing a display operation example in each of the variable display devices 41 to 44 in this case, and FIG. 39 is a diagram showing a variable display mode of special symbols and decorative symbols in each of the variable display devices 41 to 44. is there.

  In this display control example, the variable display pattern # 21 (reach A normal big hit) is selected and determined as the variable display pattern used in the special figure game by the first variable display device 41. The CPU 103 of the main board 11 starts the variable display of the special symbol by the first variable display device 41 and sends the first variable display start command A0XX (h) to the display control board 12 (FIG. 26, FIG. 26). Step S268). At this time, the CPU 103 starts accelerating display by the process a for the special symbols displayed on the left, middle and right variable display portions of the first variable display device 41 according to the selected variable display pattern # 21. Let Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  In response to receiving the first variable display start command A0XX (h) sent from the main board 11 (FIG. 34, step S701; Yes), the CPU 202 of the display control board 12 responds to the GCL 205. The third variable display device 43 starts variable display of decorative symbols by sending a predetermined drawing command or the like (step S622). At this time, the GCL 205 executes image processing in accordance with the drawing command from the CPU 202, and applies the process a to the decorative symbols displayed on the left, middle, and right variable display portions of the third variable display device 43. Start accelerating display. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  Thus, in the first variable display device 41, as shown in FIGS. 39A and 39B, at the timing t10, variable display of the special symbol that has been stopped is started, and the third variable display device 41 is started. In the display device 43, variable display of the decorative symbols that have been stopped is started.

  Thereafter, during the variable display of the special symbol by the first variable display device 41, the game ball wins the second variable winning ball device 62, and the start winning memory number of the second special symbol holding memory 112 is the maximum value. When 4 is reached, a second notification effect end command 9100 (h) is sent to the display control board 12.

  Then, in the processing of steps S131 and S132, it is determined that the display result of the special figure game by the second variable display device 42 is a probable big hit, and is used in the special figure game by the second variable display device 42. As the variable display pattern, variable display pattern # 21 (reach A big hit) is selected and determined.

  The CPU 103 of the main board 11 starts the variable display of the special symbol by the second variable display device 42 according to the variable display pattern # 21 selected and determined, and controls the display of the second variable display start command A1XX (h). Send out to the substrate 12. At this time, the CPU 103 starts the accelerated display by the process a on the special symbols displayed on the left, middle, and right variable display portions of the first variable display device 41 according to the variable display pattern selected and determined. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  In response to receiving the second variable display start command A1XX (h) sent from the main board 11, the CPU 202 of the display control board 12 sends a predetermined drawing command to the GCL 205, etc. In the fourth variable display device 44, a predetermined drawing command is sent to the GCL 205, and the fourth variable display device 44 starts variable display of decorative symbols. At this time, the GCL 205 executes image processing in accordance with a drawing command from the CPU 202, and applies the process a to the decorative symbols displayed on the left, middle, and right variable display portions of the fourth variable display device 44. Start accelerating display. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  Thereby, as shown in FIG. 39C, the second variable display device 42 starts the variable display of the special symbol at the timing t11, and the fourth variable display device 44 displays the variable symbol variable display. Be started. Thereafter, the first variable display device 41 and the third variable display device 43 perform temporary stop display in the order of the left symbol and the right symbol, as shown in FIGS. 39 (D) and (E).

  Then, at timing t12 after the total variable display time T20 from timing t10, the CPU 103 of the main board 11 ends the variable display of the special symbol by the first variable display device 41, and derives and displays the normal jackpot symbol (step). In step S301, the second decorative design determination command D1XX (h) is sent to the display control board 12 (step S302). In addition, the CPU 103 sets the second variable display time timer stop flag to ON, and stops the measurement of the special symbol variable display time by the second variable display device 42.

  On the other hand, at the timing t12, the CPU 202 of the display control board 12 causes the third variable display device 43 to derive and display the normal jackpot symbol and responds to the reception of the second decorative symbol determination command D1XX from the main substrate 11. Thus, the process c is displayed in a completely stopped state (step S724). Further, the CPU 103 sets the fourth variable display time timer stop flag to ON (step S726), and stops the measurement of the decorative symbol variable display time by the fourth variable display device 44.

  As a result, the first variable display device 41 and the third variable display device 43, as shown in FIG. 39 (F), the normal jackpot symbol is confirmed and displayed, and the pachinko gaming machine 1 is shown in FIG. 39 (G). As shown in FIG. Meanwhile, in the second variable display device 42 and the fourth variable display device 44, the countdown of the timer value of the second variable display time timer and the timer value of the fourth variable display time timer is stopped, and the process The constant speed display by b continues to be executed. Further, as shown in FIG. 39G, the third variable display device 44 appropriately displays a display indicating that the measurement of the variation time is stopped (in the drawing, “Paused”).

  Then, at timing t13 when the big hit gaming state ends, the CPU 103 of the main board 11 sends a big hit end command E000 (h) to the display control board 12 (step S321). Further, the CPU 103 clears and turns off the second variable display time timer stop flag (step S322), and restarts the measurement of the special symbol variable display time by the second variable display device.

  On the other hand, the CPU 202 of the display control board 12 clears and turns off the fourth variable display time timer stop flag (step S732), and resumes the measurement of the special symbol variable display time by the fourth variable display device 44.

  Thereafter, the second variable display device 42 and the fourth variable display device 44 perform temporary stop display in the order of the left symbol and the right symbol, as shown in FIGS. 39 (I) and (J). Then, at timing t14, the CPU 103 of the main board 11 ends the variable display of the special symbol by the second variable display device 42, derives and displays the probability variation big winning symbol (step S301), and the second decorative symbol confirmation command. D1XX (h) is sent to the display control board 12 (step S302).

  Further, the CPU 202 of the display control board 12 responds to the fact that the fourth variable display device 44 derives and displays the probable big hit symbol at timing t14 and receives the second decorative symbol determination command D0XX from the main board 11. Thus, the process c is displayed in a completely stopped state (step S724).

  As a result, the second variable display device 42 and the fourth variable display device 44, as shown in FIG. 39 (K), confirm and display the probability variation big hit symbol, and the pachinko gaming machine 1 enters the big hit gaming state. Transition to the probability improvement state after completion.

  As described above, according to this embodiment, the random R1 used for the jackpot determination in the special game in the first variable display device 41 and the special game in the second variable display device 42 are used. The random R1 used for the big hit determination is acquired by the random counter 113 having the configuration shown in FIG. According to the random counter 113 configured as described above, the output data of the counter 1203 is latched by one latch circuit 1205 with respect to the winnings to the first and second ordinary variable winning ball devices 61 and 62, Based on the first and second winning ball detection signals SDA and SDB output from the second winning port switches 70A and 70B, the first and second special figure reservation memories 111 and 112 are appropriately distributed. It is composed. Therefore, the random number value can be appropriately processed with a small amount of hardware.

  Further, for example, when the big hit symbol is derived and displayed on the second variable display device 42 during execution of the variable display of the special symbol by the first variable display device 41, the CPU 103 displays the first variable display time timer. When the jackpot gaming state based on the derivation and display of the jackpot symbol is terminated, the timer value countdown is restarted. In this way, the CPU 103 continues the variable display of the special symbol on the first variable display device 41 until the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the second variable display device 42 is completed. Continue to extend the variable display time. As a result, a jackpot gaming state based on the fact that the first jackpot symbol is derived and displayed on the first variable display device 41, and a jackpot gaming state based on the jackpot symbol being derived and displayed on the second variable display device 42, , Can be prevented from occurring at the same time. For this reason, it is possible to prevent the player from having a strong impact and inciting significant euphoria.

  Further, until the variable display of the special symbol by the second variable display device 42 reaches the big hit state, the variable display of the special symbol by the first variable display device 41 is normally executed. It is difficult for the player to realize that the variable display in the game is a big hit, and it can enhance the interest.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible.

  For example, in the above embodiment, the count clock signals S1 and S2 are signals having the same period and a phase difference of 180 °, but the period and duty of the first and second latch clock signals S1 and S2, The phase is arbitrary.

  In the configuration of FIG. 10, the count value of the counter 1203 is latched by the latch circuit 1205 and then taken into the I / O port of the CPU 103. However, it may be taken directly into the I / O port of the CPU 103. Good.

  In the circuit configuration of FIG. 10, the first and second winning ball detection signals SDA and SDB output from the first and second winning opening switches 70A and 70B, and the starting winning detection signal output from the starting winning detector 1111 are output. The SSN is directly supplied to the CPU 103 and the latch signal generation circuit 1204. In such a configuration, the player does not feel distrust because no change is made to the start winning signal as a trigger for determining whether or not to win. However, with such a configuration, there is a possibility that a “winning” may be erroneously determined when the signal instantaneously becomes an active level due to noise or the like (when a whiskers occur). In order to prevent such a problem, for example, as shown in FIG. 40, a timer circuit 1177 is arranged, and only when the detection signals SDA, SDB, and SSN continue for a certain period, the CPU 103 and the latch signal generation circuit 1204 are provided. A signal may be supplied.

  Specifically, the timer circuit 1177 shown in FIG. 40 includes the first and second winning opening switch 70A or 70B, the first or second winning ball detection signal SDA or SDB from the starting winning detector 1111 and the starting winning detection. The time during which the signal SSN is input is measured using, for example, an arbitrary clock signal from the reference clock signal generation circuit 1201. When the measured time reaches a predetermined time (for example, 3 ms), the first or first time 2 winning ball detection signals SDA and SDB are output to the CPU 103, and a start winning detection signal SSN is output to the CPU 103 and the latch signal generation circuit 1204.

  The timer circuit 1177 is constituted by, for example, an up counter or a down counter, and starts in response to a high level signal being input. The timer circuit 1177 sequentially inputs the reference clock signal generation circuit 1201 while the input is at a high level, and counts up or down the clock signal. When the count value obtained by counting up or down becomes, for example, a value corresponding to 3 ms, the timer circuit 1177 outputs the first or second winning ball detection signals SDA and SDB and the starting winning detection signal SSN. To do.

  Further, for example, when an input signal (which may be any of SDA, SDB, and SSN) is continued for a certain period by the method shown in FIGS. 41 and 42, it may be determined that a regular signal has been input. First, as shown in FIG. 41A, a signal duration counter 1113 for counting the duration of each target signal is arranged in the RAM 102.

  Subsequently, in the switch process (step S11) of the game control interrupt process (timer interrupt process) shown in FIG. 19, if the signal is high level (active level) (step S1001; Yes), the signal duration counter The count value of 1113 is incremented by 1 (step S1002), and if it is a low level (inactive level) (step S1001; No), the count value of the signal duration counter 1113 is reset (step S1003).

  Then, as shown in FIG. 42, in the i-th special symbol process shown in FIG. 21, whether or not the count value of the signal duration counter 1113 for the start winning detector 1111 is 2 or more, for example, Then, it is determined whether or not the start winning detection signal SSN has continued for two interrupt processing periods (4 ms) (step S101). When it is determined that the start winning detection signal SSN is 2 or more, the first and second normal winnings are determined. Which of the variable winning ball devices 61 and 62 has been won may be determined based on the duration of the first and second winning ball detection signals SDA and SDB, and the subsequent processing may be performed.

  In addition, when a situation in which a game ball wins at the first and second winning openings is expected at the same time, for example, as shown in FIG. The output of the gaming ball detection signal may be suppressed, and when the processing for the previously generated gaming ball detection signal is completed, the processing of the subsequent gaming ball detection signal may be made possible by the CPU.

  Further, in the above embodiment, after the big hit symbol is derived and displayed on one of the first and second variable display devices 41 and 42 and the big hit gaming state is started, Until the end, the other variable display device displays the special symbol and the decorative symbol variably at a constant speed. However, the present invention is not limited to this, and during this time, even if the lost symbol is paused and displayed on the other variable display device, a message indicating that it is paused may be further displayed. .

  In the above embodiment, as shown in FIG. 19, one of the first special symbol process and the second special symbol process is executed according to the value of the pointer i in one game control interrupt process. As described above, for example, as shown in FIG. 43, both the first special symbol process 16a and the second special symbol process 16b may be performed in one game control interrupt process. Good. Similarly, both the first normal symbol process 17a and the second normal symbol process 17b may be performed in one game control interrupt process.

  In addition, the arrangement of the first, second, third and fourth variable display devices 41 to 44 is not limited to the arrangement of the above-described embodiment, but depends on the configuration and specifications of the pachinko gaming machine 1. It can be changed arbitrarily. Furthermore, the first, second, third, and fourth variable display devices 41 to 44 do not need to be configured as independent display devices. For example, in the four display areas of one display device, the above-described first display device is provided. Substantially the same display as that of the first, second, third, and fourth variable display devices 41 to 44 may be performed.

  In addition, each of the two display devices may operate as one of the first and second variable display devices 41 and 42 described above so as to be interchangeable. For example, a period in which the pachinko gaming machine 1 is operating with power supply is divided into a first period and a second period, and one of the two display devices is the first variable in the first period. It operates as the display device 41 and the other operates as the second variable display device 42. On the other hand, in the second period, one of the two display devices operates as the second variable display device 42 and the other operates as the first variable display device 41. In this case, the third and fourth variable display devices 43 and 44 may be switched and operated corresponding to the first and second variable display devices 41 and 42.

  Alternatively, of the two display devices, the one in which the condition for starting the special figure game is established first and the special symbol variable display is started may operate as the first variable display device 41 described above. Then, when a condition for starting the special figure game by the other display device on which the special symbol is stopped and displayed during execution of the special figure game is established, the other display device is set to the second variable display described above. The device 42 may be operated.

  Further, the first and second variable display devices 41 and 42 have functions as the third and fourth variable display devices 43 and 44, and the first and second variable display devices 41 and 42 have the above-described third function. And the effect display similar to the 4th variable display apparatuses 43 and 44 may be performed.

  In the above embodiment, the first and second ordinary variable winning ball devices 61 and 62 are described as starting winning ports. However, only one of them is arranged, and one game ball detection signal is turned on / off. , It may be determined which of the ordinary variable winning ball devices has won.

  In the embodiment described above, the first and second special variable winning ball devices 71 and 72 are described as the big winning openings. In other words, the description has been given on the assumption that two winning prize openings are provided corresponding to the two variable display devices. However, the present invention is not limited to this, and for example, one big winning opening corresponding to both the first and second variable display devices 41 and 42 may be provided.

  In addition, the first and second special variable winning ball devices 71 and 72 as the special winning opening are provided corresponding to the first and second variable display devices 41 and 42, respectively, but the present invention is not limited thereto. Instead, the first and second special variable winning ball devices 71 and 72 may be alternately opened for each round in the big hit gaming state. For example, in the odd round, the first special variable winning ball device 71 is opened and the second special variable winning ball device 72 is closed, and in the even round, the first special variable winning ball device 71 is closed. The second special variable winning ball device 72 may be opened.

  In the above-described embodiment, it has been described that the on / off control of the first and second start winning memory indicators 45 and 46 is performed on the main board 11 side. On the other hand, the on / off control of the first and second start winning memory indicators 45 and 46 may be performed on the display control board 12 side. In this case, when the CPU 103 mounted on the main board 11 is changed by adding or subtracting 1 from the number of reserved memories in the first and second special figure reservation memories 111 and 112, A setting is made to transmit a display control command indicating the number of reserved memories corresponding to each of the second special figure reservation memories 111 and 112 to the display control board 12. Then, the CPU 202 mounted on the display control board 12 performs on / off control of the first and second start winning memory display units 45 and 46 according to the number of reserved memories indicated by the display control command from the main board 11. You may make it perform.

  In addition, the first and second start winning memory indicators 45 and 46 have been described as being provided on the upper portions of the first and second variable display devices 41 and 42, but the present invention is not limited thereto. Similar to the first and second start winning memory indicators 45 and 46, the third and third displays that make it possible to specify the start winning memory numbers for the first and second ordinary variable winning ball devices 61 and 62, respectively. The display may be performed in a predetermined display area provided in the four variable display devices 43 and 44. Furthermore, both the display of the start winning memory number on the first and second start winning memory indicators 45 and 46 and the display of the start winning memory number on the third and fourth variable display devices 43 and 44 are both performed. You may do it.

  Furthermore, in the above embodiment, the special symbol derived and displayed on each of the variable display devices 41 to 44 causes the player to shift to the probability improvement state after the big hit gaming state, or to end the probability improvement state. I was informed. However, the present invention is not limited to this, and the occurrence or end of the probability improvement state may be notified by another effect accompanying the variable symbol variable display. In addition, the effect of notifying the occurrence or termination of the probability improvement state may be performed during execution of variable symbol special display, or may be performed after derivation display of a fixed symbol. Further, the effect of notifying the occurrence of the probability improvement state may be performed in the big hit gaming state.

  Moreover, in the said embodiment, although the common table was arrange | positioned for the 1st and 2nd variable display apparatuses 41 and 42, you may arrange | position unique tables to each.

  In the present invention, two or more N variable display devices may be arranged. In that case, a circuit that latches the count value of one counter at different timings may be provided.

  In the above embodiment, the example in which the output of the random counter 113 is used as a random R1 (big hit random number) has been shown, but it is also possible to use it as another random. In this case, the CPU 103 may directly take in the count value of the counter 1203 (or take it in after latching it) triggered by another arbitrary event, and use it in a necessary scene.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a figure which shows the channel | path structure of the winning ball of the pachinko game machine in embodiment of this invention. It is a block diagram which shows the circuit structure etc. of the main board | substrate. It is a figure which shows an example of the content of a display control command. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure for demonstrating the random number used for game control and display control. It is a figure which shows the structural example of the table for jackpot determination. It is a figure which shows the structural example of the table for symbol determination. It is a figure which shows the structural example of the table for variable display pattern determination. It is a circuit block diagram which shows the structural example of a random counter. It is a circuit block diagram which shows the structural example of a latch circuit. It is a timing chart for demonstrating operation | movement of a random counter. It is a block diagram which shows an example of the hardware constitutions for a display. It is a block diagram which shows the structural example of a display control board. It is a figure which shows the example of a random number. It is a figure which shows the structural example of a display control pattern table memory. It is a figure which shows the structural example of a symbol display control pattern table. It is a flowchart which shows a game control main process. It is a flowchart which shows a game control interruption process. It is a flowchart which shows a winning opening switch process. It is a flowchart which shows the detail of a special symbol process process. It is a flowchart which shows the detail of a winning process. It is a flowchart which shows the detail of a big hit determination process. It is a flowchart which shows the detail of a fixed symbol determination process. It is a flowchart which shows the detail of a fixed symbol determination process. It is a flowchart which shows the detail of a variable display pattern setting process. It is a flowchart which shows the detail of a variable display control process. It is a flowchart which shows the detail of a variable display stop time process. It is a flowchart which shows the detail of a jackpot end process. It is a flowchart which shows a display control main process. It is a flowchart which shows the detail of a command analysis process. It is a flowchart which shows the detail of a command analysis process. It is a flowchart which shows the detail of a decoration symbol display control process process. It is a flowchart which shows the detail of a variable display start command reception waiting process. It is a flowchart which shows the detail of the process during variable display. It is a flowchart which shows the detail of a decoration symbol stop waiting process. It is a flowchart which shows the detail of a big hit end display process. It is a figure which shows the process which comprises each display control pattern. Display control when a special figure game whose display result is a promiscuous big hit is started on the second variable display apparatus after a special figure game whose display result is a normal big hit is started on the first variable display apparatus It is a figure which shows an example. FIG. 6 is a circuit block diagram illustrating a configuration example in which processing can be executed only when a detection signal continues for a certain period. It is a figure which shows the structural example which can perform a process only when a detection signal continues for a fixed period. It is a flowchart for demonstrating the process which can perform a process only when a detection signal continues for a fixed period. It is a flowchart which shows the other example of a game control interruption process. It is a block diagram of the modification of the structure of a random counter.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machine 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board 21-24 ... Solenoid
41. First variable display device
42 ... Second variable display device
43 ... Third variable display device
44. Fourth variable display device
45 ... 1st start winning memory indicator
46 ... Second start winning memory indicator
51 ... 1st normal symbol indicator
52 ... Second normal symbol display
61: First ordinary variable winning ball apparatus
62 ... Second ordinary variable winning ball apparatus
70… Each prize opening switch
71: First special variable winning ball apparatus
72 ... Second special variable winning ball apparatus 75A, 75B ... RS flip-flop 100 ... Game control microcomputers 101, 203 ... ROM
102, 204 ... RAM
103, 202 ... CPU
104 ... I / O port 107 ... Switch circuit 108 ... Solenoid circuit 111 ... First special figure reservation memory 112 ... Second special figure reservation memory 113, 211 ... Random counter 114 ... Big hit determination table memory 115 ... For symbol determination Table memory 116 ... Variable display pattern determination table memory 117 ... Probability change counter 118, 214 ... Flag memory 119 ... Variable display time timer 120 ... Normal-time big hit judgment table 121 ... Probability change big hit judgment table 130 ... First normal big hit Symbol determining table 131... First probability variation big hit symbol determining table 132... First left symbol determining table 133... First middle symbol determining table 134... First right symbol determining table 140. Standard jackpot design table 141 ... second probability variation big hit symbol determination table 142 ... second left symbol determination table 143 ... second middle symbol determination table 144 ... second right symbol determination table 150 ... variable at the time of the first normal loss Display pattern determination table 151... First reach loss variable display pattern determination table 152... First big hit variable display pattern determination table 160... Second normal loss variable display pattern determination table 161. Reach-losing variable display pattern determination table 162 ... Second big hit variable display pattern determination table 200 ... Oscillator circuit 201 ... Reset circuit 205 ... GCL
206 ... CGROM
207 ... VRAM
212 ... Display control pattern table memory 215 ... Various timers 220 ... Symbol display control pattern table 1101 ... 1st flow path 1102 ... 2nd flow path 1103 ... 3rd flow path 1111 ... Start winning prize detector
1201 ... Reference clock signal generation circuit 1202 ... Count clock signal generation circuit 1203 ... Counter 1204 ... Latch signal generation circuit 1221 ... Winning order memory

Claims (6)

A plurality of types of identification that can be identified based on the fact that the first start condition is satisfied after the first start condition is satisfied by passing the game medium through the first start area provided in the game area. After a second start condition different from the first start condition is established by passing the game medium through a first variable display means for variably displaying information and a second start area provided in the game area. Second variable display means for variably displaying a plurality of types of identification information each identifiable based on the establishment of the second start condition, and variable identification information by the first variable display means When the display result of the display is a combination of predetermined specific identification information, or when the display result of the variable display of the identification information by the second variable display means is the combination of the specific identification information To the player Te a gaming machine to control the advantageous specific gaming state,
A common flow path through which the game medium that has passed through the first start area and the game medium that has passed through the second start area pass in common;
A first game medium path that guides the game medium that has passed through the first starting area to the common flow path;
A second game medium path that guides the game medium that has passed through the second starting area to the common flow path;
Start detection means arranged in the common flow path, detecting a game medium passing through the common flow path and outputting a start detection signal;
A game medium detecting means which is arranged in at least one of the first game medium path and the second game medium path and detects a game medium and outputs a game medium detection signal;
Numeric data update means for updating and outputting numeric data within a predetermined update range at a predetermined cycle;
Storage means for storing numerical data output from the numerical data update means as a random value when the start detection signal is output from the start detection means;
Game control means for controlling the progress of the game using the variable display of the first and second variable display means based on the numerical data output by the numerical data update means,
The game control means includes
Numerical data reading means for reading numerical data stored in the storage means when the start detection signal is output from the start detection means;
When the start detection signal is output from the start detection means, based on the game medium detection signal, it is determined whether the first start condition or the second start condition is satisfied. Discrimination means;
When the starting condition satisfaction determining means determines that the first start condition is satisfied, by determining whether or not the random value read by the numerical data reading means matches predetermined determination value data, When it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the start condition establishment determination means determines that the second start condition is satisfied, the storage means Display result for determining whether or not the display result in the variable display on the second variable display means is the specific display result by determining whether or not the stored random number value matches the predetermined determination value data A determination means;
When the first start condition is satisfied, variable display of the identification information in the first variable display means is started, and a display result based on the determination result of the display result determination means is derived and displayed, Display control means for starting the variable display of the identification information in the second variable display means and deriving and displaying the display result based on the determination result of the display result determination means when the second start condition is satisfied When,
A gaming machine comprising: The numerical data updating means includes
A reference clock signal output means for outputting a reference clock signal having a reference period;
A clock terminal to which the reference clock signal is input from the reference clock signal output means, an input terminal to which a first signal is input, and the reference clock from which the change state of the first signal is input from the clock terminal A first output terminal that outputs a signal synchronized with a timing that changes at every predetermined period of the signal, and a signal that has the same period and a different phase as the signal output from the first output terminal. Two output terminals, means for connecting the second output terminal and the input terminal, a first clock signal output from the first output terminal, and an output from the second output terminal Clock signal generating means for generating a second clock signal having the same period and a different phase from the first clock signal;
A counter for updating numerical data at a first timing at which the first clock signal generated by the clock signal generating means changes in a predetermined manner;
Including
The storage means
Latch signal output means for outputting the start detection signal as a latch signal in synchronization with a second timing at which the second clock signal generated by the clock signal generation means changes in the predetermined manner;
A latch circuit for latching output data of the numerical data updating means in response to an output signal of the latch signal output means;
including,
The gaming machine according to claim 1.   The game control means controls the storage means to be in a readable state by outputting an output control signal to the storage means before the numerical data reading means reads the random number value from the storage means. And a read control means for controlling the storage means to an unreadable state by stopping output of an output control signal to the storage means after reading a random value from the storage means. The gaming machine according to 1 or 2.   The storage means includes an output control signal reception control means for controlling the output control signal output from the read control means to an unreceivable state when a latch signal is input from the latch signal output means. The gaming machine according to claim 3. The storage means includes latch signal reception control means for controlling the latch signal output from the latch signal output means to be in an unreceivable state when the output control signal is input.
The gaming machine according to claim 3 or 4, characterized in that.   The game medium detection means includes a first game medium detection means arranged in the first game medium path, and a second game medium detection means arranged in the second game medium path. The gaming machine according to any one of claims 1 to 5, wherein:

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