JP4266187B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more specifically, a first variable display means for variably displaying a plurality of types of identification information that can be identified based on the first start condition being satisfied, A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the establishment of a second start condition different from the first start condition, and the identification information by the first variable display means When the display result of the variable display is a combination of predetermined specific identification information, or when the display result of the variable display of the identification information by the second variable display means is the combination of the specific identification information The present invention also relates to a gaming machine that controls a specific gaming state that is advantageous to the player.

  In gaming machines such as pachinko machines, variable display is performed by updating or scrolling predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on the display result.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In this game, the case where the stop symbol form when the display is completely stopped is a predetermined specific display form is determined as “big hit”. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

  The selection and determination of the display pattern variable display mode is based on the detection of the game ball passing through the start winning opening and the random number value (mainly including the big hit random number and other random numbers for determining the figure stop symbol). Based on the extracted random number value, it is determined by determining whether or not to enter the big hit gaming state, the variation mode, and the like. As an example of a random number circuit for enabling such processing, Patent Document 1 discloses a configuration in which a counter is updated by a clock signal and a count value is acquired based on a predetermined timing signal. .

  Also, some pachinko gaming machines have a plurality of start winning openings and a variable display unit corresponding to each starting winning opening, and one clock count circuit and two pieces are provided so as to correspond to this type of gaming machine. Patent Document 2 discloses a circuit including a count value storage circuit and two latch signal output circuits. Further, in a gaming machine having a plurality of start winning openings and a variable display portion corresponding to each start winning opening, in order to prevent a situation where the player's joyfulness is intensified, it is possible that a plurality of variable display portions are simultaneously hit. To prevent the variable display on one variable display unit from winning, or when one variable winning slot is in a specific game state, until the symbol variation of the other variable display device starts Patent Document 3 discloses a method for delaying the above time.

In addition, it is determined that the variable display on one of the variable display devices is winning, or it is determined that one variable winning opening is in a specific gaming state and the variable display on the other variable display device is winning. In such a case, Patent Document 4 discloses that the start of the variable display is delayed until the specific gaming state of one of the variable winning awards ends.
JP 7-124296 A JP 2003-190483 A JP 2001-62080 A JP 2001-62081 A

When the random number circuit disclosed in Patent Document 1 is simply used in a pachinko gaming machine having a configuration having a plurality of start winning openings and a variable display unit corresponding to each starting winning opening, Depending on the winning timing, there is a possibility that the count value of the counter being updated is acquired or the same count value (random number value) is acquired for a plurality of variable display units.
Further, in the configuration of the random number circuit disclosed in Patent Document 2, since the output value of the common clock count circuit is latched by the two count value storage circuits, the same value may be obtained depending on the timing of winning to a plurality of start winning ports. There is a risk that the jackpot will be synchronized or the display will be synchronized.

  In addition, in the gaming machine disclosed in Patent Document 3, when it is determined that the variable display on one variable display unit is winning, the time until the symbol variation of the other variable display device is started is delayed. As a result, the player realizes that the variable display on one of the variable display units is hit. In addition, in the gaming machine disclosed in Patent Document 4, the variable display on one variable display device and the variable display on the other variable display device are changed by delaying the start of variable display on the other variable display device. , The player realizes that both are successful. As a result, in the gaming machines described in Patent Documents 3 and 4, there is a risk that the interest will be reduced. Further, although one circuit is used as a random number circuit for a plurality of variable display devices, there is a possibility that the big hit random number is synchronized because nothing is devised.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine including a random number circuit capable of asynchronously outputting a plurality of random numbers for variable display areas.
Another aspect of the present invention provides a gaming machine including a random number circuit capable of making a random number update timing and a latch (memory) timing different from each other in a plurality of random display circuits for variable display areas. Objective.
It is another object of the present invention to provide a gaming machine that is less likely to be perceived by the player as to whether or not the game result is a big hit.

In order to achieve the above object, a gaming machine according to claim 1 of the present application,
The first start condition is satisfied after the first start condition (for example, winning to the first ordinary variable winning ball device 61) is satisfied (for example, random R1 in the first special figure reservation memory 111) A first variable display means (for example, the first variable display device 41) that variably displays a plurality of types of identification information (for example, special symbols) each identifiable based on the movement to the first entry). The second start condition is satisfied after the second start condition (for example, winning to the second ordinary variable winning ball device 62) different from the first start condition is satisfied (for example, the second start condition) Based on the movement of the random R1 to the first entry in the special figure holding memory 112, a second variable display means (for example, a variable display means for variably displaying each of a plurality of types of identification information (for example, special symbols) identifiable) The second variable display device 42) When the display result of the variable display of the identification information by the first variable display means becomes a predetermined combination of specific identification information (for example, the same symbol is aligned), or the second variable When the display result of the variable display of the identification information by the display means becomes a combination of the specific identification information (for example, the same symbol is prepared), the specific gaming state (for example, the big hit gaming state) advantageous to the player is obtained. A gaming machine to control (for example, a pachinko gaming machine 1),
Random number generating means (for example, a random counter 113) for generating a random number based on the establishment of the first start condition and the second start condition,
Game control means (for example, a game control micro) that controls the progress of the game using the variable display of the first and second variable display means based on the random number value (for example, random R1) generated by the random number generation means. A computer 100, in particular a CPU 103);
With
The random number generation means divides the reference clock signal with reference clock signal generation means (for example, a frequency dividing circuit 1201 and a reference clock signal generation circuit 1211) for generating a reference clock signal (for example, a reference clock signal S0). Generating a first count clock signal (for example, count clock signal S1) and a second count clock signal (for example, count clock signal S2) having a phase opposite to that of the first count clock signal. Means (for example, count clock signal generation circuit 1202), numerical data updating means (for example, counter 1203) for updating and outputting numerical data in a predetermined cycle in response to the first count clock signal, In response to the latch signal (for example, latch signal SLA), the numerical data updating means In response to a first random value storage means (for example, a first random value storage circuit 1205A) that stores the output numerical data as a random number value, and a second latch signal (for example, a latch signal SLB), Second random value storage means (for example, second random value storage circuit 1205B) for storing numerical data output from the numerical data update means as a random value, and frequency dividing the second count clock signal S2. the first of the first latch timing signal indicating the output timing of the latch signal (e.g., latch clock (timing) signal S2A) in the first latch timing signal and antiphase, the output of the second latch signal Latch timing signal generating means for generating a second latch timing signal (for example, latch clock (timing) signal S2B) indicating timing For example, a frequency dividing circuit 1211) and a first start signal (for example, a first start winning signal SSA) input based on the establishment of the first start condition are generated by the latch timing signal generating means. In synchronization with the generated first latch timing signal (for example, the latch clock signal S2A), the first random value storage means (for example, the first latch signal SLA) is used as the first latch signal (for example, the latch signal SLA). First latch signal output means (for example, first latch signal output circuit 1204A) to be output to the random number storage circuit 1205A) and a second start input based on the fact that the second start condition is satisfied A signal (for example, the second start winning signal SSB) is transmitted to the second latch timing signal (for example, latch clock signal generated by the latch timing signal generating means). In synchronization with the clock signal S2B), the second latch signal (for example, the second latch signal output circuit 1204B) is used as the second latch signal (for example, the second latch signal output circuit 1204B). Second latch signal output means (for example, a second latch signal output circuit 1204B) for outputting, and the latch timing signal generation means includes the first latch timing signal (for example, latch clock signal S2A). The second latch timing signal (for example, the latch clock signal S2B) and each period (one numerical data) from when the numerical data updating means (for example, the counter 1203) updates the numerical data to the next update. Only one of the latch timing signals (for example, latch clock signals S2A and S2B) As people only) is output, respectively, periodically output,
The game control means (for example, the game control microcomputer 100) stores the random number value stored in the first random value storage means (for example, the first random value storage circuit 1205A) and the second random value storage. Storage means (for example, the random number value stored in the means (for example, the second random value storage circuit 1205B) is read from the first random value storage means and the second random value storage means, respectively, and stored. , A first special figure reservation memory 111 and a second special figure reservation memory 112) in the RAM 102,
Based on the establishment of the first start condition, the random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. In the variable display by the first variable display means, it is determined whether or not the value data (for example, the big hit data registered in the big hit determination table) matches (for example, the first big hit determination process). Whether or not the display result is a specific display result is determined, and based on the establishment of the second start condition, the second start condition that is triggered by the second start condition is generated. Determining whether or not the random number value stored in the storage means matches predetermined determination value data (for example, data for jackpot registered in the jackpot determination table) (for example, second jackpot determination) Processing) A display result determining means for determining whether a specific display results display result in the variable display of the variable display means (e.g., CPU 103, jackpot determining table memory 114),
Based on the determination result of the display result determining means, the variable from the start of variable display of the identification information to the first variable display means and the second variable display means until the display result is derived and displayed. Variable display data selection for selecting variable display data indicating display time (for example, total variable display time T0 to T23) from a plurality of predetermined variable display data (for example, variable display patterns # 1 to # 24). Means (for example, CPU 103, variable display pattern determination table memory 116 (150 to 152, 160 to 162), first variable display pattern setting process, second variable display pattern setting process);
Variable display time measuring means for measuring a variable display time from the start of variable display of the identification information in each of the first variable display means and the second variable display means until the display result is derived and displayed ( For example, the CPU 103, the variable display time timer 119, the process of step S292 in the first variable display control process, the process of step S492 in the second variable display control process),
Measurement determining means for determining whether or not the variable display time indicated by the variable display data selected by the variable display data selecting means has passed by measurement by the variable display time measuring means (for example, CPU 103, variable display time timer) 119, the process of step S293 in the first variable display control process, the process of step S493 in the second variable display control process),
When the first start condition is satisfied, variable display by the first variable display means is started, and when the measurement determination means determines that the variable display time has elapsed, the display result determination means When the determined display result is derived, variable display by the second variable display means is started by the establishment of the second start condition, and it is determined that the variable display time has elapsed by the measurement determination means Derived display control means for deriving the display result determined by the display result determining means (for example, CPU 103, first variable display stop process (especially step S301) and second variable display stop process (particularly step S501)), and
The variable display time measuring means derives and displays the specific display result (for example, big hit display result; display with specific symbols) on the first variable display means (for example, the first variable display device 41). For example, when the variable display of the identification information is executed on the second variable display means (for example, the second variable display device 42) in step S301), the first variable display means specifies At the first time point when the specific gaming state based on the display result being derived and displayed (for example, when the second variable display time timer stop flag is set in step S311 of the first variable display stop time process). The measurement of the variable display time in the second variable display unit is interrupted (set of the second variable display time timer stop flag in step S311 of the first variable display stop process, and 2), the specific gaming state (for example, the big hit state) based on the fact that the specific display result is derived and displayed by the first variable display means is completed. The variable display time is measured at the second time point (for example, when the second variable display time timer stop flag is cleared in step S322 of the first jackpot end process) (for example, the step in the second variable display control process) A measurement interruption resumption means (for example, the CPU 103), which restarts (for example, the resumption of the process of step S492 by determining No in step S491 of the second variable display control process).
It is characterized by that.

In order to achieve the above object, a gaming machine according to claim 2 of the present application,
In a game area (for example, game board 2) where a game medium (for example, game ball) falls, the first start condition is established by detecting the game medium, and the first start signal (for example, first Of the first start condition is output to the first latch signal output means (for example, the first latch signal output circuit 1204A) (for example, the first ordinary variable winning ball apparatus 61). A first prize opening switch 70A) disposed in
In a game area (for example, game board 2) in which a game medium (for example, a game ball) falls, the second start condition is established by detecting the game medium, and the second start signal (for example, second) Start detection signal SSB) is output to the second latch signal output means (for example, second latch signal output circuit 1204B), second start condition establishment detection means (for example, second ordinary variable winning ball device 62). A second prize opening switch 70B) disposed in the
It is characterized by providing.

In order to achieve the above object, in the gaming machine according to claim 3 of the present application,
The random number generation means measures the duration of the first start signal, and when it continues for a certain period of time, a first time count means for supplying the first start signal to the first latch signal output circuit ( For example, a timer 1177) and a second time measuring means for measuring the duration of the second start signal and supplying the second start signal to the second latch signal output circuit when it continues for a certain period of time. (For example, timer 1177).

In order to achieve the above object, in the gaming machine according to claim 4 of the present application,
The game control means includes timer interrupt processing execution means (for example, CPU 103) for executing timer interrupt processing (for example, game control interrupt processing) in response to an interrupt request signal input periodically. The storage means (for example, the CPU 103) is configured such that the first timer interrupt process is executed by the timer interrupt process executing means (for example, while the game control interrupt process is repeated for a plurality of times). Based on the fact that the first start signal (for example, the first start winning signal SSA) is continuously input from the start signal output means (for example, the first start port switch 70A) (for example, in step S101A). Based on the determination that the value of the first start winning counter 1113A is 2 or more), the first random number storage means (for example, the first random number storage circuit 1205A) A numerical value is read (for example, step S204 in the first winning process), and a second starting signal (for example, a starting winning signal SSB) is output from the second starting signal output means (for example, the second starting port switch 70B). Based on the continuous input (for example, based on the determination that the value of the second start winning counter 1113B is 2 or more in step S121A in FIG. 58B), the second The second random value is read from the random value storage means (for example, step S404 in the second winning process).

In order to achieve the above object, in the gaming machine according to claim 5 of the present application,
In the game control means, the display result determining means (for example, the CPU 103, the jackpot determination table memory 114, the first and second jackpot determination processing) is the first random number storage means (for example, the first random value storage means). Before reading a random number value from the numerical value storage means 1205A), a first output control signal (for example, a read control signal SRCA) is output to the first random number value storage means to read out the first random number value storage means. The display result determining means reads out the random number value from the first random number value storing means, and then stops outputting the first output control signal to the first random number value storing means. The first random number storage unit is controlled to be unreadable, and the display result determination unit reads out the random number value from the second random value storage unit (for example, the first random value storage unit 1205A). , The second random value storage means A second output control signal (for example, a read control signal SRCB) is output to control the second random number value storage means to a readable state, and the display result determining means is disturbed from the second random number value storage means. Read control means for stopping the output of the second output control signal to the second random number value storage means and controlling the second random number value storage means to an unreadable state after reading the numerical value.

In order to achieve the above object, in the gaming machine according to claim 6 of the present application,
The first random value storage means (for example, the first random value storage means 1205A) outputs the first random number output from the read control means when a latch signal is input from the first latch signal output means. First output control signal reception control means (e.g., logic gates 1301 to 1304) for controlling the output control signal to be in an unreceivable state, and the second random number value storage means includes the second latch signal. When a latch signal is input from the output means, second output control signal reception control means (for example, a logic gate 1301) that controls the second output control signal output from the read control means to be in an unreceivable state. ~ 1304).

In order to achieve the above object, in the gaming machine according to claim 7 of the present application,
The first random value storage means controls the latch signal output from the first latch signal output means to be in an unreceivable state when the first output control signal is input from the read control means. First latch signal reception control means (for example, logic gates 1301-1304),
The second random number storage means controls the latch signal output from the second latch signal output means to be in an unreceivable state when the second output control signal is input from the read control means. Second latch signal reception control means (for example, logic gates 1301 to 1304).

In order to achieve the above object, in the gaming machine according to claim 8 of the present application,
When the derivation display control means interrupts the time measurement by the variable display time measurement means, a means for notifying that effect (for example, direct notification by displaying “time stop” on the variable display device) , Indirect notification by displaying the stopped losing symbol).

  The inventions according to claims 1 to 8 of the present application have the following effects.

According to the gaming apparatus of the first aspect, it is possible to extract random numbers for a plurality of variable display means by using one numerical data update means, and the circuit efficiency is good. In addition, since the timing for latching the numerical data is surely shifted between the first and second random value storage means, there is no possibility that both the random value storage means store one numerical data in common. Further, when the variable display of the identification information by the first variable display device is started, the first variable display device performs the variable display until the variable display by the second variable display device becomes a big hit state. Therefore, until the display result of the variable display of the first variable display device actually becomes the specific display result, the player is not realized to enter the specific game state, and the interest is not impaired. In addition, the game executed by the first variable display device and the second variable display device are not in the special game state at the same time, and the gambling feeling is not raised.

  According to the gaming apparatus of the second aspect, the first start signal is directly supplied from the first start condition establishment detection means to the first latch signal output means, and the second start condition establishment detection means supplies the second The second start signal is directly supplied to the latch signal output means, and no artificial processing is applied from the detection of the start condition to the input of the start signal to the latch signal output means of the start signal. Therefore, no distrust is given to the player.

  According to the configuration of claim 3, the random number generation unit does not directly output the start signal input from the start signal output unit to the latch signal output unit, but instead calculates the input time of the start signal. Measurement is performed by the timer means, and when the measurement time reaches a preset time, the start signal is output to the latch signal output means. Therefore, it is possible to prevent the latch signal output means from erroneously outputting a latch signal to the random value storage means due to the influence of noise or the like.

  According to the configuration of claim 4, since the random number value is read when the first or second start signal continues for a predetermined number of timer interruption processes, the interruption cycle measured by the timer means is It can be shortened, and it can be prevented that the random value is not stored in the first or second random value storage means.

  According to the configuration of claim 5, the game control means can make the random value storage means readable only when the display result determination means reads the random value, so that the random value Acquisition can be performed reliably and stably.

  According to the configuration of claim 6, when the random number value stored in the random value storage unit is updated, the random number generation unit is configured to change the random number value from the random value storage unit by the display result determination unit. Can be prevented from being read out, the random number value can be updated reliably and stably.

  According to the configuration of claim 7, the random number generation unit stores the random number value stored in the random value storage unit when the display result determination unit reads the random value from the random number storage unit. Therefore, it is possible to reliably and stably acquire a random value.

  According to the configuration of the eighth aspect, since the fact is notified while the measurement of the elapsed time is stopped, no distrust is given to the player.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being aligned. And is that state).

The gaming machine in the present embodiment is a gaming machine that performs a special-purpose game on an image display device such as an LCD, and a card reader (CR: Card) that lends a ball using a prepaid card.
Reader) pachinko machines and slot machines equipped with LCD.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. The first variable display device 41 that variably displays the first special symbol as identifiable identification information and the second special symbol are variably displayed at approximately the center position of the game area. A second variable display device 42 is provided. In addition, below the first variable display device 41 and the second variable display device 42, a third decorative display that can perform variable display of a first decorative design different from the first special design, respectively. A variable display device 43 and a fourth variable display device 44 capable of performing variable display of a second decorative design different from the second special design are provided.

  On the lower side of the third variable display device 43 and the fourth variable display device 44, a first ordinary variable winning ball device (start winning port) 61 and a second ordinary variable winning ball device 62 are arranged, respectively. Has been. Below the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62, a first special variable winning ball device (large winning opening) 71 and a second special variable winning ball device ( A grand prize award) 72 is provided. In addition, a first normal symbol display 51 and a second normal symbol display 52 are provided below the first special variable winning ball device 71 and the second special variable winning ball device 72, respectively. ing.

  The first and second variable display devices 41 and 42 are composed of 7-segment LEDs and the like. In the first variable display device 41, a game ball wins the first ordinary variable winning ball device 61. However, in the second variable display device 42, a variable display game (special game) in which a game ball winning in the second ordinary variable winning ball device 62 becomes a variable display execution condition (starting condition). ), Display symbols that are composed of numbers, characters, and symbols, each functioning as a plurality of types of identification information that can be identified, are variably displayed in a plurality of variable display areas. In this embodiment, three variable display portions are respectively arranged on the first variable display device 41 and the second variable display device 42, and in each variable display portion, left, middle, and right Special symbols shall be variably displayed.

  In a special game played by the first variable display device 41 or the second variable display device 42, after a specific time has elapsed after starting the variable symbol variable display, the special symbol display results are derived in a predetermined order. Display and stop display the finalized symbol (final stop symbol). And when the combination of a fixed symbol becomes a predetermined specific display result (a big hit combination), this pachinko gaming machine 1 becomes a specific gaming state (also called a big hit gaming state). In the big hit gaming state, the first special variable winning ball device 71 and the second special variable winning ball device 72 generate a predetermined number (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls. The game ball that falls on the surface of the game board 2 is received. The opening cycle can be repeated up to a predetermined upper limit number (for example, 16 times).

  In this embodiment, the first left symbol variably displayed as a special symbol on the left variable display portion, the first middle symbol variably displayed as a special symbol on the middle variable display portion, and the special symbol on the right variable display portion 1st right symbol variably displayed, 2nd left symbol variably displayed as a special symbol on the left variable display portion, 2nd middle symbol variably displayed as a special symbol on the middle variable display portion, right variable display portion The second right symbols displayed as special symbols are 9 symbols, and symbols “1” to “9” are assigned to the symbols. For example, in each of the left, middle, and right variable display sections, when variable display of a special symbol is started during a special symbol game, an updated display is performed from a special symbol with a smaller symbol number to a special symbol with a larger symbol number. When the special symbol with “9” is displayed, the special symbol with the symbol number “1” is displayed next.

  In addition, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is a probability variable jackpot symbol. That is, in the special game by the first variable display device 41 or the second variable display device 42, after the variable symbol display is started, the same special symbol is displayed on the left, middle and right variable display units. When it is derived and displayed as a display result and confirmed, the pachinko gaming machine 1 enters a big hit gaming state. Also, in the special game by the first variable display device 41 or the second variable display device 42, after the variable display of the special symbol is started, the same probability variation big hit symbol is displayed on each of the left, middle and right variable display units. Is displayed and confirmed as a display result, the pachinko gaming machine 1 enters the special game state (probability improvement state) following the end of the big hit game state, and thereafter, the display result in the special game is displayed until a predetermined condition is satisfied. The probability of a big hit combination is improved. In the probability improvement state, the opening time of the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 is longer than that in the normal gaming state, and the number of times of opening is higher than that in the normal gaming state. It becomes an advantageous state for a player different from the big hit gaming state, such as increasing. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The third and fourth variable display devices 43 and 44 are composed of, for example, an LCD or the like, and three variable display portions are arranged respectively. In each variable display area of the third variable display device 43, left, middle, and right decorative symbols are variably displayed. The left, middle, and right decorative symbols are displayed on the left and middle of the first variable display device 41, respectively. It corresponds to the special symbols that are variably displayed in the middle and right variable display areas. The left, middle, and right decorative symbols are also variably displayed in the variable display areas of the fourth variable display device 44, and the left, middle, and right decorative symbols are displayed on the second variable display device 42. It corresponds to each special symbol variably displayed in the left, middle and right variable display areas.

  The 1st normal symbol display 51 and the 2nd normal symbol display 52 are provided with a light emitting diode (LED) etc., and are provided with the 1st passage gate and the 2nd passage gate which were provided in the game field. Lighting, blinking, coloring, and the like are controlled in a normal game where the starting condition is that each game ball passes through. When display is performed with a predetermined winning pattern in the normal game, the display result in the normal game is “winning”, and the first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 are configured. The movable wing piece of the electric tulip is controlled to tilt until a predetermined time elapses.

  The first ordinary variable winning ball device 61 and the second ordinary variable winning ball device 62 are tilted (enlarged and opened) by the solenoid 21 (FIG. 2) and the solenoid 22 (FIG. 2), respectively. A tulip-shaped accessory (ordinary electric accessory) having a pair of movable blades controlled to move between positions is configured. The variable display of the special symbol based on the winning of the game ball on the first ordinary variable winning ball device 61 and the variable display of the special symbol based on the winning of the game ball on the second ordinary variable winning ball device 62 are a predetermined number of times. The first special figure reservation memory 111 (FIG. 4) and the second special figure reservation memory 112 (FIG. 4), which will be described later, are stored up to (in this embodiment, four times). Here, two normal symbol displays are provided and two ordinary variable winning ball devices corresponding to these are provided. However, as one normal symbol display and one ordinary variable winning ball device, For example, the normal variable winning ball apparatus may be a start winning opening in which a non-tulip entrance does not open.

  The first special variable winning ball device 71 and the second special variable winning ball device 72 have opening / closing plates for opening and closing the winning area by the solenoid 23 (FIG. 2) and the solenoid 24 (FIG. 2), respectively. Prepare. The opening / closing plate is normally closed, and based on the winning of the game ball to the first ordinary variable winning ball device 61, the special game by the first variable display device 41 and the second ordinary variable winning ball device 62. As a result of the special game played by the second variable display device 42 based on the winning of the game ball to the game, when the big hit gaming state is achieved, the solenoid 23 or the solenoid 24 sets the winning area for a predetermined period (for example, 29 Second) or a predetermined number (for example, 10) of winning balls is set to be in a state of being opened (opening cycle), and a game ball falling in the game area is received during the opening. The opening cycle can be repeated up to 16 times, for example. The game balls that have won the first special variable winning ball device 71 or the second special variable winning ball device 72 are detected by a predetermined detection unit. In response to the detection of the winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (not shown).

  A first start prize memory display 45 and a second start prize memory display 46 are provided above the first variable display device 41 and the second variable display device 42, respectively. The first and second start winning memory indicators 45 and 46 are constituted by LEDs, for example. The first start winning memory display 45 is based on the stored contents of the first special figure holding memory 111 (FIG. 4), and the first variable display is performed when a game ball wins the first ordinary variable winning ball device 61. Although the start condition for executing the special figure game by the device 41 is established, the start prize for starting the variable display is not established due to the reason that the previous special figure game is being executed, etc. The number of memories (the number of reserved memories) is displayed. For example, in the first start winning memory display 45, a number of LEDs corresponding to the number of reserved memories of the special figure game by the first variable display device 41 are turned on. Further, the second start winning memory display 46 displays the second variable when the game ball wins the second ordinary variable winning ball device 62 based on the stored contents of the second special figure holding memory 112 (FIG. 4). Start where the start condition for executing the special display game by the display device 42 is established, but the start condition for starting the variable display is not satisfied due to the reason that the previous special figure game is being executed, etc. The number of winning memories (the number of reserved memories) is displayed. For example, in the second start winning memory display 46, the LED corresponding to the number of reserved games stored in the special figure game by the second variable display device 42 is turned on.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or blinks and speakers 8L and 8R that generate sound effects.

  The pachinko gaming machine 1 is mounted with a main board 11 and a display control board 12 as shown in FIG. The main board 11 and the display control board 12 are arranged at appropriate positions on the back surface of the pachinko gaming machine 1, and, for example, eight signal lines of display control signals CD0 to CD7 are wired between the two boards. Further, a signal line for a display control INT signal for transmitting / receiving a strobe signal is also wired between the main board 11 and the display control board 12. In addition, various control boards such as a power supply board, a sound control board, a lamp control board, a payout control board, and an information terminal board are arranged on the back surface of the pachinko gaming machine 1. The display control board 12 may constitute one board together with the voice control board, the lamp control board, etc., or may be provided independently of these boards.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function for setting random numbers used in a special game, a function for inputting a signal from a switch or the like arranged at a predetermined position, and a sub-side control comprising a display control board 12 and a payout control board. Each board has a function of outputting and transmitting a control command as an example of command information as a control signal, and a function of outputting various kinds of information to a hall management computer. The control command transmitted from the main board 11 to the display control board 12 is, for example, a display control command transmitted as an electrical signal using the signal lines of the display control signals CD0 to CD7.

  FIG. 3 is an explanatory diagram showing an example of the contents of a display control command sent from the main board 11 to the display control board 12 used in this embodiment. The display control command is composed of 2 bytes, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit of MODE data is always “1”, and the first bit of EXT data is “0”. The command form shown in FIG. 3 is an example, and other command forms may be used. In this example, one control command is composed of two control signals. However, the number of control signals constituting one control command may be one or a plurality of three or more. May be.

  In the example shown in FIG. 3, the command A0XX (h) is a variable display start command for instructing the start of variable display of decorative symbols by the third variable display device 43, and the command A1XX (h) is a fourth variable. This is a variable display start command for instructing the display device 44 to start variable display of decorative symbols. In the following, it is assumed that XX (h) is an unspecified hexadecimal number, and is a value that is arbitrarily set according to the instruction content by the display control command. On the display control board 12 side, it is possible to specify a variable display device that performs variable display of decorative symbols corresponding to the MODE data included in the variable display start command. Also, decorative symbols corresponding to the EXT data can be specified. The total variable display time, the determination result of whether or not the display result of the variable display becomes the specific display result, the determination result of whether or not to reach, and the like can be specified.

  The commands B0XX (h), B1XX (h), and B2XX (h) are symbol designation commands for designating the left / middle / right fixed symbols of the decorative symbols variably displayed on the third variable display device 43. C0XX (h), C1XX (h), and C2XX (h) are symbol designation commands for designating the left / middle / right determined symbols of the decorative symbols variably displayed on the fourth variable display device 44. In each symbol designating command, the symbol numbers of the first and second decorative symbols are set in XX (h). The command D000 (h) is a decoration design confirmation command for instructing stop of variable display of the first decorative design, and the command D100 (h) is a design for instructing stop of variable display of the second decorative design. This is a symbol confirmation command. The command D000 (h) is a jackpot end command for instructing the end of the jackpot gaming state.

  Other display control commands include a jackpot start command indicating that the jackpot gaming state is started, a probability change start command indicating that the probability variation control is started when the jackpot gaming state is ended, and when the jackpot gaming state is ended. In addition, a time-short start command indicating that the time-short control is started, a probability change end command indicating that the time-varying control is ended, a time-short end command indicating that the time-short control is ended may be prepared.

  As shown in FIG. 2, the main board 11 has first and second ordinary variable winning ball devices 61 and 62 that are start winning ports, and first and second special variable winning ball devices 71 that are large winning ports. In addition, wiring from each winning opening switch 70 for detecting a winning of a game ball to 72 and other winning openings is also connected. Further, on the main board 11, the movable wing piece movement control in the first and second ordinary variable winning ball devices 61 and 62 and the opening / closing control in the first and second special variable winning ball devices 71 and 72 are provided. Wirings to solenoids 21, 22, 23 and 24 for performing the above are connected.

The main board 11 is configured by mounting a game control microcomputer 100, a switch circuit 107, a solenoid circuit 108, and the like. The game control microcomputer 100 is, for example, a one-chip microcomputer, and a ROM (Read
CPU (Central Memory) 101, a random access memory (RAM) 102 used as a work memory, and a CPU (Central
Processing Unit) 103 and I / O (Input / Output) port 104 are included.

  Further, as shown in FIG. 4, the game control microcomputer 100 includes a first special figure holding memory 111, a second special figure holding memory 112, a random counter 113, a jackpot determination table memory 114, A symbol determination table memory 115, a variable display pattern determination table memory 116, a probability variation counter 117, a flag memory 118, and a variable display time timer 119 are provided.

  The first special figure holding memory 111 has established a condition (starting condition) for a game ball to win the first ordinary variable winning ball apparatus 61 and execute a special symbol variable display (special game). This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as executing the previous variable display. The second special figure holding memory 112 is a memory for storing a holding state in which the start condition is satisfied when the game ball wins the second ordinary variable winning ball apparatus 62 but the start condition is not satisfied. .

  Each of the first special figure reservation memory 111 and the second special figure reservation memory 112 is provided with four entries and a reading area. In each entry of the first special figure holding memory 111, a holding number and a random value (random R1 value to be described later) extracted by the winning order in the winning order to the first ordinary variable winning ball apparatus 61 are stored in the second order. Each entry in the special figure holding memory 112 stores a holding number and a random value extracted by the winning order in association with the second ordinary variable winning ball apparatus 62 in association with each other. Each time the variable display of the variable display of special symbols and decorative symbols ends or the big hit gaming state ends, the variable display start condition based on the highest level information is established, and the highest level information is displayed. Based on the variable display is executed. At this time, the second and lower registration information is moved up by one place. In addition, when a game ball is newly won in the first ordinary variable winning ball device 61 or the second ordinary variable winning ball device 62 during the variable display of special symbols and decorative symbols, the random value resulting from the winning is the highest. Registered in the upper empty entry.

The game control microcomputer 100 generates random numbers R1 to R5 which are random numbers for determination and display used for game control as shown in FIG.
Among these, the random R1 is generated by the random counter 113 shown in FIG. 4 and is a big hit determination random number that determines whether or not the pachinko gaming machine 1 is brought into a specific gaming state by generating a big hit, It takes a value in the range of “0” to “65535”. The configuration and operation of the random counter 113 will be described later with reference to FIGS.

  The random numbers R2 to R5 are generated when the CPU 103 executes random number software. Random R2 is a reach determination random number that determines whether or not to reach when lost, and takes a value in the range of “0” to “1530”. Random R3 is a display random number for determining a variable display pattern used for variable display of the special symbol, and takes a value in the range of “0” to “149”.

  Random R4-1 is a random number that determines a fixed symbol of the special symbol at the time of big hit and a fixed symbol of the left symbol at the time of losing, and takes a value in the range of “0” to “106”. Random R4-2 is a random number that determines a fixed symbol in the middle symbol at the time of losing, and takes a value in the range of “0” to “162”. Random R4-3 is a random number that determines a definite symbol in the right symbol at the time of normal losing without reach, and takes a value in the range of “0” to “72”. Random R5 is a random number for determining whether or not to perform probability variation control (probability variation control) for shifting to the probability improvement state after putting the pachinko gaming machine 1 into the big hit gaming state, and is “0” to “9”. Takes a value in the range.

  In this embodiment, the random R1 to R5 are commonly used for both the special game by the first variable display device 41 and the special game by the second variable display device 42. Note that it is possible to use separate random numbers for the special game by the first variable display device 41 and the special game by the second variable display device 42, but in this way, a random number is generated. As the circuit configuration increases, the number of random numbers counted by the random counter 113 increases, and the processing load on the CPU 103 due to the management of random numbers such as updating of random numbers and shifting to initial values increases, which is not appropriate.

  The big hit determination table memory 114 shown in FIG. 4 stores a plurality of big hit determination tables set for the CPU 103 to determine whether or not the display result in the special figure game is a big hit. Specifically, the big hit determination table memory 114 stores a normal time big hit determination table 120 shown in FIG. 6A and a probability change big hit determination table 121 shown in FIG. 6B.

  The normal big hit determination table 120 shown in FIG. 6A and the probability variation big hit determination table 121 shown in FIG. 6B are based on the first variable display device 41 and the second variable display device 42. It is a table for determining whether the display result of a special figure game is a big hit. In each of the big hit determination tables 120 and 121, the value of the random R1 and the setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 121, more random R1 values are associated with the display result of “big hit” than the normal big hit determination table 120. That is, by determining the display result of the special figure game using the probability change jackpot determination table 121, it is possible to achieve a probability improvement state in which the probability of becoming a big hit gaming state is higher than in the normal gaming state.

  The symbol determination table memory 115 shown in FIG. 4 determines a plurality of types of symbols used to determine a fixed symbol of a special symbol variably displayed on the first variable display device 41 or the second variable display device 42. Store the table. Specifically, the symbol determination table memory 115 includes a first normal jackpot symbol determination table 130 shown in FIG. 7A and a first probability variable jackpot symbol determination table 131 shown in FIG. 7B. 7C, the first left symbol determination table 132 shown in FIG. 7C, the first middle symbol determination table 133 shown in FIG. 7D, and the first right symbol determination table shown in FIG. 7E. A table 134 for storage. Further, the symbol determination table memory 115 includes a second normal jackpot symbol determination table 140 shown in FIG. 8A, a second probability variation jackpot symbol determination table 141 shown in FIG. 8B, and FIG. A second left symbol determination table 142 shown in FIG. 8C, a second middle symbol determination table 143 shown in FIG. 8D, and a second right symbol determination table 144 shown in FIG. And store.

  The first normal jackpot symbol determination table 130 shown in FIG. 7 (A) is used to derive and display the same normal jackpot symbol on the left, middle, and right as the display result of the special figure game by the first variable display device 41. FIG. 10 is a table for determining a definite symbol (first normal jackpot symbol) for each special symbol. For example, in the first normal jackpot symbol determination table 130, a symbol number of a special symbol as a normal jackpot symbol that is selected and determined as a confirmed symbol is stored in association with a random R4-1 value. .

  The first probability variation jackpot symbol determination table 131 shown in FIG. 7B is used to derive and display the same probability variation jackpot symbol on the left, middle and right as the display result of the special figure game by the first variable display device 41. 7 is a table for determining a definite symbol (first probability variation big hit symbol) of each special symbol. For example, in the first probability variation big hit symbol determination table 131, the symbol number of the special symbol as the first probability variation big hit symbol selected and determined as the confirmed symbol and the value of the random R4-1 are stored in association with each other. Has been.

  The first left symbol determination table 132 shown in FIG. 7C is used when the display result of losing is derived and displayed without making a big hit in the special game by the first variable display device 41. It is a table for determining the fixed symbol (1st left fixed symbol) in a left variable display part. For example, in the first left symbol determination table 132, a symbol number of a special symbol that becomes a confirmed symbol in the first left variable display unit and a value of random R4-1 are stored in association with each other.

  The first medium symbol determination table 133 shown in FIG. 7D is displayed on the first medium variable display section when the display result of the loss is derived and displayed in the special game by the first variable display device 41. It is a table for determining a definite symbol (first medium definite symbol). For example, in the first medium symbol determination table 133, the addition value for the symbol number of the first left determined symbol and the value of random R4-2 are stored in association with each other. That is, when the game is not a big hit, the added value determined using the first medium symbol determination table 133 based on the value of the random R4-2 extracted from the random counter 113 is used as the first left symbol determination table 132. By adding to the symbol number of the first left determined symbol determined using, the first medium defined symbol can be determined. In addition, when the display result of losing is derived and displayed without reaching a big hit after reaching, if the added value determined using the first medium symbol determination table 133 is “0”, the derivation is performed. In order to make the display result to be lost, 1 may be added to the symbol number of the first medium fixed symbol.

  The first right symbol determination table 134 shown in FIG. 7E is displayed in the first right variable display section when the display result of the loss is derived and displayed in the special game by the first variable display device 41. It is a table for determining a definite symbol (1st right definite symbol). For example, in the first right symbol determination table 134, the added value for the symbol number of the left confirmed symbol and the value of the random R4-3 are stored in association with each other.

  The second normal jackpot symbol determination table 140 shown in FIG. 8A is used to derive and display the same normal jackpot symbol on the left, middle, and right as the display result of the special symbol game by the second variable display device 42. FIG. 10 is a table for determining a definite symbol (second normal jackpot symbol) for each special symbol. For example, in the second normal jackpot symbol determination table 140, a symbol number of a special symbol as a normal jackpot symbol that is selected and determined as a confirmed symbol and a value of random R4-1 are stored in association with each other. .

  The second probability variation big hit symbol determination table 141 shown in FIG. 8B is used when the same probability variation big hit symbol is derived and displayed on the left, middle and right as the display result of the special figure game by the second variable display device 42. FIG. 10 is a table for determining a definite symbol (second probability variation big hit symbol) of each special symbol. For example, in the second probability variation jackpot symbol determination table 141, a symbol number of a special symbol as a probability variation jackpot symbol selected and determined as a confirmed symbol and a value of random R4-1 are stored in association with each other. .

  The second left symbol determination table 142 shown in FIG. 8C is used when the display result of the losing is derived and displayed without making a big hit in the special game by the second variable display device 42. It is a table for determining the fixed symbol (2nd left fixed symbol) in a left variable display part. For example, in the second left symbol determination table 142, a symbol number of a special symbol that is a confirmed symbol in the second left variable display unit and a value of random R4-1 are stored in association with each other.

  The second middle symbol determination table 143 shown in FIG. 8D is displayed in the second middle variable display section when the display result of the loss is derived and displayed in the special game by the second variable display device 42. It is a table for determining a definite symbol (second medium definite symbol). For example, in the second medium symbol determination table 143, the addition value for the symbol number of the left determined symbol and the value of the random R4-2 are stored in association with each other. That is, in the case of a loss that is not a big hit, the added value determined using the second medium symbol determination table 143 based on the value of the random R4-2 extracted from the random counter 113 is used as the second left symbol determination table. By adding to the symbol number of the second left determined symbol determined using 142, the second medium defined symbol can be determined. When the display result of losing is derived without reaching a big hit after reaching, if the added value determined using the second medium symbol determination table 143 is “0”, the derivation is performed. In order to make the display result to be lost, 1 may be added to the symbol number of the second medium fixed symbol.

  The second right symbol determination table 144 shown in FIG. 8E is displayed in the second right variable display unit when the display result of the loss is derived and displayed in the special game by the second variable display device 42. It is a table for determining a fixed symbol (2nd right fixed symbol). For example, in the second right symbol determination table 144, the added value for the symbol number of the left confirmed symbol and the value of the random R4-3 are stored in association with each other.

  The variable display pattern determination table memory 116 shown in FIG. 4 stores a plurality of variable display patterns used in the special figure game. Specifically, the variable display pattern determination table memory 116 includes a first normal loss variable display pattern determination table 150 shown in FIG. 9A and a first reach loss variable display shown in FIG. A pattern determination table 151 and a first jackpot variable display pattern determination table 152 shown in FIG. 9C are stored. The variable display pattern determination table memory 116 is a second normal loss variable display pattern determination table 160 shown in FIG. 10A, and a second reach loss variable display pattern determination shown in FIG. A table 161 and a second jackpot variable display pattern determination table 162 shown in FIG. 10C are stored.

  The variable display pattern determination table 150 for the first normal loss shown in FIG. 9A is a variable display for deriving and displaying a fixed symbol of the loss without reaching in the special game by the first variable display device 41. It is a table for selecting a pattern. The first reach-losing variable display pattern determination table 151 shown in FIG. 9B derives and displays the confirmed symbols of the lose without making a hit after reaching the special figure game by the first variable display device 41. It is a table for selecting the variable display pattern to perform.

  The first jackpot variable display pattern determination table 152 shown in FIG. 9C is a variable display pattern in which the display result in the variable symbol special display in the special game by the first variable display device 41 is a jackpot. It is a table for selecting.

  The second normal loss variable display pattern determination table 160 shown in FIG. 10 (A) is a variable display for deriving and displaying the fixed symbols of the lose without reaching in the special game by the second variable display device 42. It is a table for selecting a pattern. The second reach / losing variable display pattern determination table 161 shown in FIG. 10 (B) derives and displays the confirmed symbols of the lose without hitting after reaching the special figure game by the second variable display device 42. It is a table for selecting the variable display pattern to perform.

  The second jackpot variable display pattern determination table 162 shown in FIG. 10C is a variable display pattern in which the display result in the variable symbol special display in the special game by the second variable display device 42 is a normal jackpot. Is a table for selecting.

  Each of the variable display pattern determination tables 150 to 152 and 160 to 162 includes, for example, a plurality of variable display patterns, a random R3 value, a total variable display time of a special symbol measured by the variable display time timer 119, and a variable. A control code set as EXT data of the display start command is stored in association with each other. Based on the value of random R3, the variable display pattern to be executed when the special symbol is variably displayed in the special game is selected from the variable display pattern determination tables 150 to 152 and 160 to 162. .

  The variable display start command sent from the main board 11 to the display control board 12 specifies a variable display pattern in the special symbol variable display by EXT data. Different variable display patterns are used depending on whether the display result is lost or a big hit. For this reason, on the display control board 12 side, it corresponds to a special symbol variably displayed on the first variable display device 41 or the second variable display device 42 by the variable display start command transmitted from the main board 11. The decorative design can be variably displayed on the third variable display device 43 or the fourth variable display device 44, and whether or not the display result in the variable display of the decorative design is used as the specific display result is specified. can do.

  Different variable display pattern determination tables are used depending on whether the first variable display device 41 performs variable display of special symbols or the second variable display device 42 performs variable display of special symbols. Is set. Therefore, on the display control board 12 side, the variable display device that performs the special figure game can be specified by the variable display start command transmitted from the main board 11.

  The normal A and normal B variable display patterns selected using the first and second normal loss variable display pattern determination tables 150 and 160 are variable display patterns without a reach mode. The variable display pattern of reach A (lost) selected using the first and second reach / losing variable display pattern determination tables 151 and 161 has a reach mode, but the variable display result (determined symbol) produces a big hit. This is a variable display pattern that cannot be made to occur. The variable display pattern of reach A (big hit) selected using the first and second jackpot variable display pattern determination tables 152 and 162 has a reach mode, and a variable display pattern in which the variable display result causes a big hit. It is.

  The variable display pattern of reach B is a variable display pattern having a reach form different from reach A. Here, “reach mode is different” means that after reaching reach, a different variable display mode (variable display speed or rotation direction of a special symbol, etc.), a character, or the like appears. For example, in the reach A, the reach mode is realized by only one type of variable display mode, whereas in the reach B, the reach mode including a plurality of variable display modes having different variable display speeds and rotation directions of special symbols is provided. Realized.

  In addition, the variable display pattern of reach C is a variable display pattern having a reach form different from reach A and reach B. Unlike the reach A to reach C, the variable display pattern of reach D is a variable display pattern in which reach effect display by moving images is performed. In Reach A to Reach D, there are cases where a big hit and cases where a big hit is not made.

  Furthermore, when the reach-losing variable display pattern determination tables 151 and 161 and the big hit variable display pattern determination tables 152 and 162 are compared, the assignment of the random R3 value to each variable display pattern (reach type) is different. ing. That is, the percentage of reach types to be selected differs depending on whether the display result in the special figure game is a big hit. Thereby, the probability that the display result will be a big hit differs depending on the type of reach that appears in the special figure game.

  For example, in the example shown in FIG. 9, that is, in the special game on the first variable display device 41, the ratio that the variable display pattern of reach A is used when the display result is lost is the variable display pattern of reach D Is higher than the percentage used. On the other hand, when the display result is a big hit, the ratio at which the reach display variable display pattern is used is lower than the ratio at which the reach D variable display pattern is used. For this reason, when reach by the variable display pattern of reach D appears in the special figure game, the probability that the display result will be a big hit is higher than when reach by the variable display pattern of reach A appears. In the example shown in FIG. 10, that is, in the special game with the second variable display device 42, the ratio is reversed. The probability that the display result determined for each type of variable display device or reach is a big hit is called the reach big hit reliability, or simply the reach reliability.

  The probability variation counter 117 shown in FIG. 4 is for counting the remaining number of special figure games that can be executed in the probability improvement state where probability variation control is performed. The probability variation counter 117 is predetermined to be executable in the probability improvement state when the display result of the special figure game by the first variable display device 41 or the special figure game by the second variable display device 42 is a probable big hit. Data indicating “100”, which is the number of special figure games, is set as an initial value. Each time the special symbol variable display in the special figure game is finished without the display result being a big hit in the probability improvement state, the count value of the probability variation counter 117 is decremented by one.

  The flag memory 118 is for setting a plurality of types of flags used for controlling the progress of the game in the pachinko gaming machine 1. For example, the flag memory 118 includes first and second special symbol process flags, first and second normal symbol process flags, first and second jackpot state flags, first and second probability change confirmation flags, A probability changing flag, a probability changing end flag, first and second variable display time timer stop flags, an input status flag, an error flag, a timer interrupt flag, and the like are provided.

  The first special symbol process flag indicates which processing should be selected and executed in the first special symbol process (described later) (FIG. 21). The second special symbol process flag indicates which process should be selected and executed in a second special symbol process (described later) (FIG. 30). The first normal symbol process flag indicates which process should be selected and executed in the first normal symbol process. The second normal symbol process flag indicates which process should be selected and executed in the second normal symbol process.

  The first big hit state flag is set to an on state when the display result of the special figure game by the first variable display device 41 is a big hit (when the big hit state is established), and when the big hit gaming state is ended ( It is cleared and turned off when the big hit state ends. The second big hit state flag is set to an on state when the display result of the special figure game by the second variable display device 42 is a big hit (when the big hit state is established), and when the big hit gaming state is ended ( It is cleared and turned off when the big hit state ends.

  The first certainty change confirmation flag is set to the on state when it is determined that the variable display result in the special figure game is a probable big hit when the special variable game is started by the first variable display device 41. And cleared when the big hit gaming state ends. The second certainty change confirmation flag is set to the on state when it is determined that the variable display result in the special figure game is a probable big hit when the special variable game is started by the second variable display device 42. And cleared when the big hit gaming state ends.

  The probability variation flag is set to an on state when either the first or second probability variation confirmation flag is on when the big hit gaming state ends, and the count value of the probability variation counter 117 is “0”. It is cleared and turned off when it becomes a big hit gaming state based on a normal big hit. The probability variation end flag is set to the on state when the determination to end the probability improvement state is made in first and second winning processes (FIGS. 22 and 31) described later, and the probability improvement state ends. When cleared it is turned off.

  The input state flag is a flag composed of a plurality of bits that are set or cleared in accordance with the state of various signals input to the I / O port 104, the state of the detection signal input from each winning port switch 70, and the like. The error flag is a flag composed of a plurality of bits in which bits corresponding to the type of error that has occurred are set when various errors occur in the pachinko gaming machine 1. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The first variable display time timer stop flag is displayed when a big hit symbol is derived and displayed on the second variable display device 42 during execution of the special figure game by the first variable display device 41 (a big hit state is established). At the time), it is set to the on state, and when the big hit gaming state is finished (at the time the big hit state is finished), it is cleared and turned off. The second variable display time timer stop flag is displayed when a big hit symbol is derived and displayed on the first variable display device 41 during execution of the special figure game by the second variable display device 42 (a big hit state is established). At the time), it is set to the on state, and when the big hit gaming state is finished (at the time the big hit state is finished), it is cleared and turned off.

  The variable display time timer 119 shown in FIG. 4 includes a first variable display time timer and a second variable display time timer. The first variable display time timer is a down counter for measuring on the main side the variable display time that is the execution time of the special figure game by the first variable display device 41, and the second variable display time timer is It is a down counter for measuring the variable display time which is the execution time of the special figure game by the 2nd variable display apparatus 42 by the main side. When the variable display start command is sent from the main board 11 to the display control board 12, the first and second variable display time timers have a count value corresponding to the total variable display time specified by the variable display pattern. Set as initial value.

  The switch circuit 107 shown in FIG. 2 takes in the detection signal from each winning opening switch 70 and transmits it to the game control microcomputer 100. The solenoid circuit 108 drives each of the solenoids 21, 22, 23 and 24 in accordance with a command from the game control microcomputer 100. The solenoid 21 is connected to the movable wing piece of the first ordinary variable winning ball apparatus 61 via a link mechanism. The solenoid 22 is connected to the movable wing piece of the second ordinary variable winning ball apparatus 62 via a link mechanism. The solenoid 23 is connected to the opening / closing plate of the first special variable winning ball apparatus 71 through a link mechanism. The solenoid 24 is connected to the opening / closing plate of the second special variable winning ball device 72 through a link mechanism.

Next, details of the random counter 113 will be described with reference to FIG.
As shown in FIG. 11, the random counter 113 includes a reference clock signal generation circuit 1201, a count clock signal generation circuit 1202, a counter 1203, a frequency division circuit 1211, a first latch signal output circuit 1204A, Random number value storage circuit 1205A, a second latch signal output circuit 1204B, and a second random number value storage circuit 1205B.

  The reference clock signal generation circuit 1201 outputs a reference clock signal S0 having a predetermined frequency, for example, 20 MHz, as shown in FIG.

  The count clock signal generation circuit 1202 is composed of a D-type flip-flop, the reference clock signal S0 (FIG. 13A) is supplied to the clock terminal Clk, and the reverse phase output (Q bar) signal S2 (FIG. 13C). ) Is fed back to the D input terminal, and the positive phase output Q is output to the counter 1203 as the count clock signal S1 (FIG. 13B).

  The counter 1203 is composed of a 16-bit up counter and, as shown in FIG. 13D, in response to the rising edge of the count clock signal S1, the count value C is counted one by one from “0” to “65535”. Go up. When the counter 1203 counts up the count value C to “65535”, the counter 1203 returns to “0” and again counts up to “65535”.

  The frequency dividing circuit 1211 is composed of a D-type flip-flop, and the anti-phase output (Q bar) signal S2 (FIG. 13C) of the count clock signal output circuit 1202 is supplied to the clock terminal Clk and the anti-phase output ( Q bar) signal S2A (FIG. 13E) is fed back to the D input terminal and output to the clock terminal Clk of the first latch signal output circuit 1204A. Further, the positive phase output (Q) S2B (FIG. F)) is supplied to the clock terminal Clk of the second latch signal output circuit 1204B.

  The first latch signal output circuit 1204A is composed of a D-type flip-flop, and the input terminal D is connected to the output terminal of the first winning opening switch 70A disposed in the first ordinary variable winning opening device 61, and the clock terminal Clk. Are respectively connected to the negative phase output (Q bar) of the frequency dividing circuit 1211. The first latch signal output circuit 1204A latches the first start winning signal SSA (for example, the signal shown in FIG. 13G) input to the input terminal D at an arbitrary timing and input to the clock terminal Clk. It is output from the output terminal Q as a latch signal (high level signal) SLA (FIG. 13 (I)) in synchronization with the rising edge (latch timing signal) of the clock signal S2A (FIG. 13 (E)).

  The first random value storage circuit 1205A is composed of a D-type flip-flop, and the counter 1203 counts in response to the rising edge of the latch signal SLA (FIG. 13 (I)) from the first latch signal output circuit 1204A. The value C (FIG. 13D) is latched and output as shown in FIG.

  The second latch signal output circuit 1204B is composed of a D-type flip-flop, and the input terminal D is connected to the output terminal of the second winning opening switch 70B arranged in the second ordinary variable winning opening device 62, and the clock terminal Clk. Are respectively connected to the positive phase output (Q) of the frequency dividing circuit 1211. The second latch signal output circuit 1204B latches a second start winning signal SSB (for example, a signal shown in FIG. 13H) input to the input terminal D at an arbitrary timing and input to the clock terminal Clk. In synchronization with the rising edge (latch timing signal) of the clock signal S2B (FIG. 13F), it is output from the output terminal Q as a latch signal (high level signal) SLB (FIG. 13J).

  Note that the latch clock signal S2A supplied to the clock terminal Clk of the first latch signal output circuit 1204A and the latch clock signal S2B supplied to the clock terminal Clk of the second latch signal output circuit 1204B are divided by the frequency dividing circuit 1211. The reverse phase output Q bar and the normal phase output Q are inversion signals whose phases are shifted by 180 °, and the counter 1203 has a cycle twice as long as the count value is updated.

  The second random value storage circuit 1205B is composed of a D-type flip-flop, and the counter 1203 counts in response to the rising edge of the latch signal SLB (FIG. 13J) from the second latch signal output circuit 1204B. The value C (FIG. 13D) is latched and output as a random value as shown in FIG.

  FIG. 12 is a circuit diagram showing a configuration example of the first random value storage circuit 1205A. As illustrated, the first random value storage circuit 1205A includes two AND circuits 1301 and 1303, two NOT circuits 1302 and 1304, 16 flip-flop circuits 1311 to 1326, and 16 ORs. Circuits 1331 to 1346.

  The input terminal of the AND circuit 1301 is connected to the output terminal Q of the first latch signal output circuit 1204A and the output terminal of the NOT circuit 1304, and the output terminals thereof are the input terminal of the NOT circuit 1302 and the flip-flop circuits 1311 to 1326. Are connected to the clock terminals Clk1 to Clk16. The input terminal of the NOT circuit 1302 is connected to the output terminal of the AND circuit 1301, and the output terminal is connected to one input terminal of the AND circuit 1303.

  The input terminal of the AND circuit 1303 is connected to the output terminal of the NOT circuit 1302 and the I / O port of the CPU 103, and the output terminal is connected to the input terminal of the NOT circuit 1304. The input terminal of the NOT circuit 1304 is connected to the output terminal of the AND circuit 1303, and the output terminal is connected to one input terminal of the AND circuit 1301 and one input terminal of each of the OR circuits 1331 to 1338.

  The input terminals D1 to D16 of the flip-flop circuits 1311 to 1326 are connected to the output terminal of the counter 1203, and any of 16 bits of bit data constituting the count value C is supplied. The clock terminals Clk1 to Clk16 of the flip-flop circuits 1311 to 1326 are connected to the output terminal of the AND circuit 1301, and the output terminals Q1 to Q16 are connected to the other input terminals of the OR circuits 1331 to 1346, respectively.

  The input terminals of the OR circuits 1331 to 1346 are connected to the output terminal of the NOT circuit 1304 and the corresponding output terminals of the flip-flop circuits 1311 to 1326, and the output terminals are connected to the I / O port of the CPU 103. Yes.

  In this configuration, in the initial state, both the start winning signal SLA and the read control signal SRCA are at a low level. The output of the AND gate 1301 is low level, the output of the NOT circuit 1302 is high level, the output of the AND gate 1303 is low level, the output of the NOT circuit 1304 is high level, and the OR gates 1331 to 1346 all output high level signals. To do. In this state, when a start winning is generated and the first start winning signal SLA becomes high level, the output of the AND gate 1301 also becomes high level, and each of the D flip-flops 1311 to 1326 has a count value (random value). Corresponding bits C1 to C16 are latched. On the other hand, the output of the NOT circuit 1302 becomes a low level. Therefore, the read control signal SRCA from the CPU 103 is not accepted while the first start winning signal SLA is high bell. Therefore, while the D flip-flops 1311 to 1326 are updating the count value, the CPU 103 does not read the unstable (incomplete) random number value being updated.

  On the other hand, in the initial state (both the start winning signal SLA and the read control signal SRCA are both at low level), when the CPU 103 reads the random number value and makes the read control signal SRCA high, the output of the NOT circuit 1304 becomes low. The OR gates 1331 to 1346 output the output data (stored values) of the D flip-flops 1311 to 1326 as they are to the I / O port of the CPU 103. Further, since one input of the AND gate 1301 is at a low level, the AND gate 1301 does not accept the start winning signal SLA. Therefore, while the CPU 103 reads the random number value with the read control signal SRCA at the high level, the situation that the random number value is not updated occurs, and the random number value can be read stably.

  The configuration of the second random value storage circuit 1205B is basically the same as that shown in FIG. However, the latch signal is read from SLA to SLB, and the read control signal is read from SRCA to SRCB.

  The first and second start winning signals SSA and SSB from the first and second winning opening switches 70A and 70B arranged in the first and second ordinary variable winning ball devices 61 and 62 are also supplied to the CPU 103. The CPU 103 takes in the count values (random number values) latched by the first random number value storage circuit 1205A and the second random number value storage circuit 1205B, and stores each count value (random number value) in the first special diagram. It is stored at the head of each empty entry in the holding memory 111 and the second special figure holding memory 112.

  FIG. 13 is a timing chart for explaining the operation of the random counter 113.

  As shown in FIG. 13A, the reference clock signal generation circuit 1201 has, for example, a frequency of 20 MHz and rises from a low level to a high level at timings T11, T12,. The reference clock signal S0 falling to the level is output to the count clock signal generation circuit 1202.

  The count clock signal generation circuit 1202 substantially divides the reference clock signal S0 by ½, and the 10 MHz count clock signal S1 as shown in FIGS. 13B and 13C and its inverted signal count. The clock signal S2 is converted and output from the positive phase output terminal (Q) and the negative phase output terminal (Q bar).

  As shown in FIG. 13D, the counter 1203 updates and outputs a count value (count value data) C in response to the rising edge of the count clock signal S1.

  The frequency dividing circuit 1211 substantially divides the count clock signal S2 output from the count clock signal generation circuit 1202 by 1/2 to obtain a 5 MHz latch clock (timing as shown in FIGS. 13E and 13F). ) Signal S2A and its inverted signal, latch clock signal S2B, are converted and output from negative-phase output terminal Q bar and positive-phase output terminal Q.

  The first latch signal output circuit 1204A generates a start winning signal SSA as illustrated in FIG. 13 (G) output at the start winning generated at an arbitrary timing as a first latch clock signal (latch timing signal) S2A. In synchronization with (FIG. 13E), the first latch signal SLA shown in FIG. 13I is output.

  In response to the first latch signal SLA (rising edge), the first random value storage circuit 1205A latches the count value (random number) data as shown in FIG.

  Thereafter, the CPU 103 outputs a read control signal SRCA, reads the random number value stored in the first random value storage circuit 1205A, sets it in the first special figure reservation memory 111 (if there is an empty space), and then The read control signal SRCA is turned off to make it impossible to read.

  The positive-phase (Q) output terminal of the frequency dividing circuit 1211 is supplied to the second latch signal output circuit 1204B as the second latch clock signal S2B shown in FIG.

  As shown in FIGS. 13B to 13F, the first and second latch clock signals S2A and S2B have a period twice that of the count clock signal S1, that is, a count value update period of the counter 1203. The period is 180 ° shifted from each other and in a reverse phase relationship, while the counter 1203 outputs one value (between the count value update and the next update) Only one of the latch clock signals rises.

  The second latch signal output circuit 1204B synchronizes with the second latch clock signal S2B a start winning signal SSB as illustrated in FIG. 13 (H) output at the start winning established at an arbitrary timing. The second latch signal SLB shown at 13 (J) is output.

  In response to the second latch signal SLB (rising edge), the second random value storage circuit 1205B latches the count value (random value) data as shown in FIG.

  After that, the CPU 103 outputs the read control signal SRCB, reads the stored value, sets it in the second special figure reservation memory 112 (if there is an empty space), and then turns off the read control signal SRCB to set the read disabled state. To do.

  As shown in FIGS. 13D to 13H, the first and second latch clock signals S2A and S2B are 2 in the cycle in which the counter 1203 updates the count value C (the cycle of the count clock signal S1). It is in reverse phase with double period. For this reason, only one of these rising edges (latch timing) occurs in one count value of the counter 1203 (period from when the count value is updated to when it is updated next). Accordingly, suppose that the game balls win the first and second ordinary variable winning ball devices 61 and 62 almost simultaneously, and as shown in FIGS. 13 (G) and (H), the first and second start almost simultaneously. Even when the winning signals SSA and SSB are generated, the timings at which the first and second latch clock signals (latch timing signals) S2A and S2B are output are different, as shown in FIGS. 13 (I) and (J). In other words, the random number values stored in the first and second random value storage circuits 1205A and 1205B are different. Therefore, although one counter 1203 is used, a situation in which the random number value for the first variable display device 41 and the random value value for the second variable display device 42 are synchronized is prevented.

  The display control board 12 shown in FIG. 2 performs display control for image processing in the variable display game independently of the main board 11. The display control board 12 displays an image used in the variable display game on the third variable display device 43 and the fourth variable display device 44 based on the display control command output from the main board 11. That is, the display control board 12 controls the display operation of the third variable display device 43 and the fourth variable display device 44 based on a control command from the main board 11, thereby displaying images related to the progress of the game. Control the production.

FIG. 14 is a block diagram illustrating a hardware configuration example of the display control board 12. The display control board 12 includes an oscillation circuit 200, a reset circuit 201, a CPU 202 for display control, a ROM 203, a RAM 204, and a GCL (Graphic).
Control LSI) 205, CGROM 206, and VRAM (Video RAM) 207.

  The oscillation circuit 200 outputs a reference clock signal to the CPU 202 and the GCL 205, and the reset circuit 201 outputs a reset signal for resetting the CPU 202 and the GCL 205. When the CPU 202 receives a display control command from the main board 11, the CPU 202 reads control data for performing display control from the ROM 203 while using the RAM 204 as a work area. Further, the CPU 202 sends a drawing command to the GCL 205 based on the read control data. The ROM 203 is a semiconductor memory that stores various control programs used by the CPU 202, and the RAM 204 is a semiconductor memory used as a work area by the CPU 202.

  The GCL 205 has a display device control function for performing image display and a high-speed drawing function, and operates in accordance with a drawing command from the CPU 202. Further, it has a two-dimensional address space independent of the CPU 202, and the VRAM 207 is mapped there. The CGROM 206 is for storing various image data for displaying images on the third variable display device 43 and the fourth variable display device 44. For example, in the CGROM 206, character image data frequently used among images displayed on the third variable display device 43 and the fourth variable display device 44, specifically, a person, an animal, or a character, Figures or symbols are stored in advance. A VRAM 207 is a frame buffer memory for expanding image data generated by the GCL 205.

  Further, as shown in FIG. 15, the display control board 12 includes a random counter 211, a display control pattern table memory 212, a flag memory 214, and various timers 215.

  The random counter 211 counts a random R10, which is a random number used to determine the content of the effect produced by the display on the third variable display device 43 or the fourth variable display device 44. As shown in FIG. 16, the random R10 is a random number for determining which one of the plurality of types of display control patterns stored in the display control pattern table memory 212 is to be used in the current decoration drawing game. "Takes a value in the range of" 9 ".

  The display control pattern table memory 212 shown in FIG. 15 stores a plurality of display control pattern tables selected based on the display control command received from the main board 11. Specifically, as shown in FIG. 17, the display control pattern table memory 212 includes a symbol display control pattern table 220 and the like.

  The symbol display control pattern table 220 shown in FIG. 17 stores a plurality of types of symbol display control patterns. As shown in FIG. 18, each symbol display control pattern includes data for controlling the display state of a decorative symbol such as a symbol display control process timer setting value, symbol display control data, and the like. The display speed, the size of the pattern to be displayed, the display period in the display state, the character switching timing, and the like are set.

  The flag memory 214 is for setting a plurality of types of flags that are set or cleared in accordance with the display state of the third and fourth variable display devices 43 and 44 and the reception of a command from the main board 11. For example, the flag memory 214 includes first and second display control process flags, first and second notification effect start flags, first and second variable display start flags, first and second valid flags, Third and fourth variable display time timer stop flags, a timer interrupt flag, and the like are provided.

  The first display control process flag indicates which process should be selected and executed in the first decorative symbol display control process (described later) (FIG. 42). The second display control process flag indicates which process should be selected and executed in the second decorative symbol display control process (FIG. 47) described later.

  The first notification effect start flag is set to an on state when the first notification effect start command 8000 (h) is received from the main board 11, and the second notification effect start flag is set to the second value from the main board 11. Is turned on when the notification effect start command 8100 (h) is received. The first notification effect end flag is set to the on state when the first notification effect end command 9000 (h) is received from the main board 11, and the second notification effect end flag is set to the second value from the main board 11. When the notification effect end command 9100 (h) is received, it is set to the on state.

  The first variable display start flag is set to an on state when the first variable display start command A0XX (h) is received from the main board 11, and the second variable display start flag is set to the second variable display start flag. Set to ON when command A1XX (h) is received. The first valid flag is set to the on state when the first left / middle / right symbol designation commands B0XX (h), B1XX (h) and B2XX (h) are received from the main board 11, and the second valid flag The valid flag is set to ON when the second left / middle / right symbol designation commands C0XX (h), C1XX (h), and C2XX (h) are received from the main board 11.

  The third variable display time timer stop flag is set to an on state when a big hit symbol is derived and displayed on the fourth variable display device 44 during execution of the special game by the third variable display device 43. When the big hit gaming state is finished, it is cleared and turned off. The fourth variable display time stop flag is set to an on state when a big hit symbol is derived and displayed on the third variable display device 43 during execution of the special figure game by the fourth variable display device 44. When the jackpot gaming state ends, it is cleared and turned off. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated.

  The various timers 215 shown in FIG. 15 include a plurality of types of timers used for display control of the third variable display device 43 and the fourth variable display device 44. For example, the various timers 215 include first and second symbol display control process timers, third and fourth variable display time timers, and first and second monitoring timers. The first symbol display control process timer variably displays the ornament symbol in a manner according to the display control pattern on the third variable display device 43 by counting down the process timer value set in the symbol display process table. The second symbol display control process timer measures the variable display period in which the fourth variable display device 44 variably displays the decorative symbols in a manner according to the display control pattern.

  The third variable display time timer included in the various timers 215 is a down counter for measuring the variable display time, which is the execution time of the decoration drawing game by the third variable display device 43, on the sub side. The variable display time timer is a down counter for measuring the variable display time, which is the execution time of the decoration drawing game by the fourth variable display device 44, on the sub side. The first monitoring timer is for measuring an elapsed time after the third variable display time timer times out, and the second monitoring timer is after the fourth variable display time timer times out. It is for measuring the elapsed time. The first and second monitoring timers time out when a display control command is not received from the main board 11 for a predetermined time or more.

  In addition, the gaming machine 1 performs the audio output control and the lamp output control independently of the main board 11 based on the control command transmitted from the main board 11, respectively, and the sub-side audio control board and lamp control board Is provided. The sound control board controls the sound output operation by the speakers 8L and 8R based on the control command from the main board 11, thereby controlling the sound effect related to the progress of the game. Further, the lamp control board controls the lighting / flashing operation of the game effect lamp 9 based on the control command from the main board 11, thereby controlling the effect by the lighting, blinking or extinguishing of the lamp related to the progress of the game. The payout control board 15 performs payout control for game balls, prize balls, and the like. Further, the gaming machine 1 includes an information terminal for outputting various game-related information to the outside.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. FIG. 19 is a flowchart showing a game control main process executed by the game control microcomputer 100 mounted on the main board 11. In the main board 11, when the power supply voltage from the power supply board 10 is supplied, the game control microcomputer 100 is activated, and the CPU 103 first executes the game control main process shown in the flowchart of FIG. When the game control main process is started, the CPU 103 performs the necessary initial setting (step S2) after setting the interrupt prohibition (step S1). In this initial setting, for example, the RAM 102 is cleared. Further, by setting a register of a CTC (counter / timer circuit) built in the game control microcomputer 100, a timer interrupt is generated periodically (for example, every 2 milliseconds). When the initial setting is completed, interrupt processing is permitted (step S3), and then loop processing is started.

  By executing the game control main process, the timer interrupt is set to repeatedly occur every 2 milliseconds. When the timer interrupt occurs, the CPU 103 executes the game control interrupt process shown in the flowchart of FIG. .

  When the game control interrupt process shown in the flowchart of FIG. 20 is started, the CPU 103 first executes a predetermined switch process, thereby changing the state of the detection signal input from each winning opening switch 70 via the switch circuit 107. Determination is made (step S11). Subsequently, by executing predetermined error processing, abnormality diagnosis of the pachinko gaming machine 1 is performed, and if necessary, warning can be generated according to the diagnosis result (step S12). Thereafter, a process of extracting random R1 which is a random number for determination counted by the random counter 113, and a random number update process for determination for updating random R2 and R5 which are random numbers generated by software processing (step S13) Then, the display random number update process for updating the random numbers R3 and R4, which are display random numbers generated by the software process, is sequentially executed (step S14).

  Next, the CPU 103 sequentially executes the first special symbol process (step S15) and the second special symbol process (step S16). In the first special symbol process and the second special symbol process, the first special symbol process provided in the flag memory 118 for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The corresponding processing is selected and executed according to the flag and the second special symbol process flag. Subsequently, the CPU 103 sequentially executes the first normal symbol process (step S17) and the second normal symbol process (step S18). In the first normal symbol process and the second normal symbol process, the first normal symbol display 51 and the second normal symbol display 52 are controlled in a predetermined order in order to control the first normal symbol display 51 and the second normal symbol display 52. Corresponding processing is selected and executed according to the process flag and the second normal symbol process flag.

  Further, the CPU 103 executes a predetermined command control process to send a control command from the main board 11 to a sub-side control board such as the display control board 12 and instruct operation control according to the gaming state. (Step S19). The CPU 202 of the display control board 12 receives the display control command sent from the main board 11 by this command control processing, and the display control of the third and fourth variable display devices 43 and 44 is performed according to the display control command.

  In addition, the CPU 103 executes predetermined information output processing to output the contents of the storage area for various output data to each output port included in the I / O port 104 (step S20). In this information output process, a command for outputting jackpot information, starting information, probability variation information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Subsequently, the CPU 103 executes a predetermined solenoid output process to perform the movable control of the movable blade pieces in the first and second ordinary variable winning ball devices 61 and 62 when the predetermined condition is satisfied. Opening and closing drive of the opening and closing plates in the second special variable winning ball devices 71 and 72 is performed (step S21). After that, by executing predetermined prize ball processing, it is possible to set the number of prize balls based on the detection signal input from each prize opening switch 70 and to output a payout control command to the payout control board 15. (Step S22).

  FIG. 21 is a flowchart showing the first special symbol process executed in step S15. When the first special symbol process is started, the CPU 103 first detects whether or not the game ball has won the first ordinary variable winning ball device 61 by detecting the first starting ball included in each winning opening switch 70. The determination is made by checking the detection signal input from the switch 70A (step S101). When the game ball is won and the detection signal from the first starting ball detection switch 70A is turned on (step S101; Yes), the first winning process is executed (step S102). On the other hand, if the game ball has not won (step S101; No), the first winning process is skipped.

  FIG. 22 is a flowchart showing the first winning process in step S102. In the first winning process, the CPU 103 first determines whether or not the number of start winning memories stored in the first special figure reservation memory 111 is a maximum value of 4 (step S201).

  When the start winning memory number is 4 (step S201; Yes), the start detection by the current winning is invalidated, and the first winning process is ended as it is. On the other hand, when the starting winning memory number is less than 4 (step S201; No), 1 is added to the starting winning memory number of the first special figure reservation memory 111 (step S202), and the value of the random R1 is determined from the random counter 113 Extract (step S203).

  This random number extraction process will be specifically described. As described with reference to FIGS. 11 to 13, in the random counter 113, the count clock signal generation circuit 1202 generates the count clock signal S1 based on the reference clock signal S0. In response to the count clock signal S1, the counter 1203 sequentially updates the count value. The start winning signal SSA from the start winning port switch 70A of the first ordinary variable winning ball apparatus 61 is also supplied to the first latch signal output circuit 1203A, and the reverse phase output (Q bar) of the count clock signal generation circuit 1202 Is output to the first random value storage circuit 1205A as a latch signal SLA in synchronization with the first latch clock signal S2A output from the first random number memory circuit 1202A. The first random value storage circuit 1205A latches the count value output from the counter 1203 in response to the latch signal SLA.

  The CPU 103 reads out the random value stored in the first random value storage circuit 1205A, that is, the random R1, and sets it at the head of the empty entry in the first special figure reservation memory 111 (step S204). At this time, the first start-winning memory, such as turning on one of the LEDs turned off in the first start-winning memory display 45 (for example, the leftmost LED among the turned-off LEDs) is used. Lighting control of the display 45 is performed.

  Thereafter, the CPU 103 selects one of the nine processes of steps S110 to S118 shown in FIG. 21 based on the value of the first special symbol process flag provided in the flag memory 118. Below, each process of step S110-S118 is demonstrated.

  The first special symbol normal process of step S110 is a process executed when the value of the first special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the first special figure reservation memory 111 is “0”. Here, in the first special figure reservation memory 111, when various data such as a random number value corresponding to the reservation number “1” is not stored, it is determined that the storage number is “0”. If the number of reserved memories is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the third variable display device 43 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the first special symbol process flag is updated to “1” which is a value corresponding to the first jackpot determination process.

  The first jackpot determination process in step S111 is a process executed when the value of the first special symbol process flag is “1”. In this process, as shown in FIG. 23, the CPU 103 first reads the value of the random R1 stored corresponding to the hold number “1” from the first special figure hold memory 111 (step S221). At this time, 1 is subtracted from the reserved storage number, and the random R1 value stored in the second to fourth entries (holding numbers “2” to “4”) of the first special figure holding memory 111 is set to one entry. The information is shifted up one by one (step S222).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S223), and if it is not in the probability change state (step S223; No), the CPU 103 determines that the game state is normal, and the first A normal big hit determination table 120 as shown in FIG. 6 (A) is set as a table for determining whether or not the display result of the special figure game by the variable display device 41 is a big hit (step S224). On the other hand, if the probability change is in progress (step S223; Yes), the probability change big hit determination table 121 as shown in FIG. 6B is set (step S225).

  The CPU 103 uses the jackpot determination table 120 or 121 set in the process of step S224 or S225 based on the value of the random R1 read in the process of step S221, and the special game by the first variable display device 41. It is determined whether or not the display result is a big hit (step S226). If it is determined to be a big hit (step S226; Yes), the first big hit state flag provided in the flag memory 118 is set to the on state (step S227), and it is determined to be lost. In such a case (step S226; No), the first big hit state flag is cleared and turned off (step S228). Thereafter, the value of the first special symbol process flag is updated to “2” which is a value corresponding to the first confirmed symbol determination process (step S229).

  The first determined symbol determination process in step S112 shown in FIG. 21 is a process executed when the value of the first special symbol process flag is “2”. In this process, the CPU 103 executes the processes shown in FIGS. 24 and 25, and first determines whether or not the first big hit state flag provided in the flag memory 118 is on (step S231). When the first big hit state flag is off (step S231; No), a random number program is executed to generate a random R2, extract its value (step S232), and determine whether or not to reach. (Step S233). For example, when the value of random R2 extracted in the process of step S232 is any one of “105” to “1530”, it is determined not to reach, and when it is any one of “0” to “104”. And decide to reach.

  When it is determined not to reach in the process of step S233 (step S233; No), the CPU 103 clears the first reach state flag provided in the flag memory 118 and sets it to the off state (step S234). Then, a random number program is executed to generate a random R4-1, and based on this value, a first left determined symbol is determined using the first left symbol determining table 132 shown in FIG. Step S235). In addition, a random number program is executed to generate a random R4-2, and based on this value, the first medium symbol determination table 133 shown in FIG. (Step S236), Random R4-3 is generated by the random number program, and based on this value, the first right determined symbol is determined using the first right symbol determining table 134 shown in FIG. 7C. (Step S237). Thereafter, the process proceeds to step S251.

  Further, when it is determined to reach in the process of step S233 (step S233; Yes), the CPU 103 sets the first reach state flag to the on state (step S238), and the random number extracted from the random counter 113 is set. Based on the value of R 4-1, the first left determined symbol is determined using the first left symbol determining table 132 (step S 239). Further, it is determined that a special symbol having the same symbol number as the first left determined symbol is set as the first right determined symbol (step S240), and any special symbol different from the first left / right determined symbols is determined. To be the first medium-determined symbol (step S241). Thereafter, the process proceeds to step S251.

  When it is determined in step S231 described above that the big hit state flag is on (step S231; Yes), the CPU 103 executes a random number program to generate a random R5 (step S242), and based on this value Then, it is determined whether or not to perform probability variation control for shifting to the probability improvement state after the big hit gaming state is ended (step S243). For example, it is determined that the probability variation control is performed when the value of the random R5 is an odd number, and it is determined that the probability variation control is not performed when the value of the random R5 is an even number.

  When it is determined that the probability variation control is not performed in the process of step S243 (step S243; No), the CPU 103 clears the first probability variation confirmation flag provided in the flag memory 113 and sets the off state (step S244). ), A first normal jackpot symbol determination table 130 shown in FIG. 7A is set as a table for determining the fixed symbol of the special symbol that is a variable display result of the jackpot (step S245). When it is determined that the probability variation control is to be performed in the process of step S243 (step S243; Yes), the first probability variation flag is set to the on state (step S246), and the fixed symbol of the special symbol is determined. As a table for this purpose, a first probability variation big hit symbol determination table 131 shown in FIG. 7B is set (step S247).

  After executing the process of step S245 or S247, the CPU 103 generates a random R4-1 (step S248), and based on the value of the random R4-1, the symbol determination table 130 set in the process of step S245 or S247. Alternatively, 131 is used to determine a decisive symbol for jackpot that is the same for left, middle, and right (step S249).

  Then, the first left / middle / right symbol designation commands B0XX (h), B1XX are set by setting control data corresponding to the confirmed symbol of the special symbol determined in step S249 in a predetermined command transmission table. (H) and B2XX (h) are set to be sendable to the display control board 12 (step S250). Thereafter, the CPU 103 updates the value of the first special symbol process flag to “3”, which is a value corresponding to the first variable display pattern setting process, and ends the first fixed symbol determination process (step S1). S251).

  The first variable display pattern setting process in step S113 shown in FIG. 21 is a process executed when the value of the first special symbol process flag is “3”. In this process, the CPU 103 executes the process shown in FIG. 26, and first determines whether or not the first big hit state flag provided in the flag memory 118 is on (step S261). When the first big hit state flag is OFF (step S261; No), it is determined whether or not reach is determined in the first determined symbol determination process in step S112 (step S262).

  When not reaching (step S262; No), the first normal loss variable display pattern determination table 150 shown in FIG. 9A is set as a table for selecting a variable display pattern (step S263). On the other hand, in the case of reaching (step S262; Yes), the first reach / losing variable display pattern determination table 151 shown in FIG. 9B is set as a table for selecting a variable display pattern. (Step S264).

  When the first big hit state flag is ON in the process of step S261 (step S261; Yes), the first big hit time variable shown in FIG. 9C is used as a table for selecting a variable display pattern. The display pattern determination table 152 is set (step S265).

  The CPU 103 extracts the value of random R3 from the random counter 113 (step S266), and based on the extracted value of random R3, among the variable display pattern determination tables set in the processing of step S263, S264, or S265. From this, the variable display pattern used in this special figure game is determined (step S265).

  Thereafter, the CPU 103 performs display control of the first variable display start command A0XX (h) by setting control data corresponding to the variable display pattern determined in step S267 in a predetermined command transmission table. It is set so that it can be sent to the substrate 12 (step S268). Then, the variable display of the special symbol is started by the first variable display device 41 (step S269), and the total variable display time corresponding to this variable display pattern is displayed in the first variable display provided in the variable display time timer 119. The time timer is set (step S270). Thereafter, the CPU 103 updates the value of the first special symbol process flag to “4”, which is a value corresponding to the first variable display control process (step S271).

  The first variable display control process of step S114 shown in FIG. 21 is a process executed when the value of the first special symbol process flag is “4”. In this process, as shown in FIG. 27, the CPU 103 first determines whether or not the first variable display time timer stop flag provided in the flag memory 118 is turned on (step S291). When the first variable display time timer stop flag is off (step S291; No), the timer value is updated by subtracting 1 from the timer value of the first variable display time timer (step S292).

  Then, it is determined whether or not the timer value of the updated first variable display time timer is “0” (step S293). When the timer value of the first variable display time timer becomes “0” (step S293; Yes), the value of the first special symbol process flag is a value corresponding to the variable display stop time process “5”. To "" (step S294). On the other hand, when it is determined in step S293 that the timer value of the first variable display time timer is other than “0” (step S293; No), the first special symbol process flag is not updated. 1 variable display control processing is terminated.

  When the first variable display time timer stop flag is turned on in step S291 (step S291; Yes), the processing in steps S292 to S294 is skipped and the first variable display control process is performed as it is. Exit. Thereby, the countdown of the timer value of the first variable display time timer can be stopped until the first variable display time timer stop flag is turned on again after being turned on. As a result, the first variable display time timer can be stopped. While the variable display of the special symbol by the device 41 is continued, the variable display time of the special symbol can be extended.

  The first variable display stop process in step S115 of FIG. 21 is a process executed when the value of the first special symbol process flag is “5”. In this processing, as shown in FIG. 28, the CPU 103 derives and displays the fixed symbol of the special symbol on the first variable display device 41, and ends the variable symbol special symbol display on the first variable display device 41. At the same time (step S301), settings are made to send the first decorative symbol determination command D000 (h) from the main board 11 to the display control board 12 (step S302). Specifically, the control data corresponding to the first decorative symbol determination command D00 (h) is set in a predetermined command transmission table, and the first decorative symbol determination command D000 (h) is displayed on the display control board. 12 is set to be sendable. The CPU 103 transmits one or more commands set in the command transmission table to the display control board 12 in a subsequent command control process (step S19).

  Subsequently, the CPU 103 determines whether or not the first big hit state flag provided in the flag memory 118 is turned on (step S303). When the first big hit state flag is off (step S303; No), it is subsequently determined whether or not the probability changing flag provided in the flag memory 118 is on (step S304). When the probability changing flag is off (step S304; No), the process proceeds to step S310.

On the other hand, when the probability change flag is on (step S304; Yes), it is determined whether or not the probability change end flag is on (step S305). If the probability variation end flag is on (step S305; Yes), the probability variation in progress flag, the probability variation end flag, and the probability variation counter are cleared (step S306), and the process proceeds to step S310.
If the probability variation end flag is off in step S305 (step S305; No), the count value of the probability variation counter 117 is decremented by 1 (step S307), and the count value of the probability variation counter 117 is “0”. It is determined whether or not (step S308). When the count value of the probability variation counter 117 is not “0” (step S308; No), the process proceeds to step S310.

  On the other hand, when the count value of the probability variation counter 117 is “0” (step S308; Yes), the probability variation flag is cleared (step S309). Thereafter, the CPU 103 updates the value of the first special symbol process flag to “0” (step S310).

  Further, when the first big hit state flag is on in the process of step S303 (step S303; Yes), the second variable display time timer stop flag provided in the flag memory 118 is set to the on state ( After that, the value of the first special symbol process flag is updated to “6” that is a value corresponding to the first pre-opening process for the winning opening (step S312).

  21 is the process executed when the value of the first special symbol process flag is “6”. In this process, the CPU 103 performs setting for starting control for opening the first special variable winning ball apparatus 71 as a big winning opening. Then, the control for opening the first special variable winning ball apparatus 71 is started, and the value of the first special symbol process flag is updated to “7”, which is a value corresponding to the first big prize opening opening process. To do.

  Further, the first special winning opening opening process in step S117 is a process executed when the value of the first special symbol process flag is “7”. In this process, the CPU 103 displays a display control command for detecting the winning of a game ball to the opened first special variable winning ball device 71, a payout command, measuring the opening time, and displaying the number of rounds of the opening cycle. Make settings. For example, the number of opening of the first special variable winning ball apparatus 71 is counted for one jackpot, and if the number of opening reaches, for example, 16, the condition for ending the specific gaming state (jackpot gaming state) Is completed, the value of the first special symbol process flag is updated to “8” which is a value corresponding to the jackpot end process. On the other hand, if the number of opening times has not reached 16, the first special variable winning ball apparatus 71 is once closed and then opened again after a predetermined time has elapsed.

  The first jackpot end process in step S118 is a process executed when the value of the first special symbol process flag is “8”. In this process, as shown in FIG. 29, the CPU 103 first ends the jackpot gaming state by making a setting for sending a jackpot end command E000 (h) to the display control board 12 ( In step S321), the first big hit state flag and the second variable display time timer stop flag provided in the flag memory 118 are cleared and turned off (step S322). Thereby, the countdown of the timer value of the second variable display time timer provided in the flag memory 118 is resumed.

  As described above, the second variable display time timer stop flag is in the ON state from the first variable display stop time process of step S115 to the first big hit end process of step S118. In the display device 42, after the big hit symbol is derived and displayed on the first variable display device 41 and enters the big hit gaming state, the display display of the display result is restricted until the big hit gaming state ends. As a result, the jackpot symbol is also derived and displayed on the second variable display device 42 while the jackpot gaming state is based on the fact that the jackpot symbol is derived and displayed on the first variable display device 41, and the two jackpot symbols are displayed. It is possible to prevent the gaming state from occurring at the same time.

  Subsequently, the CPU 103 determines whether or not the first certainty change confirmation flag is on (step S323), and when it is on (step S323; Yes), clears the first certainty confirmation flag. The probability changing flag is set to the ON state (step S324). Further, a count initial value that is a variable display count initial value during probability variation is set in the probability variation counter 117 (step S325). Here, the initial value of the variable display count during probability change is the initial value (for example, “100”) of the remaining number of special figure games that can be executed in a high probability state.

  On the other hand, when the first certainty change confirmation flag is off in the process of step S323 (step S323; No), the certainty changing flag is cleared and turned off, and the certainty counter 117 is cleared and the count value is set to “ It is initialized to “0” (step S326). That is, when the big hit gaming state based on the normal big hit is reached, the high probability state ends and the normal gaming state is restored. Then, the value of the first special symbol process flag is updated to “0” (step S327).

  Here, in this embodiment, when the big hit is not accompanied by a probability fluctuation, the probability changing flag is cleared at the end of the big hit, but when the big hit is started, the probability changing flag is always set once. It is cleared, and at the end of the big hit, it is determined whether or not the big hit is accompanied by a probability fluctuation, and if the result of the determination is accompanied, the probability changing flag may be set again.

  FIG. 30 is a flowchart showing the second special symbol process executed in step S16. When the first special symbol process is started, the CPU 103 first detects whether or not the game ball has won the second normal variable winning ball device 62 by detecting the second starting ball included in each winning opening switch 70. The determination is made by checking a detection signal input from the switch, an input state flag provided in the flag memory 118, or the like (step S121). When the game ball is won and the detection signal from the second starting ball detection switch is turned on (step S121; Yes), the second winning process is executed (step S122). On the other hand, if the game ball has not won (step S121; No), the second winning process is skipped.

  FIG. 31 is a flowchart showing the second winning process in step S122. In the second winning process, the CPU 103 first determines whether or not the starting winning memory number stored in the second special figure holding memory 112 is the maximum value of 4 (step S401).

  When the start winning memory number is 4 (step S401; Yes), the start detection by the current winning is invalidated, and the second winning process is finished as it is. On the other hand, when the starting winning memory number is less than 4 (step S401; No), the starting winning memory number of the second special figure holding memory 112 is incremented by 1 (step S402), and the value of the random R1 is calculated from the random counter 113. Extraction (step S403), and the value of the extracted random R1 is set to the head of the empty entry in the second special figure reservation memory 112 (step S404). At this time, the second start-winning memory, such as turning on one of the LEDs that is turned off in the second start-up winning memory display 46 (for example, the leftmost LED among the LEDs that are turned off). Lighting control of the display 46 is performed.

  Thereafter, the CPU 103 selects one of nine processes of steps S130 to S138 shown in FIG. 30 based on the value of the second special symbol process flag provided in the flag memory 118. Below, each process of step S130-S138 is demonstrated.

  The second special symbol normal process of step S130 is a process executed when the value of the first special symbol process flag is the initial value “0”. In this process, the CPU 103 determines whether or not the number of reserved memories stored in the second special figure reservation memory 112 is “0”. Here, in the second special figure reservation memory 112, when various data such as a random number value corresponding to the reservation number “1” is not stored, it is determined that the number of stored storage is “0”. If the number of reserved memories is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the fourth variable display device 44 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the second special symbol process flag is updated to “1” which is a value corresponding to the second jackpot determination process.

  The second jackpot determination process in step S131 is a process executed when the value of the second special symbol process flag is “1”. In this process, as shown in FIG. 32, the CPU 103 first reads the value of the random R1 stored in correspondence with the hold number “1” from the second special figure hold memory 112 (step S421). At this time, 1 is subtracted from the reserved memory number, and the random R1 value stored in the second to fourth entries (holding numbers “2” to “4”) of the second special figure holding memory 112 is set to one entry. The information is shifted up one by one (step S422).

  Subsequently, the CPU 103 determines whether or not the probability improvement state (probability change is in progress) (step S423). If the probability change is not in progress (step S423; No), the CPU 103 determines that the game state is normal and the second A normal big hit determination table 120 as shown in FIG. 6A is set as a table for determining whether or not the display result of the special figure game by the variable display device 42 is a big hit (step S424). On the other hand, if the probability change is in progress (step S423; Yes), the probability change big hit determination table 121 as shown in FIG. 6B is set (step S425).

  The CPU 103 uses the jackpot determination table 120 or 121 set in the process of step S424 or S425 based on the value of the random R1 read out in the process of step S421, and the special game by the second variable display device 42. It is determined whether or not the display result is a big hit (step S426). If it is determined to be a big hit (step S426; Yes), the second big hit state flag provided in the flag memory 118 is set to the on state (step S427), and it is determined to be lost. In such a case (step S426; No), the second big hit state flag is cleared and turned off (step S428). Thereafter, the value of the second special symbol process flag is updated to “2” which is a value corresponding to the second determined symbol determination process (step S429).

  The second determined symbol determination process in step S132 shown in FIG. 30 is a process executed when the value of the second special symbol process flag is “2”. In this process, as shown in FIGS. 33 and 34, the CPU 103 first determines whether or not the second big hit state flag provided in the flag memory 118 is on (step S431). When the second big hit state flag is OFF (step S431; No), the value of the random R2 is extracted from the random counter 113 (step S432), and it is determined whether or not to reach (step S433). For example, when the value of the random R2 extracted in the process of step S432 is any one of “105” to “1530”, it is determined not to reach, and when it is any one of “0” to “104”. And decide to reach. Further, a table having different random R2 values to be reached depending on whether or not the probability changing flag provided in the flag memory 118 is on is prepared, and the table selected according to the state of the probability changing flag. It may be determined whether or not to reach by using.

  When it is determined not to reach in the process of step S433 (step S433; No), the CPU 103 clears the second reach state flag provided in the flag memory 118 and sets it to the off state (step S434). Then, based on the value of the random R4-1 extracted from the random counter 113, the second left determined symbol is determined using the second left symbol determining table 142 shown in FIG. 8C (step S435). Further, based on the value of the random R4-2 extracted from the random counter 113, the second medium determined symbol is determined using the second medium symbol determining table 143 shown in FIG. 8D (step S436). Based on the value of the random R4-3 extracted from the random counter 113, the second right determined symbol is determined using the second right symbol determining table 144 shown in FIG. 8E (step S437). Thereafter, the process proceeds to step S451.

  Further, when it is determined to reach in the process of step S433 (step S433; Yes), the CPU 103 sets the second reach state flag to the on state (step S438), and the random number extracted from the random counter 113 is set. Based on the value of R4-1, the second left symbol determination is determined using the second left symbol determination table 142 (step S439). Further, it is determined that the special symbol having the same symbol number as the first left determined symbol is set as the second right determined symbol (step S440), and any special symbol different from the second left / right determined symbol is determined. To be the first medium-determined symbol (step S441). Thereafter, the process proceeds to step S451.

  When it is determined in the process of step S431 that the big hit state flag is on (step S431; Yes), the CPU 103 extracts the value of random R5 from the random counter 113 (step S442), and the big hit gaming state is ended. After that, it is determined whether or not to perform probability variation control for shifting to the probability improvement state (step S443). For example, when the value of the random R5 extracted from the random counter 113 is an odd number, it is determined that the probability variation control is performed, and when it is an even number, it is determined that the probability variation control is not performed.

  When it is determined in the process of step S443 that the probability variation control is not to be performed (step S443; No), the CPU 103 clears the second probability change confirmation flag provided in the flag memory 113 and sets the off state (step S444). ), A second normal jackpot symbol determination table 140 shown in FIG. 8A is set as a table for determining the fixed symbol of the special symbol that is a variable display result of the jackpot (step S445). When it is determined that the probability variation control is to be performed in the process of step S443 (step S443; Yes), the second probability variation flag is set to the on state (step S446), and the fixed symbol of the special symbol is determined. As a table for this purpose, the second probability variation big hit symbol determination table 141 shown in FIG. 8B is set (step S447).

  After executing the process of step S445 or S447, the CPU 103 extracts the value of the random R4-1 from the random counter 113 (step S448), and performs the process of step S445 or S447 based on the extracted value of the random R4-1. Using the symbol determination table 140 or 141 set in the above, the determined symbol for big hit that is the same for the left, middle and right is determined (step S449).

  Then, the second left / middle / right symbol designation commands C0XX (h), C1XX are set by, for example, setting control data corresponding to the confirmed symbol of the special symbol determined in step S449 in a predetermined command transmission table. (H) and C2XX (h) are set to be sendable to the display control board 12 (step S450). Thereafter, the CPU 103 updates the value of the second special symbol process flag to “3”, which is a value corresponding to the second variable display pattern setting process, and ends the second determined symbol determination process (step S1). S451).

  The second variable display pattern setting process of step S133 shown in FIG. 30 is a process executed when the value of the second special symbol process flag is “3”. In this process, as shown in FIG. 35, the CPU 103 first determines whether or not the second big hit state flag provided in the flag memory 118 is on (step S461). When the second big hit state flag is OFF (step S461; No), it is determined whether or not reach is determined in the second determined symbol determination process in step S132 (step S462).

  When not reaching (step S462; No), the second normal loss variable display pattern determination table 160 shown in FIG. 10A is set as a table for selecting the variable display pattern (step S463). On the other hand, in the case of reaching (step S462; Yes), a second reach / losing variable display pattern determination table 161 shown in FIG. 10B is set as a table for selecting a variable display pattern. (Step S464).

  When the second big hit state flag is ON in the process of step S461 (step S461; Yes), the second big hit time variable shown in FIG. 10C is used as a table for selecting the variable display pattern. The display pattern determination table 162 is set (step S465).

  Subsequently, the CPU 103 extracts the value of the random R3 (step S465), and based on the extracted value of the random R3, from the variable display pattern determination table set in the process of steps S463, S464, or S465. Then, a variable display pattern to be used in this special figure game is determined (step S467).

  After that, the CPU 103 sets the control data corresponding to the variable display pattern determined in step S467 in a predetermined command transmission table, and the like, and then sends the second variable display start command A1XX (h) to the display control board. 12 is set to be sendable (step S468). Then, the variable display of the special symbol is started by the second variable display device 42 (step S469), and the total variable display time corresponding to the variable display pattern is displayed in the second variable display provided in the variable display time timer 119. The time timer is set (step S470). Thereafter, the CPU 103 updates the value of the second special symbol process flag to “4”, which is a value corresponding to the second variable display control process (step S471).

  The second variable display control process of step S134 shown in FIG. 30 is a process executed when the value of the second special symbol process flag is “4”. In this process, as shown in FIG. 36, the CPU 103 first determines whether or not the second variable display time timer stop flag provided in the flag memory 118 is turned on (step S491). When the second variable display time timer stop flag is off (step S491; No), the timer value is updated by subtracting 1 from the timer value of the second variable display time timer (step S492).

  Then, it is determined whether or not the timer value of the updated second variable display time timer is “0” (step S493). When the timer value of the second variable display time timer becomes “0” (step S493; Yes), the value of the second special symbol process flag is a value corresponding to the variable display stop time process “5”. (Step S494). On the other hand, when it is determined in step S493 that the timer value of the second variable display time timer is other than “0” (step S493; No), the second special symbol process flag is not updated. 1 variable display control processing is terminated.

  When the second variable display time timer stop flag is turned on in the process of step S491 (step S491; Yes), the processes of steps S492 to S494 are skipped and the second variable display control process is performed as it is. Exit. Thereby, the countdown of the timer value of the second variable display time timer can be stopped until the second variable display time timer stop flag is turned on again after being turned on. As a result, the second variable display time timer can be stopped. While the variable display of the special symbol by the device 42 is continued, the variable display time of the special symbol can be extended.

  The second variable display stop process in step S135 shown in FIG. 30 is a process executed when the value of the second special symbol process flag is “5”. In this process, as shown in FIG. 37, the CPU 103 first displays and displays the fixed symbol of the special symbol on the second variable display device 42, and displays the variable symbol of the special symbol on the second variable display device 42. Upon completion (step S501), settings are made to send the second decorative symbol determination command D100 (h) from the main board 11 to the display control board 12 (step S502). Specifically, the control data corresponding to the second decorative symbol determination command D100 (h) is set in a predetermined command transmission table, and the second decorative symbol determination command D100 (h) is displayed on the display control board. 12 is set to be sendable. The CPU 103 transmits one or more commands set in the command transmission table to the display control board 12 in a subsequent command control process (step S19).

  Subsequently, the CPU 103 determines whether or not the second big hit state flag provided in the flag memory 118 is on (step S503). When the second big hit state flag is off (step S503; No), it is subsequently determined whether or not the probability changing flag provided in the flag memory 118 is on (step S504). When the probability changing flag is off (step S504; No), the process proceeds to step S510.

  On the other hand, when the probability change flag is on (step S504; Yes), it is further determined whether or not the probability change end flag provided in the flag memory 118 is on (step S505). When the probability variation end flag is on (step S505; Yes), after the probability variation flag and the probability variation end flag are cleared and turned off, the probability variation counter 117 is cleared and the count value is initialized to “0”. (Step S506), the process proceeds to Step S510.

  On the other hand, when the probability variation end flag is off (step S505; No), the count value of the probability variation counter 117 is decremented by 1 (step S507), and it is determined whether or not the count value of the probability variation counter 117 is “0”. (Step S508). When the count value of the probability variation counter 117 is not “0” (step S508; No), the process proceeds to step S510.

  On the other hand, when the count value of the probability variation counter 117 is “0” (step S508; Yes), the probability variation flag is cleared (step S509). Thereafter, the CPU 103 updates the value of the second special symbol process flag to “0” (step S510).

  Further, when the second big hit state flag is on in the process of step S503 (step S503; Yes), the first variable display time timer stop flag provided in the flag memory 118 is set to the on state ( After that, the value of the second special symbol process flag is updated to “6” that is a value corresponding to the second pre-opening process for the special winning opening (step S512).

  The second big winning opening opening pre-processing in step S136 shown in FIG. 30 is a process executed when the value of the second special symbol process flag is “6”. In this process, the CPU 103 performs setting for starting control for opening the second special variable winning ball device 72 as a big winning opening. Then, the control for opening the second special variable winning ball apparatus 72 is started, and the value of the second special symbol process flag is updated to “7” which is a value corresponding to the second big winning opening opening process. To do.

  The second big prize opening opening process of step S137 is a process executed when the value of the second special symbol process flag is “7”. In this process, the CPU 103 performs display control commands for detecting the winning of a game ball to the opened second special variable winning ball device 72, giving a prize ball, measuring the opening time, and displaying the round number of the opening cycle. Make settings. Then, for example, the number of opening of the second special variable winning ball device 72 is counted for one big hit, and if the number of opening reaches, for example, 16 times, the condition for ending the specific gaming state (big hit gaming state) Is completed, the value of the second special symbol process flag is updated to “8”, which is a value corresponding to the jackpot end process. On the other hand, if the number of opening times has not reached 16, the second special variable winning ball apparatus 72 is once closed and then opened again after a predetermined time has elapsed.

  The second jackpot end process in step S138 is a process executed when the value of the second special symbol process flag is “8”. In this process, as shown in FIG. 38, the CPU 103 first ends the jackpot gaming state by making a setting for sending a jackpot end command E000 (h) to the display control board 12 ( In step S521), the second big hit state flag and the first variable display time timer stop flag provided in the flag memory 118 are cleared and turned off (step S522). Thereby, the countdown of the timer value of the first variable display time timer provided in the flag memory 118 is resumed.

  Thus, the first variable display time timer stop flag is in the ON state from the second variable display stop time process in step S135 to the second jackpot end process in step S138. In the display device 41, after the big hit symbol is derived and displayed on the second variable display device 42 to be in the big hit gaming state, the display display of the display result is restricted until the big hit gaming state is ended. As a result, during the continuation of the big hit gaming state based on the fact that the big variable symbol is derived and displayed on the second variable display device 42, the big variable symbol is also derived and displayed on the first variable display device 41. It is possible to prevent the gaming state from occurring at the same time.

  Subsequently, the CPU 103 determines whether or not the second certainty change confirmation flag is on (step S523), and when it is on (step S523; Yes), the second certainty change confirmation flag is cleared. The probability changing flag is set to the ON state (step S524). Further, the count initial value that is the initial value of the variable display count during probability variation is set in the probability variation counter 117 (step S525). Here, the initial value of the variable display count during probability change is the initial value (for example, “100”) of the remaining number of special figure games that can be executed in a high probability state.

  On the other hand, when the second certainty change confirmation flag is off in the process of step S523 (step S523; No), the certainty changing flag is cleared and turned off, and the certainty counter 117 is cleared and the count value is set to “ It is initialized to “0” (step S526). That is, when the big hit gaming state based on the normal big hit is reached, the high probability state ends and the normal gaming state is restored. Then, the value of the second special symbol process flag is updated to “0” (step S527).

  Next, the operation in the display control board 12 will be described. FIG. 39 is a flowchart showing a display control main process executed by the display control CPU 202 mounted on the display control board 12. When the display control main process is started, first, a predetermined initialization process is executed to clear the RAM 204, set various initial values, and initialize a 33 millisecond timer for determining the display control activation interval. This is performed (step S31).

  Thereafter, the CPU 202 monitors a timer interrupt flag provided in the flag memory 214, and executes a loop process until the timer interrupt flag is set (step S32; No). In this embodiment, a timer interrupt occurs every 33 milliseconds in the CPU 202, and when this timer interrupt occurs, a predetermined timer interrupt process is executed, so that a timer interrupt flag provided in the flag memory 214 is obtained. Is set.

  In the CPU 202, an interrupt for receiving a display control command from the main board 11 is generated separately from the timer interrupt generated every 33 milliseconds. This interrupt is an interrupt that occurs when the display control INT signal from the main board 11 is turned on. When an interrupt occurs due to the display control INT signal being turned on, the CPU 202 automatically sets the interrupt disabled state. However, if a CPU that does not automatically enter the interrupt disabled state is used, the CPU 202 It is preferable to issue an insertion prohibition instruction (DI instruction).

  When the display control INT signal from the main board 11 is turned on, an interruption occurs in the CPU 202, so that the CPU 202 reads data from an input port assigned to input of display control command data. Then, MODE data and EXT data of a display control command having a 2-byte structure are sequentially received, and the received command is stored in a predetermined reception command buffer. In this way, the display control command transmitted from the main board 11 is stored in the reception command buffer, while the occurrence of the timer interrupt is confirmed in step S32 shown in FIG. When the occurrence of this timer interrupt is confirmed (step S32; Yes), the CPU 202 clears the timer interrupt flag provided in the flag memory 214 and turns it off, and then executes a command analysis process. The received display control command is analyzed (step S33).

  When the command analysis process ends, the CPU 202 executes a counter update process for updating the random R10 counted by the random counter 210 (step S34), and then performs the first decorative symbol display control process process (step S35) and the first process. The decorative pattern display control process process 2 (step S36) is sequentially executed. In the first decorative symbol display control process, a first display control process flag provided in the flag memory 214 in order to control the display operation in the first variable display device 41 in a predetermined order according to the display state. The corresponding process is selected and executed according to the value of. Further, in the second decorative design control process, a process corresponding to the value of the second display control process flag in order to control the display operation in the second variable display device 42 in a predetermined order according to the display state. Is selected and executed. When the first and second decorative symbol display control process processes are completed, the process returns to the process of step S32.

  40 and 41 are flowcharts showing the command analysis processing in step S33. When the command analysis process is started, the CPU 202 first checks whether or not there is a display control command received from the main board 11 (step S601). For example, when it is confirmed that there is a received command because the received command is stored in the received command buffer (step S601; Yes), the received command is read (step S602). It is determined whether or not the middle / right symbol designation commands B0XX (h), B1XX (h), and B2XX (h) (step S603).

  If the received command read in the process of step S602 is the first left / middle / right symbol designation command B0XX (h), B1XX (h) and B2XX (h) (step S603; Yes), the EXT of the command The data is stored in the first left / middle / right symbol storage area for decorative symbols secured in the RAM 204 (step S604), and the first valid flag provided in the flag memory 214 is set to the on state (step S604). Step S605). The EXT data of the first left / middle / right symbol designation commands B0XX (h), B1XX (h), and B2XX (h) is data indicating the symbol number of the decorative symbol. On the other hand, when the received command read in the process of step S602 is not the first left / middle / right symbol designation command B0XX (h), B1XX (h) and B2XX (h) (step S603; No) Then, it is determined whether or not the command is the second left / middle / right symbol designation command C0XX (h), C1XX (h) and C2XX (h) (step S606).

  If the received command read in the process of step S602 is the second left / middle / right symbol designation C0XX (h), C1XX (h), and C2XX (h) (step S606; Yes), the EXT data of the command Are stored in the second left / middle / right symbol storage area for decorative symbols secured in the RAM 204 (step S607), and the second valid flag provided in the flag memory 214 is set to ON (step S607). S608). The EXT data of the second left / middle / right symbol designation commands C0XX (h), C1XX (h) and C2XX (h) is data indicating the symbol number of the decorative symbol. On the other hand, when the received command read in step S602 is not the second left / middle / right symbol designation C0XX (h), C1XX (h) and C2XX (h) (step S606; No), the command It is determined whether or not the command is the first variable display start command 90XX (h) (step S609).

  If the received command read in the process of step S602 is the first variable display start command 90XX (h) (step S609; Yes), the first variable display pattern storage in which the EXT data of the command is secured in the RAM 204 is stored. The area is stored and saved (step S610), and the first variable display start reception flag provided in the flag memory 214 is set to an on state (step S611). On the other hand, when the received command read in step S602 is not the first variable display start command 90XX (h) (step S609; No), the command is the second variable display start command 91XX (h). It is determined whether or not there is (step S612).

  If the received command read in the process of step S602 is the second variable display start command 82XX (h) (step S612; Yes), the second variable display pattern storage in which the EXT data of the command is secured in the RAM 204 is stored. The area is stored and saved (step S613), and the second variable display start reception flag provided in the flag memory 214 is set to the on state (step S614). When the received reception command is another display control command (for example, the first and second decorative symbol determination commands) (step S612; No), the command corresponding to the display control command received by the flag memory 214 The reception flag is set (step S615), and the process returns to the process of step S601.When all reception commands are read in this way (step S601; No), the command analysis process ends.

  FIG. 42 is a flowchart showing the first decorative symbol display control process in step S35. In the first decorative symbol display control process, the CPU 202 performs seven processes of steps S620 to S626 shown in FIG. 42 based on the value of the first display control process flag provided in the flag memory 214. Choose one. Below, each process of step S620-S626 is demonstrated.

  The first variable display start command reception waiting process in step S620 is a process executed when the value of the first display control process flag is the initial value “0”. In this process, as shown in FIG. 43, the CPU 202 first determines whether or not the first variable display start flag provided in the flag memory 214 is set (step S701). In the command analysis process described above, when the first variable display start command A0XX (h) that can specify the variable display time is read from the reception command buffer, the first variable display start flag is set.

  When the first variable display start flag is not set (step S701; No), the first variable display control start command reception waiting process is ended as it is.

  When the first variable display start flag is set in the process of step S701 (step S701; Yes), the value of the first display control process flag is a value corresponding to the display control setting process “1”. (Step S702).

  The first display control setting process in step S621 is a process executed when the value of the first display control process flag is “1”. In this process, the CPU 202 selects and determines a symbol display control pattern corresponding to the variable display pattern saved in the variable display pattern storage area of the RAM 204, and reads it from the symbol display control pattern table 220. Then, the value of the first display control process flag is updated to “2” which is a value corresponding to the first variable display start pre-processing.

  The first variable display start pre-process in step S622 is a process executed when the value of the first display control process flag is “2”. In this process, the CPU 202 sends a command to the GCL 205 and causes the variable display unit of the third variable display device 43 to display the decorative symbol in a mode of gradually accelerating to start variable display of the decorative symbol. In addition, the count initial value corresponding to the total variable display time corresponding to the variable display pattern is set in the third variable display time timer included in the various timers 215 to start the countdown operation, thereby measuring the variable display time. To start. Then, the value of the first display control process flag is updated to “3” which is a value corresponding to the first variable display processing.

  The first variable display in-process in step S623 is a process executed when the value of the first display control process flag is “3”. In this process, first, as shown in FIG. 44, the CPU 202 first determines whether or not the third variable display time timer stop flag provided in the flag memory 214 is on (step S711). When the third variable display time timer stop flag is off (step S711; No), the timer value is updated by subtracting 1 from the timer value of the third variable display time timer (step S712).

  Then, it is determined whether or not the timer value of the updated third variable display time timer is “0” (step S713). When the timer value of the third variable display time timer becomes “0” (step S713; Yes), a predetermined count initial value is set for the first monitoring timer included in the various timers 215. (Step S714), the countdown of the first monitoring timer is started, and the value of the first display control process flag is updated to “4” which is a value corresponding to the first decorative symbol stop waiting process ( Step S715). On the other hand, when it is determined in step S713 that the timer value of the third variable display time timer is other than “0” (step S713; No), the first display control process flag is not updated. The process during variable display 1 is terminated.

  When the third variable display time timer stop flag is turned on in step S711 (step S711; Yes), the processing in steps S712 to S715 is skipped and the first variable display in-process is performed as it is. Exit. Thereby, the countdown of the timer value of the third variable display time timer can be stopped until the third variable display time timer stop flag is turned on again after being turned on. As a result, the third variable display time timer can be stopped. The variable display time of the decorative symbol by the device 43 can be extended in the same manner as the variable display time of the special symbol by the first variable display device 41. In addition, when the count of the third variable display time timer is stopped (step S711; Yes), there is a step of combining and displaying a message for notifying that to the variable display of the decorative symbol. Also good.

  The first decorative symbol stop waiting process of step S624 shown in FIG. 42 is a process executed when the value of the first display control process flag is “4”. In this process, as shown in FIG. 45, first, the CPU 202 determines whether or not the first decorative symbol determination command D000 (h) transmitted from the main board 11 has been received as a display control command (step S721). ). The first decorative symbol determination command D000 (h) is a command that is prepared for transmission in the above-described step S302 and then transmitted in step S19. When the first decorative symbol determination command D000 (h) has not been received (step S721; No), it is determined whether or not the first monitoring timer has timed out (step S722). S722; No), the first decorative symbol stop waiting process is finished as it is.

  On the other hand, when the first monitoring timer times out (step S722; Yes), the CPU 202 determines that some abnormality has occurred, and performs control to display a predetermined error screen on the third variable display device 43. (Step S723). Thereafter, the process proceeds to step S727.

  When it is determined in step S721 that the first decorative symbol determination command has been received (step S721; Yes), the CPU 202 variably displays the decorative symbol being executed by the third variable display device 43. Is performed, and the control of stopping and displaying the confirmed symbols in each symbol is performed (step S724), and it is determined whether or not the display result of each symbol is a big hit which is a specific display result (step S725). When it is not a big hit (step S725; No), the process proceeds to step S727. When a big hit is made (step S725; Yes), the fourth variable display time timer stop flag provided in the flag memory 214 is turned on. Set (step S726). Thereafter, the CPU 202 proceeds to the process of step S728.

  In the process of step S727, the CPU 202 updates the value of the first display control process flag to “0” and ends the first decorative symbol stop waiting process. In step S728, the value of the first display control process flag is updated to “5”, which is a value corresponding to the first jackpot display process, and the first decorative symbol stop waiting process ends.

  The first jackpot display process in step S625 of FIG. 42 is a process executed when the value of the first display control process flag is “5”. In this process, the CPU 202 controls the third variable display device 43 to display an image corresponding to the big hit gaming state. For example, the number of rounds corresponding to a predetermined jackpot round number command sent from the main board 11 is displayed on the third variable display device 43 so that the player can be notified. When the round game executed in the big hit gaming state becomes the final round (for example, the 16th round), the value of the first display control process flag is set to “6” which is a value corresponding to the first big hit end display process. Update.

  The first jackpot end display process in step S626 is a process executed when the value of the first display control process flag is “6”. In this process, as shown in FIG. 46, the CPU 202 first ends the jackpot gaming state in the third variable display device 43 in response to receiving the jackpot end command E000 (h) from the main board 11. An effect display for informing the user of the fact is controlled (step S731). In addition, the CPU 202 clears the fourth variable display time timer stop flag provided in the flag memory 214 and turns it off (step S732). Thereby, the countdown of the timer value of the fourth variable display time timer provided in the flag memory 214 is resumed. Then, when the effect display for notifying that the big hit gaming state has ended, the value of the first display control process flag is updated to “0” (step S733).

  FIG. 47 is a flowchart showing the second decorative symbol display control process in step S36. In the second decorative symbol display control process, the CPU 202 selects one of the seven processes of steps S630 to S636 based on the value of the first display control process flag provided in the flag memory 214. To do. Below, each process of step S630-S636 is demonstrated.

  The second variable display start command reception waiting process in step S630 is a process executed when the value of the second display control process flag is the initial value “0”. In this process, as shown in FIG. 48, the CPU 202 first determines whether or not the second variable display start flag provided in the flag memory 214 is set (step S801). In the command analysis process described above, when the second variable display start command A1XX (h) that can specify the variable display time is read from the reception command buffer, the second variable display start flag is set.

  When the second variable display start flag is not set (step S801; No), the first variable display control start command reception waiting process is ended as it is.

  When the second variable display start flag is set in the process of step S801 (step S801; Yes), the value of the second display control process flag is a value corresponding to the display control setting process “1”. To "" (step S802).

  The second display control setting process in step S631 of FIG. 47 is a process executed when the value of the second display control process flag is “1”. In this process, the CPU 202 selects and determines a symbol display control pattern corresponding to the variable display pattern saved in the variable display pattern storage area of the RAM 204, and reads it from the symbol display control pattern table 220. Then, the value of the second display control process flag is updated to “2”, which is a value corresponding to the second variable display start pre-processing.

  The second variable display start pre-processing in step S632 of FIG. 47 is a process executed when the value of the second display control process flag is “2”. In this process, the CPU 202 sends a command to the GCL 205 and causes the variable display unit of the fourth variable display device 44 to display the decorative symbols in a manner that gradually accelerates, thereby starting the variable display of the decorative symbols. In addition, the count initial value corresponding to the total variable display time corresponding to the variable display pattern is set in the fourth variable display time timer included in the various timers 215 to start the countdown operation, thereby measuring the variable display time. To start. Then, the value of the second display control process flag is updated to “3” which is a value corresponding to the second variable display processing.

  The second variable display process in step S633 of FIG. 47 is a process executed when the value of the second display control process flag is “3”. In this process, first, as shown in FIG. 49, the CPU 202 first determines whether or not the fourth variable display time timer stop flag provided in the flag memory 214 is turned on (step S811). When the fourth variable display time timer stop flag is OFF (step S811; No), the timer value is updated by subtracting 1 from the timer value of the fourth variable display time timer (step S812).

  Then, it is determined whether or not the timer value of the updated fourth variable display time timer is “0” (step S813). When the timer value of the fourth variable display time timer becomes “0” (step S813; Yes), a predetermined count initial value is set for the second monitoring timer included in the various timers 215. (Step S814), the countdown of the second monitoring timer is started, and the value of the second display control process flag is updated to “4” which is a value corresponding to the second decorative symbol stop waiting process ( Step S815). On the other hand, when it is determined in step S813 that the timer value of the fourth variable display time timer is other than “0” (step S813; No), the second display control process flag is not updated. 2 variable display in-process is terminated.

  When the fourth variable display time timer stop flag is turned on in step S811 (step S811; Yes), the processing in steps S812 to S815 is skipped and the second variable display in-process is performed as it is. Exit. As a result, the countdown of the timer value of the fourth variable display time timer can be stopped until the fourth variable display time timer stop flag is turned on again after being turned on. As a result, the fourth variable display time timer can be stopped. The variable display time of the decorative symbol by the device 44 can be extended in the same manner as the variable display time of the special symbol by the second variable display device 42. In addition, when the count of the fourth variable display time timer is stopped (step 8711; Yes), there is a step of combining and displaying a message for notifying that to the variable display of the decorative symbol. Also good.

  The second decorative symbol stop waiting process in step S634 of FIG. 47 is a process executed when the value of the second display control process flag is “4”. In this process, as shown in FIG. 50, first, the CPU 202 determines whether or not the second decorative symbol determination command D100 (h) transmitted from the main board 11 has been received as a display control command (step S821). ). The second decorative symbol determination command D000 (h) is a command that is prepared for transmission in the above-described step S502 and then transmitted in step S19. When the second decorative symbol determination command D100 (h) has not been received (step S821; No), it is determined whether or not the second monitoring timer has timed out (step S822). S822; No), the second decorative symbol stop waiting process is finished as it is.

  On the other hand, when the second monitoring timer times out (step S822; Yes), the CPU 202 determines that some abnormality has occurred, and performs control to display a predetermined error screen on the fourth variable display device 44. (Step S823). Thereafter, the process proceeds to step S827.

  When it is determined in step S821 that the second decorative symbol determination command has been received (step S821; Yes), the CPU 202 variably displays the decorative symbol being executed by the fourth variable display device 44. Is terminated, and the control for stopping and displaying the fixed symbol in each symbol is performed (step S824), and it is determined whether or not the display result of each symbol is a big hit which is a specific display result (step S825). When it is not a big hit (step S825; No), the process proceeds to step S827. When a big hit is made (step S825; Yes), the third variable display time timer stop flag provided in the flag memory 214 is turned on. Set (step S826). Thereafter, the CPU 202 proceeds to the process of step S828.

  In the process of step S827, the CPU 202 updates the value of the second display control process flag to “0”, and ends the second decorative symbol stop waiting process. In step S828, the value of the second display control process flag is updated to “5”, which is a value corresponding to the second jackpot display process, and the second decorative symbol stop waiting process ends.

  The second jackpot display process in step S635 of FIG. 47 is a process executed when the value of the second display control process flag is “5”. In this process, the CPU 202 controls the fourth variable display device 44 to display an image corresponding to the big hit gaming state. For example, the number of rounds corresponding to a predetermined jackpot round number command sent from the main board 11 is displayed on the fourth variable display device 44 so that the player can be notified. Then, when the round game executed in the big hit gaming state becomes the final round (for example, the 16th round), the value of the second display control process flag is set to “6” which is a value corresponding to the second big hit end display process. Update.

  The second jackpot end display process in step S636 of FIG. 47 is a process executed when the value of the second display control process flag is “6”. In this process, as shown in FIG. 51, the CPU 202 first ends the big hit gaming state in the fourth variable display device 44 in response to receiving the big hit end command E000 (h) from the main board 11. An effect display for informing the user that the event has been made is controlled (step S831). In addition, the CPU 202 clears the third variable display time timer stop flag provided in the flag memory 214 and turns it off (step S832). Thereby, the countdown of the timer value of the third variable display time timer provided in the flag memory 214 is resumed. Then, when the effect display notifying that the big hit gaming state has ended, the value of the second display control process flag is updated to “0” (step S833).

Subsequently, a display control example for controlling the display operation in each of the variable display devices 41 to 44 will be described.
Here, after the first variable display device 41 starts a special figure game with a display result as a normal big hit, the second variable display device 42 starts a special figure game with a display result as a probable big hit. An example of display control in the case of failure will be described.

  FIG. 52 is a timing chart showing an example of display operation in each of the variable display devices 41 to 44 in this case, and FIG. 53 is a diagram showing variable display modes of special symbols and decorative symbols in each of the variable display devices 41 to 44. is there.

  In this display control example, the variable display pattern # 21 (reach A normal big hit) is selected and determined as the variable display pattern used in the special figure game by the first variable display device 41. The CPU 103 of the main board 11 starts the variable display of the special symbol by the first variable display device 41 and sends the first variable display start command A0XX (h) to the display control board 12 (step S281). . At this time, the CPU 103 starts accelerating display by the process a for the special symbols displayed on the left, middle and right variable display portions of the first variable display device 41 according to the selected variable display pattern # 21. Let Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  Then, the CPU 202 of the display control board 12 responds to the reception of the first variable display start command A0XX (h) sent from the main board 11 (FIG. 43, step S701; Yes), to the GCL 205. The third variable display device 43 starts variable display of decorative symbols by sending a predetermined drawing command or the like (step S622). At this time, the GCL 205 executes image processing in accordance with the drawing command from the CPU 202, and applies the process a to the decorative symbols displayed on the left, middle, and right variable display portions of the third variable display device 43. Start accelerating display. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  Thereby, in the first variable display device 41, as shown in FIGS. 53A and 53B, at the timing t10, variable display of the special symbol that has been stopped is started, and the third variable display device 41 is started. In the display device 43, variable display of the decorative symbols that have been stopped is started.

  Thereafter, during the variable display of the special symbol by the first variable display device 41, the game ball wins the second variable winning ball device 62, and the start winning memory number of the second special symbol holding memory 112 is the maximum value. When 4 is reached, a second notification effect end command 9100 (h) is sent to the display control board 12.

  Then, in the processes of steps S131 and S132, it is determined that the display result of the special figure game by the second variable display device 42 is a probable big hit (step S426; Yes, step S443; Yes), and the second variable. As the variable display pattern used in the special game by the display device 42, the variable display pattern # 21 (reach A big hit) is selected and determined.

  The CPU 103 of the main board 11 starts the variable display of the special symbol by the second variable display device 42 according to the variable display pattern # 21 selected and determined, and controls the display of the second variable display start command A1XX (h). Send out to the substrate 12. At this time, the CPU 103 starts the accelerated display by the process a on the special symbols displayed on the left, middle, and right variable display portions of the first variable display device 41 according to the variable display pattern selected and determined. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  In response to receiving the second variable display start command A1XX (h) sent from the main board 11, the CPU 202 of the display control board 12 sends a predetermined drawing command to the GCL 205, etc. In the fourth variable display device 44, a predetermined drawing command is sent to the GCL 205, and the fourth variable display device 44 starts variable display of decorative symbols (step S632). At this time, the GCL 205 executes image processing in accordance with a drawing command from the CPU 202, and applies the process a to the decorative symbols displayed on the left, middle, and right variable display portions of the fourth variable display device 44. Start accelerating display. Then, when all symbols are accelerated to a predetermined speed by the process a, a constant speed display by the process b is performed.

  Thereby, in the second variable display device 42, as shown in FIG. 53C, the special symbol variable display is started at the timing t11, and in the fourth variable display device 44, the decorative symbol variable display is performed. Be started. Thereafter, the first variable display device 41 and the third variable display device 43 perform temporary stop display in the order of the left symbol and the right symbol as shown in FIGS. 53 (D) and 53 (E).

  Then, at timing t12 after the total variable display time T20 from timing t10, the CPU 103 of the main board 11 ends the variable display of the special symbol by the first variable display device 41, and derives and displays the normal jackpot symbol (step). In step S301, the second decorative design determination command D1XX (h) is sent to the display control board 12 (step S302). In addition, the CPU 103 sets the second variable display time timer stop flag to ON, and stops the measurement of the special symbol variable display time by the second variable display device 42.

  On the other hand, at the timing t12, the CPU 202 of the display control board 12 causes the third variable display device 43 to derive and display the normal jackpot symbol and responds to the reception of the second decorative symbol determination command D1XX from the main substrate 11. Thus, the process c is displayed in a completely stopped state (step S724). Further, the CPU 103 sets the fourth variable display time timer stop flag to ON (step S726), and stops the measurement of the decorative symbol variable display time by the fourth variable display device 44.

  Thereby, as shown in FIG. 53 (F), the first jackpot symbol is displayed on the first variable display device 41 and the third variable display device 43, and the pachinko gaming machine 1 is shown in FIG. 53 (G). As shown in FIG. Meanwhile, in the second variable display device 42 and the fourth variable display device 44, the countdown of the timer value of the second variable display time timer and the timer value of the fourth variable display time timer is stopped, and the process The constant speed display by b continues to be executed. Further, as shown in FIG. 53G, the third variable display device 44 appropriately displays a display indicating that the measurement of the variation time is stopped (in the drawing, “Paused”).

  Then, at timing t13 when the big hit gaming state ends, the CPU 103 of the main board 11 sends a big hit end command E000 (h) to the display control board 12 (step S321). Further, the CPU 103 clears and turns off the second variable display time timer stop flag (step S322), and restarts the measurement of the special symbol variable display time by the second variable display device.

  On the other hand, the CPU 202 of the display control board 12 clears and turns off the fourth variable display time timer stop flag (step S732), and resumes the measurement of the special symbol variable display time by the fourth variable display device 44.

  Thereafter, the second variable display device 42 and the fourth variable display device 44 perform temporary stop display in the order of the left symbol and the right symbol as shown in FIGS. 53 (I) and (J). At timing t14, the CPU 103 of the main board 11 ends the variable display of the special symbol by the second variable display device 42, derives and displays the probability variation big hit symbol (step S501), and the second decorative symbol confirmation command. D1XX (h) is sent to the display control board 12 (step S502).

  Further, the CPU 202 of the display control board 12 responds to the fact that the fourth variable display device 44 derives and displays the probable big hit symbol at timing t14 and receives the second decorative symbol determination command D0XX from the main board 11. Thus, the process c is displayed in a completely stopped state (step S824).

  As a result, the second variable display device 42 and the fourth variable display device 44, as shown in FIG. 53 (K), display the probability variation big hit symbol, and the pachinko gaming machine 1 enters the big hit gaming state. Transition to the probability improvement state after completion.

  As described above, according to this embodiment, the random R1 used for the jackpot determination in the special game in the first variable display device 41 and the special game in the second variable display device 42 are used. The random R1 used for the big hit determination is acquired by the random counter 113 having the configuration shown in FIG. According to the random counter 113 having this configuration, the timing at which the output data of the first and second variable counters 1203 is latched with respect to the start winning signals SSA and SSB from the first and second ordinary variable winning ball devices 61 and 62 is determined. The output timings of the first latch signal SLA and the second latch signal SLB are adjusted so that they are always different. Therefore, in both special figure games, there is no problem that the same random number value is taken in or the random numbers are synchronized, and a big hit state is established with appropriate randomness, which can enhance the interest of the game. .

  When the jackpot symbol is derived and displayed on the second variable display device 42 during execution of variable display of the special symbol by the first variable display device 41, the CPU 103 determines the timer value of the first variable display time timer. When the countdown is stopped and the jackpot gaming state based on the fact that the jackpot symbol is derived and displayed, the timer value countdown is resumed. In this way, the CPU 103 continues the variable display of the special symbol on the first variable display device 41 until the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the second variable display device 42 is completed. Continue to extend the variable display time. As a result, a jackpot gaming state based on the fact that the first jackpot symbol is derived and displayed on the first variable display device 41, and a jackpot gaming state based on the jackpot symbol being derived and displayed on the second variable display device 42, , Can be prevented from occurring at the same time. For this reason, it is possible to prevent the player from having a strong impact and inciting significant euphoria.

  Further, until the variable display of the special symbol by the second variable display device 42 reaches the big hit state, the variable display of the special symbol by the first variable display device 41 is normally executed. It is difficult for the player to realize that the variable display in the game is a big hit, and it can enhance the interest.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible.

  For example, in the above embodiment, the first latch clock signal S2A and the second latch clock signal S2B are signals having the same cycle and a phase difference of 180 °, but the first and second latch clock signals S2A are different. As for the period and the duty between S2B and S2B, the rising of the latch clock signals SLA and SLB (latch timing signal) occurs only once during each period from when the counter 1203 updates the count value data to the next update. If so, it is optional.

  For example, the first latch clock signal S2A is set as shown in FIG. 55 (F), and the second latch clock signal S2B is set with a cycle, waveform, duty, etc. as shown in FIG. 55 (G). Also good.

  The method of generating the first and second latch clock signals S2A and S2B is arbitrary. For example, as shown in FIG. 54, a mask circuit 1211 and a quaternary counter 1212 are added to the circuit of FIG. This can be achieved.

  The mask circuit 1211 internally has a mask signal as shown in FIG. 55E according to the second count clock signal S2 shown in FIG. 55C from the reverse phase output (Q bar) of the count clock signal generation circuit 1202. When the mask signal is off, the gate is opened and the input signal S2 is output as it is. When the mask signal is on, the gate is closed and the output signal is clamped to a low level. As a result, FIG. This is a circuit for outputting the first latch clock signal S2A shown in (F).

  Further, the quaternary counter 1212 counts the falling edge of the first count clock signal S1 from the positive phase output (Q) of the count clock signal generation circuit 1202, and one clock every time four falling edges are counted. This is a circuit that outputs a high-level signal only for a period and, as a result, outputs a second latch clock signal S2B shown in FIG.

  Note that whether the first and second latch clock signals S2A and S2B are output is that both latch clock signals S2A and S2B are not output in duplicate during the period when the counter 1203 outputs one value. As a condition, the period and the ratio of the number of times of output are arbitrary.

  Further, in the circuit block diagrams of FIGS. 11 and 54, the output signals SSA and 22B of the start prize opening switches 70A and 70B are directly supplied to the CPU 103, the first latch signal output circuit 1204A, and the second latch signal output circuit 1204B. is doing. In such a configuration, the player does not feel distrust because no change is made to the start winning signal as a trigger for determining whether or not to win. However, with such a configuration, there is a possibility that the winning prize signal SSA or SSB may be erroneously determined as “winning” when the start winning signal SSA or SSB instantaneously becomes an active level (when a beard is generated). In order to prevent such a problem, for example, as shown in FIG. 56, a timer circuit 1177 is arranged, and only when the start winning signal SSA or SSB continues for a certain period, the CPU 103 or the first or second latch The start winning signal SSA or SSB may be supplied to the signal output circuit 1204A or 11204B.

  Specifically, the timer circuit 1177 shown in FIG. 56 uses the time when the start winning signal SSA or SSB is input from the start winning port switch 70A or 70B as an arbitrary clock signal from the reference clock signal generation circuit 1201. When the measured time reaches a predetermined time (for example, 3 ms), the start winning signal SSA or SSB is output to the CPU 103 and the first or second latch signal output circuit 1204A or 1204B.

  The timer circuit 1177 is constituted by, for example, an up counter or a down counter, and starts in response to a high level signal being input. The timer circuit 1177 up-counts or down-counts, for example, the reference clock signal S0 sequentially input from the clock signal generation circuit 1201 while the input is at a high level. When the count value obtained by counting up or down becomes, for example, a value corresponding to 3 ms, the timer circuit 1177 outputs the start winning signal SSA or SSB to the CPU 103 and the first or second latch signal output circuit 1204A or To 1204B.

  Further, for example, when the start winning signal SSA or SSB is continued for a certain time by the method shown in FIGS. 57 and 58, it may be determined that there has been a winning. First, as shown in FIG. 57A, in the RAM 102, a first start winning counter 1113A for counting the duration of the start winning signal SSA and a second for counting the duration of the starting winning signal SSB. The start winning counter 1113B is arranged.

Subsequently, in the switch process (step S11) of the game control interrupt process (timer interrupt process) shown in FIG. 20, if the start winning signal SSA is at a high level (active level), the first winning port switch counter 1113A is set. The count value is incremented by 1 (step S1001), and if the start winning signal SSA is at a low level (inactive level), the count value of the first winning port switch counter 1113A is reset (step S1002).
Further, if the start winning signal SSB is high level (active level), the count value of the second winning port switch counter 1113B is incremented by 1 (step S1003), and if the starting winning signal SSB is low level (inactive level). Then, the count value of the second winning opening switch counter 1113B is reset (step S1004).

  Then, as shown in FIG. 58A, in the first special symbol process shown in FIG. 21, is the count value of the first start winning counter 1113A, for example, 2 or more instead of step S101? Whether or not, that is, whether or not the start winning signal SSA has continued for a period of 2 interrupt processing (2 ms) is determined (step S101A), and only when it is determined that it is 2 or more (step S101A; Yes), step The first winning process of S102 is executed, and if it is less than 2 (step S101A; No), the winning process may be skipped.

  Similarly, as shown in FIG. 58 (B), in the second special symbol process shown in FIG. 30, instead of step S121, the count value of the second start winning counter 1113B is 2 or more, for example. Whether or not, that is, whether or not the start winning signal SSA has continued for two interruption processes (2 ms) (step S121A), and only when it is determined that it is 2 or more (step S121A; Yes), The first winning process in step S102 is executed, and if it is less than 2 (step S121A; No), the winning process may be skipped.

  Further, in the above embodiment, after the big hit symbol is derived and displayed on one of the first and second variable display devices 41 and 42 and the big hit gaming state is started, Until the end, the other variable display device displays the special symbol and the decorative symbol variably at a constant speed. However, the present invention is not limited to this, and during this time, the losing symbol may be temporarily displayed on the other variable display device.

  In this modification, the flag memory 118 of the game control microcomputer 100 includes first and second variable display pause flags, first and second variables instead of the first and second variable display time timer stop flags. Two temporary stop display flags and first and second variable display restart flags are provided.

  The first variable display pause flag is set to the on state when the big variable symbol is derived and displayed on the second variable display device 42 during execution of the special game by the first variable display device 41. When the variable display of the special symbol by the first variable display device 41 is temporarily stopped and the stop display of the lost symbol is started, it is cleared and turned off. The second variable display pause flag is set to an on state when a big hit symbol is derived and displayed on the first variable display device 41 during execution of the special game by the second variable display device 42. When the variable display of the special symbol by the second variable display device 42 is temporarily stopped and the stop display of the lost symbol is started, it is cleared and turned off.

  The first temporary stop display flag is set to an on state when the variable display of the special symbol by the first variable display device 41 is temporarily stopped and the stop display of the lost symbol is started. When the variable display of the special symbol by the variable display device 41 is resumed, it is cleared and turned off. The second temporary stop display flag is set to an on state when the variable display of the special symbol by the second variable display device 42 is temporarily stopped and the stop display of the lost symbol is started. When the variable display of the special symbol by the variable display device 42 is resumed, it is cleared and turned off.

  The first variable display restart flag is set to the on state when the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the second variable display device 42, and is set by the first variable display device 41. When the special symbol variable display is resumed, it is cleared and turned off. The second variable display restart flag is set to the on state when the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the first variable display device 41, and is set by the second variable display device 42. When the special symbol variable display is resumed, it is cleared and turned off.

  In addition, the flag memory 214 of the display control board 12 replaces the third and fourth variable display time timer stop flags with the third and fourth variable display pause flags, and the third and fourth pause displays. A middle flag and third and fourth variable display restart flags are provided.

  The third variable display pause flag is set to an on state when a big hit symbol is derived and displayed on the fourth variable display device 44 during execution of the special game by the third variable display device 43. When the variable display of the decorative symbol by the third variable display device 43 is temporarily stopped and the stop display of the lost symbol is started, it is cleared and turned off. The fourth variable display pause flag is set to an on state when a big hit symbol is derived and displayed on the third variable display device 43 during execution of the special game by the fourth variable display device 44. When the variable display of the decorative symbols by the fourth variable display device 44 is temporarily stopped and the stop display of the lost symbols is started, it is cleared and turned off.

  The third temporary stop display flag is set to the on state when the variable display of the decorative symbol by the third variable display device 43 is temporarily stopped and the stop display of the lost symbol is started. When the variable display of the decorative symbols by the variable display device 43 is resumed, it is cleared and turned off. The fourth temporary stop display flag is set to the on state when the variable display of the decorative symbol by the fourth variable display device 44 is temporarily stopped and the stop display of the lost symbol is started. When the variable display of the decorative design by the variable display device 44 is resumed, it is cleared and turned off.

  The third variable display restart flag is set to the on state when the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the fourth variable display device 44, and is set by the third variable display device 43. When the decorative display variable display is resumed, it is cleared and turned off. The fourth variable display restart flag is set to the on state when the big hit gaming state based on the fact that the big hit symbol is derived and displayed on the third variable display device 43, and is set by the fourth variable display device 44. When the decorative display variable display is resumed, it is cleared and turned off.

  FIG. 59 is a flowchart showing the first variable display control process in this case. In the first variable display control process, the CPU 103 first determines whether or not the first temporary stop display flag provided in the flag memory 118 is turned on (step S1291).

  When the first pause display flag is off (step S1291; No), it is subsequently determined whether or not the first variable display pause flag provided in the flag memory 118 is on. (Step S1292). When the first variable display pause flag is off (step S1292; No), the process proceeds to step S1298. On the other hand, when the first variable display pause flag is on (step S1292; Yes), the variable display of the special symbol by the first variable display device 41 is stopped and the pause symbol temporary display is started. (Step S1293). Thereafter, the CPU 103 clears the first variable display pause flag and turns it off, and sets the first pause display flag to on (step S1294).

  If the first pause display flag is turned on in step S1291 (step S1291; Yes), then the first variable display restart flag provided in the flag memory 118 is turned on. It is determined whether or not (step S1295). On the other hand, when the first variable display restart flag is on (step S1295; Yes), the variable display of the special symbol by the first variable display device 41 is restarted (step S1296), and the first variable display is performed. The restart flag and the first pause display flag are cleared and turned off (step S1297).

  Thereafter, the CPU 103 updates the timer value by subtracting 1 from the timer value of the first variable display time timer (step S1298). Then, it is determined whether or not the timer value of the updated first variable display time timer is “0” (step S1299). When the timer value of the first variable display time timer becomes “0” (step S1299; Yes), the value of the first special symbol process flag is a value corresponding to the variable display stop process “5”. (Step S1300). On the other hand, when it is determined in step S1299 that the timer value of the first variable display time timer is other than “0” (step S1299; No), the first special symbol process flag is not updated. 1 variable display control processing is terminated.

  When the first variable display restart flag is off in the process of step S1295 (step S1295; No), the processes of steps S1296 to S1300 are skipped and the first variable display control process is ended as it is. To do. Thus, the count-down of the timer value of the first variable display time timer can be stopped until the first pause display flag is turned off after being turned on, and during this time, the first variable display device is stopped. At 41, the pause symbol can be displayed.

  FIG. 60 is a flowchart showing the first variable display stop process in this case, and FIG. 61 is a flowchart showing the first jackpot end process. In the first variable display stop process, the CPU 103 sets the second variable display time timer stop flag as the second variable display time timer stop flag when the first big hit state flag is on in the process of step S303 (step S303; Yes). Instead, the second variable display pause flag is set to ON (step S1311). In the first jackpot end process, the CPU 103 sets the second variable display restart flag to on instead of clearing and turning off the second variable display time timer stop flag as shown in FIG. S1322).

  FIG. 62 is a flowchart showing the second variable display control process in this case. In the second variable display control process, the CPU 103 determines whether or not the second temporary stop display flag provided in the flag memory 118 is turned on (step S1491).

  When the second pause display flag is off (step S1491; No), it is subsequently determined whether or not the second variable display pause flag provided in the flag memory 118 is on. (Step S1492). When the second variable display pause flag is off (step S1492; No), the process proceeds to step S1498. On the other hand, when the second variable display pause flag is on (step S1492; Yes), the variable display of the special symbol by the second variable display device 42 is stopped, and the pause symbol temporary display is started. (Step S1493). Thereafter, the CPU 103 clears and turns off the second variable display pause flag, and sets the second pause display flag to ON (step S1494).

  If the second temporary stop display flag is turned on in step S1491 (step S1491; Yes), then the second variable display restart flag provided in the flag memory 118 is turned on. It is determined whether or not (step S1495). On the other hand, when the second variable display restart flag is on (step S1495; Yes), the variable display of the special symbol by the second variable display device 42 is restarted (step S1496), and the second variable display is performed. The restart flag and the second pause display flag are cleared and turned off (step S1497).

  Thereafter, the CPU 103 updates the timer value by subtracting 1 from the timer value of the second variable display time timer (step S1498). Then, it is determined whether or not the timer value of the updated second variable display time timer is “0” (step S1499). When the timer value of the second variable display time timer becomes “0” (step S1499; Yes), the value of the second special symbol process flag is a value corresponding to the variable display stop time process “5”. (Step S1500). On the other hand, when it is determined in step S1499 that the timer value of the second variable display time timer is other than “0” (step S1499; No), the second special symbol process flag is not updated. 2 variable display control processing is terminated.

  If the second variable display restart flag is off in the process of step S1495 (step S1495; No), the processes of steps S1496 to S1500 are skipped and the second variable display control process is terminated. To do. Thereby, the countdown of the timer value of the second variable display time timer can be stopped until the second pause display flag is turned off again after being turned on, and during this time, the second variable display device is stopped. At 42, it is possible to display a temporary stop of the lost symbol.

  FIG. 63 is a flowchart showing the second variable display stop process in this case, and FIG. 64 is a flowchart showing the second jackpot end process. In the second variable display stop process, the CPU 103 sets the first variable display time timer stop flag as the first variable display time timer stop flag when the second big hit state flag is on in the process of step S503 (step S503; Yes). Instead, the first variable display pause flag is set to ON (step S1511). In the second jackpot end process, the CPU 103 sets the first variable display restart flag to on instead of clearing and turning off the first variable display time timer stop flag (step S1522).

  FIG. 65 is a flowchart showing the first variable display processing in this case. In the third variable display processing, the CPU 202 first determines whether or not the third temporary stop display flag provided in the flag memory 214 is on (step S1711).

  When the third pause display flag is off (step S1711; No), it is subsequently determined whether the third variable display pause flag provided in the flag memory 214 is on. (Step S1712). When the third variable display pause flag is off (step S1712; No), the process proceeds to step S1718. On the other hand, when the third variable display pause flag is on (step S1712; Yes), the variable display of decorative symbols by the third variable display device 43 is stopped, and the pause symbol temporary display is started. (Step S1713). Also, if necessary, a composite display of a message for notifying that the count is interrupted is started.

  Thereafter, the CPU 202 clears and turns off the third variable display pause flag, and sets the third pause display flag to ON (step S1714).

  When the third temporary stop display flag is turned on in step S1711 (step S1711; Yes), the third variable display restart flag provided in the flag memory 214 is turned on. It is determined whether or not (step S1715). On the other hand, when the third variable display restart flag is on (step S1715; Yes), the variable display of decorative symbols by the third variable display device 43 is restarted (step S1716), and the third variable display is performed. The restart flag and the third pause display flag are cleared and turned off (step S1717).

  Thereafter, the CPU 202 updates the timer value by subtracting 1 from the timer value of the third variable display time timer (step S1718). Then, it is determined whether or not the timer value of the updated third variable display time timer is “0” (step S1719). When the timer value of the third variable display time timer becomes “0” (step S1719; Yes), a predetermined count initial value is set for the first monitoring timer included in the various timers 215. (Step S1720), the countdown of the first monitoring timer is started, and the value of the first display control process flag is updated to “4”, which is a value corresponding to the first decorative symbol stop waiting process ( Step S1721). On the other hand, when it is determined in step S1719 that the timer value of the third variable display time timer is other than “0” (step S1719; No), the first display control process flag is not updated. The process during variable display 1 is terminated.

  If the third variable display restart flag is off in step S1715 (step S1715; No), the processes in steps S1716 to S1721 are skipped and the first variable display in-process is terminated. To do. Thus, the countdown of the timer value of the third variable display time timer can be stopped until the third pause display flag is turned on again after being turned on, and during this time, the third variable display device is stopped. At 43, it is possible to perform a pause display of the lost symbol.

  FIG. 66 is a flowchart showing the first decorative symbol stop waiting process in this case, and FIG. 67 is a flowchart showing the first jackpot end display process. The processing steps in FIG. 66 are basically the same as the first decorative symbol stop waiting process shown in FIG. 45, and the processing steps in FIG. 67 are basically the first jackpot end display processing shown in FIG. It is the same. However, when the CPU 202 is a big hit in the process of step S725 of FIG. 66 (step S725; Yes), instead of the fourth variable display time timer stop flag, the fourth variable display pause flag is turned on. (Step S1726). In the first jackpot end display process of FIG. 67, the CPU 202 sets the fourth variable display restart flag to ON instead of clearing and turning OFF the fourth variable display time timer stop flag (step S1732). ).

FIG. 68 is a flowchart showing the second variable display processing.
First, when the fourth pause display flag is off (step S1811; No), subsequently, whether or not the fourth variable display pause flag provided in the flag memory 214 is on. Is discriminated (step S1812). When the fourth variable display pause flag is off (step S1812; No), the process proceeds to step S1818. On the other hand, when the fourth variable display pause flag is on (step S1812; Yes), the variable display of decorative symbols by the fourth variable display device 44 is stopped, and the pause symbol temporary display (and (Or display of a message indicating that the timing has been interrupted) is started (step S1813). Thereafter, the CPU 202 clears and turns off the fourth variable display pause flag, and sets the fourth pause display flag to on (step S1814).

  If it is determined in step S1811 that the fourth temporary stop display flag is on (step S1811; Yes), then the fourth variable display restart provided in the flag memory 214 is resumed. It is determined whether or not the flag is on (step S1815). When the fourth variable display restart flag is on (step S1815; Yes), the variable display of the decorative symbols by the fourth variable display device 44 is restarted (step S1816), and the fourth variable display restart flag is restarted. And the fourth pause display flag are cleared and turned off (step S1817).

  Thereafter, the CPU 202 updates the timer value by subtracting 1 from the timer value of the fourth variable display time timer (step S1818). Then, it is determined whether or not the timer value of the updated fourth variable display time timer is “0” (step S1819). When the timer value of the fourth variable display time timer becomes “0” (step S1819; Yes), a predetermined count initial value is set for the second monitoring timer included in the various timers 215. (Step S1820), the countdown of the second monitoring timer is started, and the value of the second display control process flag is updated to “5” which is a value corresponding to the second decorative symbol stop waiting process ( Step S1821). On the other hand, when it is determined in step S1819 that the timer value of the fourth variable display time timer is other than “0” (step S1819; No), the second display control process flag is not updated. 2 variable display in-process is terminated.

  If the fourth variable display restart flag is off in step S1815 (step S1815; No), the processes in steps S1816 to S1821 are skipped, and the second variable display in-process is terminated. To do. Accordingly, the countdown of the timer value of the fourth variable display time timer can be stopped until the fourth pause display flag is turned off after being turned on, and during this time, the fourth variable display device is stopped. At 44, the suspend symbol display (and / or display indicating that the timer countdown is interrupted) can be performed.

FIG. 69 is a flowchart showing the second decorative symbol stop waiting process in this case, and FIG. 70 is a flowchart showing the first jackpot end display process. The processing steps in FIG. 69 are basically the same as the second decorative symbol stop waiting process shown in FIG. 50, and the processing steps in FIG. 70 are basically the second jackpot end display processing shown in FIG. It is the same.
However, in the second decorative symbol stop waiting process of FIG. 69, when the CPU 202 is a big hit in the process of step S825 (step S825; Yes), the third variable display time timer stop flag is replaced with the third variable display time timer stop flag. The variable display pause flag is set to ON (step S1826). In the second jackpot end display process of FIG. 70, the CPU 202 sets the third variable display restart flag to on instead of clearing and turning off the third variable display time timer stop flag (step S1832). ).

  Next, a display control example for controlling the display operation in each of the variable display devices 41 to 44 in this case will be described. First, after a special figure game with a display result as a big hit is started on the first variable display device 41, a special figure game with a display result as a normal big hit is started on the second variable display device 42. An example of display control in this case will be described.

  71 is a timing chart showing an example of display operation in each of the variable display devices 41 to 44 in this case, and FIG. 72 is a diagram showing variable display modes of special symbols and decorative symbols in each of the variable display devices 41 to 44. is there. In the figure, process e is a display control process for displaying a suspended symbol temporarily.

  In this display control example, at timing t2, the CPU 103 of the main board 11 finishes the variable display of the special symbol by the second variable display device 42, derives and displays the normal jackpot symbol (FIG. 63, step S501), A second decorative design determination command D1XX (h) is sent to the display control board 12 (step S502). Further, the CPU 103 sets the first variable display pause flag to ON (FIG. 63, step S1511), stops the variable display of the special symbol by the first variable display device 41, and the first variable display device. For the special symbol displayed on the left, middle, and right variable display portion 41, the suspend symbol display by the process e is started.

  On the other hand, at the timing t2, the CPU 202 of the display control board 12 causes the fourth variable display device 44 to display and display the normal jackpot symbol, and responds to the reception of the second decorative symbol determination command D1XX from the main substrate 11. Then, it is displayed in a completely stopped state by the process c (FIG. 69, step S824). In addition, the CPU 103 stops the variable display of the decorative symbols by the third variable display device 43, and processes the decorative symbols displayed on the left, middle, and right variable display portions of the third variable display device 43. The temporary stop display of the lost symbol by e is started (FIG. 69, step S1826).

  Thereby, in the second variable display device 42 and the fourth variable display device 44, as shown in FIG. 72 (F), the normal big hit symbol is confirmed and displayed, and the pachinko gaming machine 1 is shown in FIG. 72 (G). As shown in FIG. During this time, the first variable display device 41 and the third variable display device 43 display a display indicating that the suspending display of the lost symbol by the process c and the continuation of the variable display time are suspended.

  Then, at timing T4 when the big hit gaming state ends, the CPU 103 of the main board 11 sends a big hit end command E000 (h) to the display control board 12 (FIG. 64, step S521). Further, the CPU 103 sets the first variable display restart flag to ON (FIG. 64, step S1522), and restarts the variable symbol special display by the first variable display device 41.

  On the other hand, in response to receiving the jackpot end command E000 (h) sent from the main board 11, the CPU 202 of the display control board 12 performs a jackpot end notification effect display as shown in FIG. 72 (H). (FIG. 70, step S831). Further, the CPU 103 turns on the third variable display restart flag (FIG. 70, step S1832), and restarts the variable display of the decorative symbols by the third variable display device 43.

  Next, after the first variable display device 41 starts the special figure game with the display result as a normal big hit, the second variable display device 42 starts the special figure game with the display result as the probable big hit. An example of display control in the case of failure will be described.

  FIG. 73 is a timing chart showing an example of display operation in each of the variable display devices 41 to 44 in this case, and FIG. 74 is a diagram showing a variable display mode of special symbols and decorative symbols in each of the variable display devices 41 to 44. is there.

  In this display control example, at timing t12, the CPU 103 of the main board 11 ends the variable display of the special symbol by the first variable display device 41, derives and displays the normal jackpot symbol (FIG. 60, step S301), The first decorative symbol determination command D1XX (h) is sent to the display control board 12 (step S302). Further, the CPU 103 sets the second variable display pause flag to ON (step S1311), stops the variable display of the special symbol by the first variable display device 41, and sets the left of the first variable display device 41 to the left. For the special symbol displayed in the middle, right variable display section, the display of the pause symbol of the lost symbol by the process e is started.

  On the other hand, at the timing t12, the CPU 202 of the display control board 12 causes the third variable display device 43 to derive and display the normal jackpot symbol and responds to the reception of the second decorative symbol determination command D1XX from the main substrate 11. Then, it is displayed in a completely stopped state by the process c (FIG. 66, step S724). Further, the CPU 103 stops the variable display of the decorative symbols by the fourth variable display device 44, and processes the decorative symbols displayed on the left, middle, and right variable display portions of the fourth variable display device 44. A pause display of a lost symbol by e is started (step S1726).

  As a result, in the first variable display device 41 and the third variable display device 43, as shown in FIG. 74 (F), the normal jackpot symbol is confirmed and displayed, and the pachinko gaming machine 1 is shown in FIG. 74 (G). As shown in FIG. In the meantime, the first variable display device 41 and the third variable display device 43 display a display indicating that the display time of the suspend symbol display and the variable display is stopped by the process c.

  Then, at timing t13 when the big hit gaming state ends, the CPU 103 of the main board 11 sends a big hit end command E000 (h) to the display control board 12 (FIG. 61, step S321). The second variable display restart flag is set to ON (FIG. 61, step S1322), and the variable display of the special symbol by the second variable display device 42 is restarted.

  On the other hand, in response to receiving the jackpot end command E000 (h) sent from the main board 11, the CPU 202 of the display control board 12 performs a jackpot end notification effect display as shown in FIG. 74 (H). (FIG. 67, step S731). Further, the CPU 103 turns on the fourth variable display restart flag (FIG. 67, step S1732), and restarts the variable display of the decorative symbols by the fourth variable display device 44.

  Even in this case, similarly to the above embodiment, the big hit gaming state based on the derivation display of the big hit symbol on the first variable display device 41 and the big hit symbol on the second variable display device 42 Since it is possible to prevent the big hit gaming state based on the derivation display from occurring at the same time, it is possible to prevent an adverse effect such as exerting a strong impact on the player and inciting a significant amount of happiness.

  In addition, the arrangement of the first, second, third and fourth variable display devices 41 to 44 is not limited to the arrangement of the above-described embodiment, but depends on the configuration and specifications of the pachinko gaming machine 1. It can be changed arbitrarily. Furthermore, the first, second, third, and fourth variable display devices 41 to 44 do not need to be configured as independent display devices. For example, in the four display areas of one display device, the above-described first display device is provided. Substantially the same display as that of the first, second, third, and fourth variable display devices 41 to 44 may be performed.

  Each of the two display devices may operate as one of the first and second variable display devices 41 and 42 described above so as to be interchangeable. For example, a period in which the pachinko gaming machine 1 is operating with power supply is divided into a first period and a second period, and one of the two display devices is the first variable in the first period. It operates as the display device 41 and the other operates as the second variable display device 42. On the other hand, in the second period, one of the two display devices operates as the second variable display device 42 and the other operates as the first variable display device 41. In this case, the third and fourth variable display devices 43 and 44 may be switched and operated corresponding to the first and second variable display devices 41 and 42.

  Alternatively, of the two display devices, the one in which the condition for starting the special figure game is established first and the special symbol variable display is started may operate as the first variable display device 41 described above. Then, when a condition for starting the special figure game by the other display device on which the special symbol is stopped and displayed during execution of the special figure game is established, the other display device is set to the second variable display described above. The device 42 may be operated.

  Further, the first and second variable display devices 41 and 42 have functions as the third and fourth variable display devices 43 and 44, and the first and second variable display devices 41 and 42 have the above-described third function. And the effect display similar to the 4th variable display apparatuses 43 and 44 may be performed.

  In the above embodiment, the first special symbol process in step S15 and the second special symbol process in step S16 have been described as being executed as separate processes. However, the present invention is not limited to this, and a process common to the first and second variable display devices 41 and 42 is executed as the first and second special symbol process. There may be. In addition, although it has been described that the first and second special symbol process processes are executed once each time the game control interrupt process is executed, the game control interrupt process is not limited to this. Each time the loading process is executed, only one of the first and second special symbol process processes may be alternately executed once.

  In the above-described embodiment, the first and second ordinary variable winning ball devices 61 and 62 are described as starting winning ports. That is, it has been described that two start winning openings are provided corresponding to the two variable display devices. However, the present invention is not limited to this, and for example, one start winning opening corresponding to both the first and second variable display devices 41 and 42 may be provided.

  In this case, when a game ball won in one start winning opening is detected by the start winning opening switch, for example, a random R1 value that is a big hit determination random number updated by the random counter 113 or the like is extracted, and the first and It is stored at the head of the empty entry in one of the first and second special figure reservation memories 111 and 112 provided corresponding to each of the second variable display devices 41 and 42. At this time, for example, when there is an empty entry in the first special figure reservation memory 111, the value of the extracted random R1 may be preferentially stored in the first special figure reservation memory 111. . The extracted random R1 is stored in the second special figure reservation storage unit 121B only when the number of reserved storage in the first special figure reservation memory 111 is the upper limit value and there is no empty entry. Good.

  Alternatively, each time the value of the random R1 is extracted, it may be alternately stored in one of the first and second special figure reservation memories 111 and 112. Further, when extracting the value of the random R1, a predetermined random number for sorting determination is extracted, and the extracted random R1 value is stored in the first and second special figure hold according to the value of the random number for sorting determination. You may make it memorize | store in either memory 111,112. In addition, the rate of this distribution may vary depending on the gaming state of the pachinko gaming machine 1. For example, in the normal gaming state, the first special figure holding memory 111 is preferentially allocated, and in the probability improvement state, the first and second special figure holding memory 111 and the special figure holding are reserved. You may make it distribute to the memory 112 equally.

  Further, based on the value of the random R1 extracted from the random counter 113, it may be determined which of the first and second special figure reservation memories 111 and 112 is to be stored. For example, it is assumed that the value of the random R1 takes a value in the range of “0” to “599”. In this case, when the value of the random R1 extracted in accordance with the winning of the game ball at the start winning opening is within the range of “0” to “299”, the value of the random R1 is set as the first special figure hold. Store in the memory 111. On the other hand, when the value of the extracted random R1 is within the range of “300” to “599”, the value of the random R1 is stored in the second special figure reservation memory 112. In this case, for example, when the value of the random R1 is “3”, it is determined that the display result of the variable display in the special game by the first variable display device 41 is a jackpot combination, and the random R1 When the value is “303”, it may be determined that the display result of the variable display in the special figure game by the second variable display device 42 is the jackpot combination.

  Further, when the first and second ordinary variable winning ball devices 61 and 62 are provided corresponding to the first and second variable display devices 41 and 42, respectively, the first and second ordinary variable devices are provided. When a game ball wins one of the winning ball apparatuses 61 and 62, for example, the random counter 113 or the like extracts the value of the random R1 updated as one kind of big hit determination random number, and the first and second ordinary The value of the extracted random R1 is stored in one of the first and second special figure holding memories 111 and 112 in accordance with which of the variable winning ball devices 61 and 62 has won the game ball. May be.

  As described above, when one start winning opening corresponding to both the first and second variable display devices 41 and 42 is provided, the game ball that has won a prize in the one starting winning opening is the start winning opening. When detected by the switch, an external signal may be output that makes it possible to specify which of the first and second variable display devices 41 and 42 is used to establish the start condition of the special figure game. For example, the CPU 103 mounted on the main board 11 executes a predetermined signal output processing program, and the random R1 value extracted from the random counter 113 is used as the first and second special figure reservation memories 111. , 112 may generate and output different types of external signals depending on which of them is stored.

  In the embodiment described above, the first and second special variable winning ball devices 71 and 72 are described as the big winning openings. In other words, the description has been given on the assumption that two winning prize openings are provided corresponding to the two variable display devices. However, the present invention is not limited to this, and for example, one big winning opening corresponding to both the first and second variable display devices 41 and 42 may be provided.

  In addition, the first and second special variable winning ball devices 71 and 72 as the special winning opening are provided corresponding to the first and second variable display devices 41 and 42, respectively, but the present invention is not limited thereto. Instead, the first and second special variable winning ball devices 71 and 72 may be alternately opened for each round in the big hit gaming state. For example, in the odd round, the first special variable winning ball device 71 is opened and the second special variable winning ball device 72 is closed, and in the even round, the first special variable winning ball device 71 is closed. The second special variable winning ball device 72 may be opened.

  In the above-described embodiment, it has been described that the on / off control of the first and second start winning memory indicators 45 and 46 is performed on the main board 11 side. On the other hand, the on / off control of the first and second start winning memory indicators 45 and 46 may be performed on the display control board 12 side. In this case, when the CPU 103 mounted on the main board 11 is changed by adding or subtracting 1 from the number of reserved memories in the first and second special figure reservation memories 111 and 112, A setting is made to transmit a display control command indicating the number of reserved memories corresponding to each of the second special figure reservation memories 111 and 112 to the display control board 12. Then, the CPU 202 mounted on the display control board 12 performs on / off control of the first and second start winning memory display units 45 and 46 according to the number of reserved memories indicated by the display control command from the main board 11. You may make it perform.

  In addition, the first and second start winning memory indicators 45 and 46 have been described as being provided on the upper portions of the first and second variable display devices 41 and 42, but the present invention is not limited thereto. Similar to the first and second start winning memory indicators 45 and 46, the third and third displays that make it possible to specify the start winning memory numbers for the first and second ordinary variable winning ball devices 61 and 62, respectively. The display may be performed in a predetermined display area provided in the four variable display devices 43 and 44. Furthermore, both the display of the start winning memory number on the first and second start winning memory indicators 45 and 46 and the display of the start winning memory number on the third and fourth variable display devices 43 and 44 are both performed. You may do it.

  Furthermore, in the above embodiment, the special symbol derived and displayed on each of the variable display devices 41 to 44 causes the player to shift to the probability improvement state after the big hit gaming state, or to end the probability improvement state. I was informed. However, the present invention is not limited to this, and the occurrence or end of the probability improvement state may be notified by another effect accompanying the variable symbol variable display. In addition, the effect of notifying the occurrence or termination of the probability improvement state may be performed during execution of variable symbol special display, or may be performed after derivation display of a fixed symbol. Further, the effect of notifying the occurrence of the probability improvement state may be performed in the big hit gaming state.

  In the above embodiment, various tables (for example, the symbol determination table in FIGS. 7 and 8 and the variable display pattern determination in FIGS. 9 and 10 are used for the first and second variable display devices 41 and 42, respectively. Table), but the contents of the tables for the first and second variable display devices are the same, and one table (for example, one symbol determination table, one variable display pattern determination table) is provided for each. It can also be configured to be shared.

  In the present invention, two or more N variable display devices may be arranged. In that case, a circuit that latches the count value of one counter at different timings may be provided.

  Further, the gaming machine of the present invention may be a ball and ball game machine such as a pachinko game machine, and if it has an image display device, for example, a general electric machine or a bullet with a probability setting function called a pachikon. It may be a ball game machine or the like. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. In other words, any type of gaming machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  The present invention can also be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided to a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Furthermore, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a detachable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. of the main board | substrate. It is a figure which shows an example of the content of a display control command. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure for demonstrating the random number used for game control and display control. It is a figure which shows the structural example of the table for jackpot determination. It is a figure which shows the structural example of the 1st symbol determination table. It is a figure which shows the structural example of the 2nd symbol determination table. It is a figure which shows the structural example of the 1st variable display pattern determination table. It is a figure which shows the structural example of the 2nd variable display pattern determination table. It is a circuit block diagram which shows the structural example of a random counter. It is a circuit block diagram which shows the structural example of a random value storage circuit. It is a timing chart for demonstrating operation | movement of a random counter. It is a block diagram which shows an example of the hardware constitutions for a display. It is a block diagram which shows the structural example of a display control board. It is a figure which shows the example of a random number. It is a figure which shows the structural example of a display control pattern table memory. It is a figure which shows the structural example of a symbol display control pattern table. It is a flowchart which shows a game control main process. It is a flowchart which shows a game control interruption process. It is a flowchart which shows the detail of a 1st special symbol process process. It is a flowchart which shows the detail of a 1st winning process. It is a flowchart which shows the detail of a 1st jackpot determination process. It is a flowchart which shows the detail of a 1st definite symbol determination process. It is a flowchart which shows the detail of a 1st definite symbol determination process. It is a flowchart which shows the detail of a 1st variable display pattern setting process. It is a flowchart which shows the detail of a 1st variable display control process. It is a flowchart which shows the detail of the process at the time of the 1st variable display stop. It is a flowchart which shows the detail of the 1st jackpot end process. It is a flowchart which shows the detail of a 2nd special symbol process process. It is a flowchart which shows the detail of a 2nd winning process. It is a flowchart which shows the detail of a 2nd jackpot determination process. It is a flowchart which shows the detail of a 2nd definite symbol determination process. It is a flowchart which shows the detail of a 2nd definite symbol determination process. It is a flowchart which shows the detail of a 2nd variable display pattern setting process. It is a flowchart which shows the detail of a 2nd variable display control process. It is a flowchart which shows the detail of the process at the time of the 2nd variable display stop. It is a flowchart which shows the detail of a 2nd jackpot end process. It is a flowchart which shows a display control main process. FIG. 40 is a flowchart showing details of command analysis processing shown in FIG. 39. FIG. FIG. 40 is a flowchart showing details of command analysis processing shown in FIG. 39. FIG. It is a flowchart which shows the detail of the 1st decoration symbol display control process process shown in FIG. 43 is a flowchart showing details of a first variable display start command reception wait process shown in FIG. 42. 43 is a flowchart showing details of a first variable display in-process shown in FIG. 42. It is a flowchart which shows the detail of the 1st decoration symbol stop waiting process shown in FIG. It is a flowchart which shows the detail of the 1st jackpot end display process shown in FIG. FIG. 40 is a flowchart showing details of second decorative symbol display control process processing shown in FIG. 39. FIG. It is a flowchart which shows the detail of the 2nd variable display start command reception waiting process shown in FIG. It is a flowchart which shows the detail of the 2nd variable display process shown in FIG. It is a flowchart which shows the detail of the 2nd decoration symbol stop waiting process shown in FIG. It is a flowchart which shows the detail of the 2nd big hit end display process shown in FIG. It is explanatory drawing which shows the process which comprises each display control pattern. Display control when a special figure game whose display result is a normal big hit is started on the second variable display device after a special figure game whose display result is a positive big hit is started on the first variable display device It is a figure which shows an example. It is a circuit block diagram which shows the other structural example of a random counter. FIG. 55 is a timing chart for explaining the operation of the random counter having the configuration shown in FIG. 54. FIG. It is a circuit block diagram which shows the other structural example of the random counter which can perform a winning process only when a start winning signal continues for a fixed period. It is a figure for demonstrating the example of a structure for performing a winning process, when a start winning signal continues for a fixed period. It is a flowchart for demonstrating the example of a structure for performing a winning process, when a start winning signal continues for a fixed period. It is a flowchart which shows the 1st variable display control process in the case of performing a pause display of a loss symbol on the other variable display device, after the big hit game state is started by one variable display device. It is a flowchart which shows the 1st process at the time of variable display stop in the case of performing a pause display of a loss symbol on the other variable display device, after the big hit game state is started by one variable display device. It is a flowchart which shows the modification of the 1st jackpot end process in the case of performing a pause display of a loss symbol on the other variable display device after the big hit game state is started on one variable display device. It is a flowchart of the 2nd variable display control process in the case of performing a pause display of a loss symbol on the other variable display device, after the big hit game state is started on one variable display device. It is a flowchart of the process at the time of the 2nd variable display stop in the case of performing a pause display of a lost symbol on the other variable display device, after the big hit game state is started on one variable display device. It is a flowchart of the 2nd big hit end process in the case of performing a pause display of a lost symbol on the other variable display device, after the big hit game state is started on one variable display device. It is a flowchart of the 1st variable display process in the case of performing a pause display of a lost symbol on the other variable display device after the big hit gaming state is started on one variable display device. FIG. 11 is a flowchart showing a modified example of the first decorative symbol stop waiting process when a lost symbol is displayed on the other variable display device after the big hit gaming state is started on one variable display device. It is a flowchart which shows the modification of the 1st big hit end display process in the case of performing a pause display of a loss symbol on the other variable display device after the big hit game state is started on one variable display device. It is a flowchart which shows the modification of the 2nd variable display process in the case of performing a pause display of a loss symbol on the other variable display device, after the big hit game state is started by one variable display device. It is a flowchart which shows the modification of the 2nd decoration symbol stop waiting process in the case of performing a temporary stop display of a loss symbol on the other variable display device, after the big hit game state is started by one variable display device. It is a flowchart which shows the modification of the 2nd big hit end display process in the case of performing a pause display of a loss symbol on the other variable display device after the big hit game state is started on one variable display device. FIG. 10 is a timing chart showing a modification example of display control in a case where a losing symbol is paused and displayed on the other variable display device after the big hit gaming state is started on one variable display device. FIG. 72 is a diagram illustrating a variable display example of special symbols in the display control example illustrated in FIG. 71. It is a timing chart which shows the modification of display control. It is a figure which shows the variable display example of the special symbol in the display control example shown in FIG.

Explanation of symbols

1 ... Pachinko machine
2… Game board
3 ... Frame for gaming machine 8L, 8R ... Speaker
9 ... Game effect lamp
10… Power supply board
11 ... Main board
12 ... Display control board
13 ... Voice control board
14 ... Lamp control board
15 ... Dispensing control board
16 ... Information terminal board 21-24 ... Solenoid
41. First variable display device
42 ... Second variable display device
43 ... Third variable display device
44. Fourth variable display device
45 ... 1st start winning memory indicator
46 ... Second start winning memory indicator
51 ... 1st normal symbol indicator
52 ... Second normal symbol display
61: First ordinary variable winning ball apparatus
62 ... Second ordinary variable winning ball apparatus
70… Each prize opening switch
71: First special variable winning ball apparatus
72 ... Second special variable winning ball device 100 ... Game control microcomputers 101, 203 ... ROM
102, 204 ... RAM
103, 202 ... CPU
104 ... I / O port 107 ... Switch circuit 108 ... Solenoid circuit 111 ... First special figure reservation memory 112 ... Second special figure reservation memory 113, 211 ... Random counter 114 ... Big hit determination table memory 115 ... For symbol determination Table memory 116 ... Variable display pattern determination table memory 117 ... Probability change counter 118, 214 ... Flag memory 119 ... Variable display time timer 120 ... Normal-time big hit judgment table 121 ... Probability change big hit judgment table 130 ... First normal big hit Symbol determining table 131... First probability variation big hit symbol determining table 132... First left symbol determining table 133... First middle symbol determining table 134... First right symbol determining table 140. Standard jackpot design table 141 ... second probability variation big hit symbol determination table 142 ... second left symbol determination table 143 ... second middle symbol determination table 144 ... second right symbol determination table 150 ... variable at the time of the first normal loss Display pattern determination table 151... First reach loss variable display pattern determination table 152... First big hit variable display pattern determination table 160... Second normal loss variable display pattern determination table 161. Reach-losing variable display pattern determination table 162 ... Second big hit variable display pattern determination table 200 ... Oscillator circuit 201 ... Reset circuit 205 ... GCL
206 ... CGROM
207 ... VRAM
212 ... Display control pattern table memory 215 ... Various timers 220 ... Symbol display control pattern table 1201 ... Reference clock signal generation circuit 1202 ... Count clock signal generation circuit 1203 ... Counter 1204A ... First latch signal output circuit 1204B ... Second latch Signal output circuit 1205A ... first random value storage circuit 1205B ... second random value storage circuit

Claims (8)

First variable display means for variably displaying a plurality of types of identification information that can be identified based on the fact that the first start condition is satisfied after the first start condition is satisfied, and the first start condition A second variable display means for variably displaying a plurality of types of identification information that can each be identified based on the second start condition being satisfied after the second start condition different from the second start condition is satisfied, When the display result of variable display of identification information by the first variable display means is a combination of specific identification information determined in advance, or the display result of variable display of identification information by the second variable display means A gaming machine that controls a specific gaming state advantageous to the player when the combination of the specific identification information is provided,
Random number generating means for generating random numbers based on the establishment of the first start condition and the second start condition,
Game control means for controlling the progress of the game using the variable display of the first and second variable display means based on the random number value generated by the random number generation means;
With
The random number generation means includes a reference clock signal generation means for generating a reference clock signal, a frequency division of the reference clock signal, a first count clock signal, and a second phase having a phase opposite to that of the first count clock signal. A count clock signal generating means for generating a count clock signal; a numerical data updating means for updating and outputting numerical data in a predetermined cycle in response to the first count clock signal; and responding to the first latch signal The first random number value storage means for storing the numerical data output from the numerical data update means as a random value, and the numerical data output from the numerical data update means in response to the second latch signal a second random number storage means for storing a random number, the second count clock signal by dividing, shows the output timing of the first latch signal A first latch timing signal, in the first latch timing signal and antiphase, and latch timing signal generating means for generating a second latch timing signal indicating the output timing of the second latch signal, the The first start signal input based on the establishment of the first start condition is synchronized with the first latch timing signal generated by the latch timing signal generating means, and is used as the first latch signal. The latch timing signal generating means generates a first latch signal output means for outputting to the first random value storage means and a second start signal inputted based on the fact that the second start condition is satisfied. Second latch signal output means for outputting to the second random number storage means as a second latch signal in synchronization with the second latch timing signal It includes,
The latch timing signal generation means is configured to update the first latch timing signal and the second latch timing signal during each period from the time when the numerical data update means updates the numerical data until the next update. Each one is output periodically so that only one of the latch timing signals is output,
The game control means uses the random number value stored in the first random number value storage means and the random number value stored in the second random number value storage means, respectively, for the first random value storage means and the random number value storage means. Storage means for reading and storing from the second random value storage means;
Based on the establishment of the first start condition, the random value generated by the establishment of the first start condition that triggers the establishment of the first start condition and stored in the storage means is a predetermined determination. By determining whether or not it matches the value data, it is determined whether or not the display result in the variable display by the first variable display means is the specific display result, and the second start condition is satisfied Based on this, it is determined whether or not the random value generated by the establishment of the second start condition that triggered the second start condition and stored in the storage means matches the predetermined determination value data. Display result determining means for determining whether or not the display result in the variable display by the second variable display means is the specific display result;
Based on the determination result of the display result determining means, the variable from the start of variable display of the identification information to the first variable display means and the second variable display means until the display result is derived and displayed. Variable display data selecting means for selecting variable display data indicating the display time from a plurality of predetermined variable display data;
Variable display time measuring means for measuring a variable display time from the start of variable display of the identification information in each of the first variable display means and the second variable display means until the display result is derived and displayed; ,
Measurement determination means for determining whether or not the variable display time indicated by the variable display data selected by the variable display data selection means by the measurement by the variable display time measurement means has passed;
When the first start condition is satisfied, variable display by the first variable display means is started, and when the measurement determination means determines that the variable display time has elapsed, the display result determination means When the determined display result is derived, variable display by the second variable display means is started by the establishment of the second start condition, and it is determined that the variable display time has elapsed by the measurement determination means Derivation display control means for deriving the display result determined by the display result determination means,
The variable display time measuring means is configured to display the identification display result on the first variable display means and when the variable information is displayed on the second variable display means. The measurement of the variable display time in the second variable display unit is interrupted at the first time when the specific gaming state based on the specific display result derived and displayed by the one variable display means, and the first variable display means A game machine comprising: a measurement interruption resuming means for resuming the measurement of the variable display time at a second time point when the specific gaming state is completed based on the specific display result being derived and displayed by the variable display means. First start detection means for establishing the first start condition by detecting a game medium in the game area where the game medium falls and outputting the first start signal to the first latch signal output means When,
Second start detection means for establishing the second start condition by detecting the game medium in the game area where the game medium falls and outputting the second start signal to the second latch signal output means When,
The gaming machine according to claim 1, further comprising:   The random number generation means measures the duration of the first start signal, and supplies the first start signal to the first latch signal output circuit when it continues for a certain period of time. Measuring a duration of the second start signal, and supplying a second start signal to the second latch signal output circuit when the duration is continued for a certain period of time. The gaming machine according to claim 1 or 2, characterized in that The game control means includes a timer interrupt process execution means for executing a timer interrupt process in response to an interrupt request signal input periodically.
The storage means that the first start signal is continuously input from the first start signal output means while the timer interrupt process execution means is executing a predetermined number of timer interrupt processes. Based on the fact that the first random number value is read from the first random number value storage means and the second start signal is continuously input from the second start signal output means, the second random number value storage means from the random number value storing means to read out the second random value,
The gaming machine according to claim 1, 2, or 3. The game control means includes
Before the display result determining means reads the random number value from the first random value storage means, the first random number value storage means outputs a first output control signal to the first random value storage means. Is controlled to be readable, and after the display result determination means reads the random number value from the first random number value storage means, the output of the first output control signal to the first random number value storage means is stopped. Then, the first random number storage means is controlled to be unreadable, and before the display result determination means reads the random number value from the second random value storage means, the second random number value storage means A second output control signal is output to control the second random number value storage means to a readable state, and the display result determining means reads the random number value from the second random number value storage means. 2 stops the output of the second output control signal to the random number value storage means 2 and stores the second random number value Including a read control means for controlling the means to the read disabled state,
The gaming machine according to any one of claims 1 to 4, characterized in that: The first random value storage means controls the first output control signal output from the read control means to be in an unreceivable state when a latch signal is input from the first latch signal output means. The second random number value storage means includes a first output control signal reception control means that outputs a first output control signal output from the read control means when a latch signal is input from the second latch signal output means. Including a second output control signal reception control means for controlling the output control signal of 2 to an unreceivable state,
The gaming machine according to claim 5 , wherein: The first random value storage means controls the latch signal output from the first latch signal output means to be in an unreceivable state when the first output control signal is input from the read control means. First latch signal reception control means
The second random number storage means controls the latch signal output from the second latch signal output means to be in an unreceivable state when the second output control signal is input from the read control means. Second latch signal reception control means
The gaming machine according to claim 5 or 6 , characterized in that. The derivation display control means comprises means for notifying that when the time measurement by the variable display time measurement means is interrupted,
The gaming machine according to any one of claims 1 to 7, wherein the gaming machine is characterized in that:

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