JP4706387B2 - Electronic component and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic component having a through electrode and a method for manufacturing the same, and more particularly to a ceramic multilayer electronic component such as a multilayer ceramic wiring board, a multilayer ceramic package, a multilayer ceramic capacitor, and a multilayer piezoelectric element, and a method for manufacturing the same.

  As an electronic component in this technical field, for example, a multilayer ceramic capacitor can be cited. In this multilayer ceramic capacitor, in order to reduce the equivalent series resistance and the equivalent series inductance, a structure in which internal electrodes are connected by via electrodes (through electrodes) is increasing. For manufacturing such a capacitor, the following manufacturing method has been used.

  First, a through hole having a diameter of, for example, about 100 μm is formed in a ceramic green sheet using a laser, a micro drill, punching, or the like. Next, a conductive paste is printed on the ceramic green sheet by a screen printing method to form internal electrodes on the ceramic green sheet, and at the same time, the conductive paste is filled into the through holes. Alternatively, the internal electrodes are formed on the ceramic green sheet and the conductive paste is filled in the through holes by separate processes by screen printing. Thereafter, a plurality of ceramic green sheets are laminated so that the positions of the through holes of the ceramic green sheets that overlap each other coincide with each other to form a laminate, and the obtained laminate is subjected to cutting treatment and firing treatment. By rubbing, a multilayer ceramic capacitor is completed.

In recent years, electronic components typified by the multilayer ceramic capacitor have been increasingly demanded for miniaturization, and for that reason, further multilayering has become necessary. That is, for the purpose of thinning and multilayering, it has become necessary to print the internal electrode thinly on the ceramic green sheet. As a result, in order to sufficiently fill the through holes with the conductive paste, screen printing for filling the through holes is performed in a separate process from the screen printing of the internal electrodes.
Japanese Patent Laid-Open No. 10-270282

  At this time, due to the problem of printing accuracy of the screen printing method, it was necessary to perform printing for filling the through holes with a screen pattern provided with paste transmission holes having a diameter larger than the diameter of the through holes. Therefore, the conductive paste protrudes on the sheet at the periphery of the through-hole, and the conductive paste rises from the sheet surface, so that the stacking shift in which the sheets that overlap vertically shift in the surface direction is large.

  Therefore, the present invention has been made to solve the above-described problems, and an object thereof is to provide an electronic component in which stacking misalignment is suppressed and a method for manufacturing the same.

In the method for manufacturing an electronic component according to the present invention, the through hole of the plurality of ceramic green sheets in which the through hole is formed is positioned above the upper surface of the ceramic green sheet, and a main body portion filling the inside of the through hole, and A step of forming a via electrode having a connection pad portion formed integrally with the main body portion, and a step of laminating a plurality of ceramic green sheets so that the through-holes in which the via electrode is formed overlap. The area S ₁ (mm ² ) of the connection pad portion on the surface of the green sheet and the thickness t ₁ (mm) of the connection pad portion are expressed by the following formulas (1) and (2).
t ₁ / S ₁ ≦ 1.35 (1)
S ₁ ≦ 1.3 × 10 ⁻² (2)
It is characterized by satisfying.

  As a result of intensive research, the inventors have formed via electrodes having connection pad portions that satisfy the above formulas (1) and (2) to obtain an electronic component in which stacking misalignment is suppressed. Newly found.

  The thickness of the ceramic green sheet is preferably 20 μm or less. In this case, an electronic component with a reduced height can be obtained. When the electronic component is a multilayer ceramic capacitor, the capacitance can be further increased.

  Moreover, when laminating ceramic green sheets, it is preferable to laminate at least 50 ceramic green sheets. In this case, for example, when a multilayer ceramic capacitor is produced as an electronic component, an increase in capacitance is realized.

The electronic component according to the present invention includes a main body portion that fills the through holes of the plurality of ceramic green sheets in which the through holes are formed, an upper side of the upper surface of the ceramic green sheet, and is integrated with the main body portion. An electronic component formed by firing after laminating a plurality of ceramic green sheets so as to form a via electrode having a connection pad portion that is formed and overlapping a through hole in which the via electrode is formed. ceramic green area of the connection pad portion after firing on the surface of the sheet S _{2 (mm} ²⁾ and thickness t _{2 (mm)} of the connection pad portion after firing, the following formula after (3) and (4)
t ₂ / S ₂ ≦ 1.59 (3)
S ₂ ≦ 9.7 × 10 ⁻³ (4)
It is characterized by satisfying.

  As a result of diligent research, the inventors have newly realized that suppression of stacking deviation can be achieved with an electronic component having a connection pad portion after firing that satisfies the above formulas (3) and (4). I found it.

  Moreover, it is preferable that the thickness after baking of a ceramic green sheet is 17 micrometers or less. In this case, an electronic component with a reduced height can be obtained. When the electronic component is a multilayer ceramic capacitor, the capacitance can be further increased.

  Further, it may be an electronic component fired after at least 50 ceramic green sheets are laminated. In this case, when the electronic component is, for example, a multilayer ceramic capacitor, an increase in capacitance is realized.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic component by which lamination | stacking deviation was suppressed and its manufacturing method are provided.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment that is considered to be the best in carrying out an electronic component and a manufacturing method thereof according to the invention will be described in detail with reference to the accompanying drawings. In addition, the same code | symbol is attached | subjected about the same or equivalent element, and the description is abbreviate | omitted when description overlaps. In this embodiment, a multilayer ceramic capacitor will be described as an example of the electronic component according to the present invention.

  First, the procedure for producing the multilayer ceramic capacitor according to this embodiment will be described.

  In producing the multilayer ceramic capacitor according to the present embodiment, as shown in FIG. 1, a ceramic green sheet (hereinafter simply referred to as a green sheet) 12 having a thickness of 20 μm or less (for example, 10 μm) is formed on the surface 10a. A plurality of carrier films 10 thus prepared are prepared. 1A is a cross-sectional view in a direction orthogonal to the thickness direction of the carrier film 10, and FIG. 1B is a plan view.

  Then, on the surface 12a of the green sheet 12 of each carrier film 10, as shown in FIGS. 2 and 3, a wiring pattern is formed by screen printing or the like, which is a known technique, using a conductive paste containing silver or nickel. The electrode 14 is formed. As shown in FIG. 2A and FIG. 2B, two types of patterns are prepared as the wiring pattern electrode 14. For convenience of explanation, one of the wiring pattern electrodes 14 is connected to the wiring pattern electrode 14A, as necessary. The other is referred to as a wiring pattern electrode 14B.

A plurality of circular holes 16 are formed in the wiring pattern electrode 14A shown in FIG. The diameter D ₁ of the respective circular holes 16 has become the same, are regularly arranged. Specifically, the circular holes 16 that are closest to each other are periodically arranged in an oblique lattice shape so that the distance between the centers of the circular holes 16 is a constant distance L.

  Further, the wiring pattern electrode 14B shown in FIG. 2B also has a square shape having the same size as the wiring pattern electrode 14A, and a plurality of circular holes 16 are located between the centers of the adjacent circular holes 16. The distances are regularly arranged in an oblique lattice pattern so that the distances are constant. However, the position of the circular hole 16 of the wiring pattern electrode 14B is shifted by a half cycle (length L / 2) relative to the position of the circular hole 16 of the wiring pattern electrode 14A. Therefore, the position of the circular hole 16 in the wiring pattern electrode 14A corresponds to the position without the circular hole 16 in the wiring pattern electrode 14B, and conversely, the position of the circular hole 16 in the wiring pattern electrode 14B is circular in the wiring pattern electrode 14A. It corresponds to a position where there is no hole 16.

  Of the plurality of carrier films 10, wiring pattern electrodes 14 </ b> A are formed on half of the carrier films 10, and wiring pattern electrodes 14 </ b> B are formed on the remaining half of the carrier films 10. Hereinafter, for convenience of explanation, of the carrier film 10 and the green sheet 12, the one on which the wiring pattern electrode 14A is formed is referred to as the carrier film 10A and the green sheet 12A, and the one on which the wiring pattern electrode 14B is formed. Are referred to as carrier film 10B and green sheet 12B. Similarly, a circular hole formed in the wiring pattern electrode 14A is referred to as a circular hole 16A, and a circular hole formed in the wiring pattern electrode 14B is referred to as a circular hole 16B as appropriate.

Next, as shown in FIGS. 4 and 5, the green sheet 12 on which the wiring pattern electrode 14 is formed is irradiated with a laser beam through a circular cross-sectional via hole (through hole) 18 that penetrates the wiring pattern electrode 14 and the green sheet 12. Formed by. The diameter of the via hole 18 is D ₂ (for example, 50 μm), and this D ₂ is smaller than the diameter D ₁ of the circular hole 16 of the wiring pattern electrode 14.

  In the carrier film 10A, as shown in FIG. 4A, the position of the via hole 18 is a half cycle (L / 2) from the center position of the circular hole 16A of the wiring pattern electrode 14A and the center position of the circular hole 16A. They are formed at positions shifted by a certain distance (that is, the center position of the circular hole 16B of the wiring pattern electrode 14B). In the carrier film 10B, as shown in FIG. 4B, the position of the via hole 18 is a half cycle (L / 2) from the center position of the circular hole 16B of the wiring pattern electrode 14B and the center position of the circular hole 16B. ), Respectively (ie, the center position of the circular hole 16A of the wiring pattern electrode 14A).

  That is, the via hole 18 is formed at the same position on both the wiring pattern electrodes 14A and 14B, and corresponds to either the position of the circular hole 16A of the wiring pattern electrode 14A or the position of the circular hole 16B of the wiring pattern electrode 14B. The number of the wiring pattern electrodes 14A and 14B is the same.

Then, each of the via holes 18 is filled with the conductive paste 20 using a known screen printing technique. The screen pattern 22 used for this screen printing has a paste having a circular cross section with a diameter D ₃ smaller than the diameter D _{1 of the} circular hole 16 and larger than the diameter D _{2 of the} via hole 18 at a position corresponding to the via hole 18. A transmission hole 24 is provided (see FIG. 7). Therefore, in order to reliably fill the via hole 18 with the conductive paste 20, if the via hole 18 is filled with more conductive paste 20 than the volume of the via hole 18, the via electrode 26 as shown in FIGS. Is formed.

The via electrode 26 includes a main body portion 26 a that fills the via hole 18 and a connection pad portion 26 b that is located above the surface 12 a of the green sheet 12 or the surface 14 a of the wiring pattern electrode 14. The body portion 26a and the connection pad portion 26b of the via electrode 26 are integrally formed. The connection pad portion 26 ^b has an area S ₁ (mm ² ) on the surface 12 a of the green sheet 12, and its projection shape is substantially the same as the cross-sectional shape of the paste transmission hole 24 (that is, a circle having a diameter D ₃ ). It has the same shape. The thickness of the connection pad portion 26b is t ₁ (mm). Incidentally, the via electrodes 26 of the via hole 18 formed at the center of the circular hole 16 of the wiring pattern electrode 14, the wiring pattern electrodes 14 to less than the diameter D ₁ of the diameter of the connection pad portions 26b are circular hole 16 The via electrode 26 and the wiring pattern electrode 14 are electrically insulated from each other. On the other hand, the via electrode 26 formed outside the circular hole 16 is electrically connected to the wiring pattern electrode 14.

  After forming the via electrode 26 as described above in each via hole 18, the green sheet 12 is peeled off from the carrier film 10. Then, as shown in FIG. 8, the plurality of green sheets 12 are stacked with the side of the via electrode 26 where the connection pad portion 26b is formed facing upward. At this time, the green sheets 12A and the green sheets 12B are alternately stacked so that the via holes 18 of the green sheet 12A and the via holes 18 of the green sheet 12B overlap each other. As a result, the via electrodes 26 of the green sheet 12 that are vertically overlapped are electrically connected.

  Then, the stacked body 32 is sandwiched between the upper cover layer 30A in which the via electrode 28 is formed at the position corresponding to the via electrode 26 and the flat lower cover layer 30B without the via electrode between the upper and lower sides of the stacked green sheets 12. Then, the laminate 32 is pressed from above and below as shown in FIG. And after cutting this laminated body 32 into chip size as needed, as shown in FIG. 10, the degreasing | defatting process and baking process are carried out by the degreasing / baking apparatus 34. FIG. Finally, the terminal electrode 35 is formed at a position corresponding to the via electrode 28 of the upper cover layer 30A of the obtained sintered body, and further baked to complete the production of the multilayer ceramic capacitor 36 (see FIG. 11). .

In the multilayer ceramic capacitor 36, the terminal electrode 35 is formed on the main surface 38 a of the mounting substrate 38 with the surface 36 a on the via electrode 28 side of the upper cover layer 30 A facing the main surface 38 a of the mounting substrate 38. Connect to the bump electrode 40. However, the terminal electrode 35 connected to the wiring pattern electrode 14A is connected to the anode bump electrode 40, and the terminal electrode 35 connected to the wiring pattern electrode 14B is connected to the cathode bump electrode 40. In the multilayer ceramic capacitor 36, the area of the connection pad portion 42 corresponding to the connection pad portion 26b of the via electrode 26 described above is S ₂ (mm), and the thickness of the connection pad portion 42 is t ₂ ( mm).

  Next, the connection pad portion 26b of the via electrode 26 formed on the green sheet 12 will be described in more detail.

The connection pad portion 26b of the via electrode 26 has an area of S ₁ (mm ² ) and a thickness of t ₁ (mm). These S ₁ and t ₁ satisfy the following two formulas (formula (1) and formula (2)).
t ₁ / S ₁ ≦ 1.35 (1)
S ₁ ≦ 1.3 × 10 ⁻² (2)

The inventors have made efforts to study a suitable range of S ₁ and t ₁ of the connection pad portion 26b in order to suppress the stacking deviation of electronic components such as a multilayer ceramic capacitor. As a result, S ₁ and t ₁ are It has been newly found that the formation of the connection pad portion 26b so as to satisfy the expressions (1) and (2) can suppress the stacking deviation of the multilayer ceramic capacitor.

Then, by firing the laminated body 32 via electrodes 26 that S ₁ and t ₁ satisfies the above two equations is formed, the following two equations (equations (3) and (4)) the connection pad portions satisfying 42 is formed.
t ₂ / S ₂ ≦ 1.59 (3)
S ₂ ≦ 9.7 × 10 ⁻³ (4)

Here, S ₂ is the area of the connection pad portion 42 in a plane orthogonal to the thickness direction of the multilayer ceramic capacitor 36, and t ₂ is the thickness of the connection pad portion 42.

  In other words, when the connection pad portion 42 included in the multilayer ceramic capacitor 36 satisfies the above expressions (3) and (4), suppression of the stacking deviation in the multilayer ceramic capacitor 36 is realized.

  In addition, the thickness of the green sheet 12 used for the production of the multilayer ceramic capacitor 36 is 20 μm or less, and the thickness of the green sheet 12 after firing is 17 μm or less when the shrinkage rate is converted to about 0.85. Therefore, the capacitance of the multilayer ceramic capacitor 36 is increased. In addition, when the green sheet 12 is thinned in this way, a reduction in height (that is, downsizing) is realized in all electronic components. Furthermore, by forming the multilayer ceramic capacitor 36 with at least 50 green sheets 12, a multilayer ceramic capacitor having a large capacitance can be obtained.

Hereinafter, in order to further clarify the effects of the present invention, description will be made using examples and comparative examples.
Example 1

It is substantially similar to the laminate 32 described above, by preparing a plurality of laminates 32 samples with the via electrodes 26 having different connection pad portion 26b of the area S ₁ and the thickness t ₁ (# 1~ # 15) The stacking deviation in the stack sample (number of stacking 140 sheets) was measured.

  As shown in FIG. 12, a specific method for measuring the stacking deviation uses the central axis X of the via electrode 26 of the lowermost green sheet 12 as a reference axis for measuring the stacking deviation. Of the via electrodes 26 of the green sheet 12 that overlap with the center axes x1, x2,... Were measured, and the average value was calculated as the stacking deviation (μm). The measurement results are as shown in the table of FIG. 13 and the graph of FIG.

As is apparent from the measurement results, the stacking deviation of the samples # 1, # 4 to # 8, # 10, # 11, and # 13 to # 15 satisfying the above formulas (1) and (2) is 40 μm. It is kept small. On the other hand, for samples # 2, # 3, # 9, and # 12 that do not satisfy the above formulas (1) and (2), the stacking deviation greatly exceeds 40 μm and is 50 μm or more. From the above, it was confirmed that the stacking deviation was significantly suppressed in the laminate sample satisfying the expressions (1) and (2).
(Example 2)

Moreover, are substantially similar to those of the laminated ceramic capacitor 36 as described above, by preparing a plurality of capacitors 36 samples with different connecting pad portion 42 in area S ₂ and the thickness _{t 2 (# 21~ # 35)} , the capacitor The stacking deviation in the sample was measured. In addition, the measuring method of lamination | stacking deviation is the same as the measuring method in the laminated body sample (140 number of lamination | stacking) mentioned above.

  The measurement results are as shown in the table of FIG. 15 and the graph of FIG. As is apparent from the measurement results, the stacking misalignment of samples # 21, # 24 to # 28, # 30, # 31, and # 33 to # 35 satisfying the above formulas (3) and (4) is less than 30 μm. It is kept small. On the other hand, for samples # 2, # 3, # 9, and # 12 that do not satisfy the above expressions (3) and (4), the stacking deviation exceeds 40 μm. From the above, it was confirmed that the stacking deviation was significantly suppressed in the capacitor samples satisfying the expressions (3) and (4).

  The present invention is not limited to the above embodiment, and various modifications are possible. For example, examples of the electronic component to which the present invention is applied include ceramic multilayer electronic components such as a multilayer ceramic substrate, a multilayer ceramic package, and a multilayer piezoelectric element in addition to the multilayer ceramic capacitor. Further, the number of stacked layers is not limited to 50 or more, and can be appropriately changed to a desired number of stacked layers.

It is the figure which showed the carrier film and green sheet which are used when producing the electronic component which concerns on embodiment of this invention. It is the top view which showed the wiring pattern electrode formed on the green sheet of FIG. It is the III-III sectional view taken on the line of FIG. FIG. 3 is a plan view showing via holes formed in the green sheet of FIG. 2. It is the VV sectional view taken on the line of FIG. FIG. 5 is a plan view showing via electrodes formed on the green sheet of FIG. 4. It is the VII-VII sectional view taken on the line of FIG. It is the figure which showed the lamination | stacking state of the wiring pattern electrode. It is the schematic sectional drawing which showed the laminated body which concerns on embodiment of this invention. It is the figure which showed the degreasing / baking apparatus applied to the laminated body of FIG. It is the schematic sectional drawing which showed the electronic component which concerns on embodiment of this invention. It is the figure which showed the measuring method of the lamination | stacking deviation which concerns on the Example of this invention. It is the table | surface which showed the measurement result of the lamination | stacking deviation which concerns on Example 1 of this invention. It is the graph which showed the measurement result of lamination gap concerning Example 1 of the present invention. It is the table | surface which showed the measurement result of the lamination | stacking deviation which concerns on Example 2 of this invention. It is the graph which showed the measurement result of lamination gap concerning Example 2 of the present invention.

Explanation of symbols

  12, 12A, 12B ... ceramic green sheet, 18 ... via hole, 26 ... via electrode, 26a ... main body, 26b ... connection pad, 36 ... multilayer ceramic capacitor.

Claims (6)

The through hole of the plurality of ceramic green sheets in which the through holes are formed is formed integrally with the main body part, which is located above the upper surface of the ceramic green sheet, and a main body part filling the through hole. Forming a via electrode having a connection pad portion;
Laminating the plurality of ceramic green sheets so that the through-holes in which the via electrodes are formed overlap,
The area S ₁ (mm ² ) of the connection pad portion on the surface of the ceramic green sheet and the thickness t ₁ (mm) of the connection pad portion are represented by the following formulas (1) and (2).
t ₁ / S ₁ ≦ 1.35 (1)
S ₁ ≦ 1.3 × 10 ⁻² (2)
An electronic component manufacturing method that satisfies the above requirements.   The method for manufacturing an electronic component according to claim 1, wherein the thickness of the ceramic green sheet is 20 μm or less.   The method for manufacturing an electronic component according to claim 1, wherein at least 50 ceramic green sheets are stacked when the ceramic green sheets are stacked. The through hole of the plurality of ceramic green sheets in which the through holes are formed is formed integrally with the main body part, which is located above the upper surface of the ceramic green sheet, and a main body part filling the through hole. An electronic component that is fired after laminating the plurality of ceramic green sheets so that the through holes in which the via electrodes are formed overlap with each other.
The area S ₂ (mm ² ) of the connection pad portion after firing on the surface of the ceramic green sheet after firing and the thickness t ₂ (mm) of the connection pad portion after firing are represented by the following formulas (3) and (3): (4)
t ₂ / S ₂ ≦ 1.59 (3)
S ₂ ≦ 9.7 × 10 ⁻³ (4)
Meet the electronic parts.   The electronic component according to claim 4, wherein a thickness of the ceramic green sheet after firing is 17 μm or less. The electronic component according to claim 4, wherein the electronic component is fired after the at least 50 ceramic green sheets are laminated.

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