JP2008205135A - Multilayer ceramic capacitor and capacitor mounting circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor capable of suppressing the propagation of the mechanical vibration because of an electrostriction phenomenon. <P>SOLUTION: The ceramic capacitor 10 includes an internal electrodes opposed region OP wherein counterpart internal electrodes 12a and 12b connected to mutually different external electrodes 16a and 16b are opposed in a chip body 15 formed by laminating alternately a plurality of dielectric layers and a plurality of nearly rectangular internal electrodes, and an internal electrode led out region LE wherein each of the internal electrodes in the internal electrodes opposed region OP is led out to the external electrode. Notches 14a and 14b are formed in the internal electrode led out region LE, respectively. Accordingly, when an AC voltage is applied between the external electrodes, even if the dielectric layer between the opposed internal electrodes in the internal electrodes opposed region repeats alternately expansion and contraction, the displacement in the surface direction caused by the expansion and the contraction is buffered by the notches, so that the displacements of the external electrodes in the surface direction are suppressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a multilayer ceramic capacitor and a capacitor-mounted circuit board on which the multilayer ceramic capacitor is mounted. More specifically, the present invention relates to a multilayer ceramic capacitor and a capacitor-mounted circuit board that suppresses propagation of vibration caused by electrostriction and reduces noise. About.

Ferroelectric materials such as barium titanate are generally used as dielectric materials for multilayer ceramic capacitors capable of obtaining a large capacitance. When an AC voltage is applied to a monolithic ceramic capacitor using a ferroelectric material, the dielectric layer sandwiched between the opposing electrodes expands and contracts alternately in the thickness and plane directions due to electrostriction. This causes vibration in the multilayer ceramic capacitor alone and the capacitor-mounted circuit board on which the multilayer ceramic capacitor is mounted, which tends to cause noise.

As a countermeasure against mechanical vibration due to the electrostriction phenomenon of the multilayer ceramic capacitor, as shown in FIG. 14 of this specification, in Patent Document 1, a hole is formed in the ceramic multilayer body, and this hole is used as a vibration node. It has been proposed to shift the resonance frequency to the high frequency side. Further, Patent Document 2 proposes an electronic component that suppresses propagation of vibrations by contacting a pair of metal terminals formed of a metal material with terminal electrodes of a capacitor element.
JP-A-11-26288 Japanese Patent Laid-Open No. 2004-288847

In recent years, the need for thin electronic devices has increased, and circuit boards mounted on these electronic devices have been increasingly thinned. For this reason, even a slight mechanical vibration of the multilayer ceramic capacitor tends to cause flexural vibration on the circuit board on which it is mounted. However, the multilayer ceramic capacitor described in the former of the background art did not have a function of suppressing propagation of the generated vibration. In addition, in the electronic component described in the latter of the background art, there is a problem that the component height is increased by the amount of contact with the metal terminal, and it is difficult to mount the electronic component on a thin electronic device.

An object of the present invention is to provide a multilayer ceramic capacitor that can be mounted on a circuit board mounted on a thin electronic device while suppressing the propagation of mechanical vibration due to an electrostrictive phenomenon by solving the above-described problems. There is to do. Another object of the present invention is to provide a capacitor-mounted circuit board capable of solving the above-described problems and suppressing the generation of noise by suppressing the propagation of mechanical vibration due to electrostriction.

In order to achieve the above object, a multilayer ceramic capacitor according to the present invention includes (1) a chip body in which a plurality of dielectric layers and a plurality of substantially rectangular internal electrodes are alternately stacked, and a surface of the chip body. In the multilayer ceramic capacitor formed and formed of a pair of external electrodes connected to land electrodes of an external circuit board, wherein the plurality of internal electrodes are alternately electrically connected to the pair of external electrodes, the chip body In which the internal electrodes connected to different external electrodes of the pair of external electrodes are opposed to each other across the dielectric layer, and the internal electrodes in the internal electrode facing region are external to each other. Of the internal electrode extraction regions that are alternately extracted to the electrodes, notches are formed in the internal electrode extraction regions, respectively. (... hereinafter referred to as first problem solving means)

One of the main forms of the multilayer ceramic capacitor is that (2) a margin region in which no internal electrode exists is provided around the notch in the internal electrode lead-out region. (... hereinafter referred to as second problem solving means)

One of the other main forms of the multilayer ceramic capacitor is (3) an insulating resin filled in the notch in the internal electrode lead-out region. (... hereinafter referred to as third problem solving means)

The capacitor-mounted circuit board of the present invention is (4) in which the external electrode of the multilayer ceramic capacitor according to any one of (1) to (3) is conductively fixed to the land electrode of the circuit board. is there. (... hereinafter referred to as fourth problem solving means)

The operation of the first problem solving means is as follows. That is, in the chip body, the internal electrodes connected to different external electrodes of the pair of external electrodes are opposed to each other across the dielectric layer, and each of the internal electrode facing regions Of the internal electrode extraction regions where the internal electrodes are alternately extracted to the external electrodes, notches are formed in the internal electrode extraction regions. For this reason, when an AC voltage is applied between the external electrodes of the multilayer ceramic capacitor, the dielectric layer between the opposing internal electrodes in the internal electrode facing region repeatedly expands and contracts alternately in the plane direction of the dielectric layer. However, the displacement in the surface direction due to the expansion / contraction is buffered by the notch, and the displacement of the external electrode in the surface direction is suppressed. Further, in the capacitor-mounted circuit board on which the multilayer ceramic capacitor is mounted, a change in the distance between the pair of land electrodes conductively fixed to the external electrodes by solder or the like is suppressed. For this reason, generation | occurrence | production of the bending vibration of the thickness direction of the said capacitor | condenser mounting circuit board is suppressed, and generation | occurrence | production of the noise accompanying the bending vibration of this circuit board is suppressed.

The operation of the second problem solving means is as follows. That is, since a margin region where no internal electrode exists is provided around the notch in the internal electrode lead-out region, it is possible to prevent a short circuit between the internal electrodes.

The operation of the third problem solving means is as follows. That is, since the inside of the notch in the internal electrode lead-out region is filled with an insulating resin, the strength of the chip body of the multilayer ceramic capacitor is prevented from being lowered, and the occurrence of a suction error by the nozzle during mounting is prevented. , Handling becomes easy.

The operation of the fourth problem solving means is as follows. That is, since the external electrode of the multilayer ceramic capacitor according to any one of (1) to (3) is conductively fixed to the land electrode of the circuit board, generation of noise on the capacitor-mounted circuit board can be suppressed. .

According to the multilayer ceramic capacitor of the present invention, when an AC voltage is applied between the terminal electrodes, the dielectric layer between the opposing electrodes in the internal electrode facing region alternately expands and contracts in the plane direction of the dielectric layer. Even if it repeats, since the displacement of the surface direction by this expansion and contraction is buffered by the notch, the displacement of the external electrode in the surface direction is suppressed. According to the capacitor-mounted circuit board of the present invention, the capacitor-mounted circuit board on which the multilayer ceramic capacitor is mounted is formed between the opposing internal electrodes in the internal electrode facing region when an AC voltage is applied between the external electrodes. Even if the dielectric layer repeats expansion and contraction alternately in the surface direction of the dielectric layer, the displacement in the surface direction due to the expansion and contraction is buffered by the notch, so that the external electrode is electrically fixed by soldering or the like. The change in the distance between the pair of land electrodes is suppressed, the occurrence of flexural vibration in the thickness direction of the circuit board is suppressed, and the generation of noise accompanying the flexural vibration of the board is suppressed. The above object and other objects, structural features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

Hereinafter, a first embodiment of a multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining the overall structure of the multilayer ceramic capacitor 10 of the first embodiment, and FIG. 1A is an external perspective view showing an example of the multilayer ceramic capacitor 10, and FIG. ) Is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB in FIG. FIG. 2 is an exploded perspective view for explaining the internal structure of the chip body 15 of the multilayer ceramic capacitor 10. FIG. 3 is a perspective view showing a state in each stage of the manufacturing process for explaining an example of the manufacturing process of the multilayer ceramic capacitor 10 of the present embodiment.

As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 10 of this embodiment includes a plurality of dielectric layers 11 a 1, 11 a 2, 11 b 1, 11 b 2 and a plurality of substantially rectangular internal electrodes 12 a, 12 b that are alternately stacked. A chip body 15 and a pair of external electrodes 16a and 16b formed on the surface of the chip body 15 and connected to a land electrode of an external circuit board, and the plurality of internal electrodes 12a and 12b are the pair of external electrodes. The external electrodes 16a and 16b are alternately electrically connected. In the chip body 15, the internal electrodes 12a and 12b connected to different external electrodes 16a and 16b are opposed to each other with the dielectric layers 11a1 and 11a2 interposed therebetween, and the internal electrode facing region OP. Of the internal electrode extraction regions LE in which the internal electrodes 12a and 12b of the OP are alternately extracted to the external electrodes 16a and 16b, notches 14a and 14b are formed in the internal electrode extraction region LE, respectively. It is.

Specifically, as shown in FIG. 1A, external electrodes are provided in the vicinity of the end surfaces of the end surface in the longitudinal direction of the substantially rectangular parallelepiped chip body 15 and four side surfaces extending in the longitudinal direction adjacent to the end surfaces. 16a and 16b are provided, and the length of a pair of opposing sides in the vicinity of the external electrodes 16a and 16b on one of the four side surfaces of the chip body 15 is longer than that of the other pair of sides. Also, long rectangular opening-shaped notches 14a and 14b are formed. As shown in FIGS. 1A and 2, the chip body 15 includes a first dielectric layer 11a1 having a first internal electrode 12a having a substantially rectangular shape on one main surface side, The internal electrodes 12a and 12b connected to the different external electrodes 16a and 16b are alternately laminated with the second dielectric layers 11a2 provided with the substantially rectangular second internal electrodes 12b on the main surface side. An internal electrode opposing region OP facing each other with the dielectric layers 11a1 and 11a2 in between, and an internal electrode extraction region LE in which the internal electrodes 12a and 12b of the internal electrode opposing region OP are alternately extracted to the external electrodes 16a and 16b. And make up. Cutouts 14a and 14b are formed in the internal electrode lead-out region LE, respectively. In addition, a plurality of dielectric layers 11b1 serving as a first cover layer are disposed on one end side in the stacking direction of the plurality of dielectric layers 11a1 and 11a2 provided with the internal electrodes 12a and 12b. A plurality of dielectric layers 11b2 serving as a second cover layer are disposed on the end side. Similarly, the plurality of dielectric layers 11b1 serving as the first cover layer are respectively disposed at positions overlapping the respective notches 14a and 14b of the dielectric layers 11a1 and 11a2 having the internal electrodes 12a and 12b in the stacking direction. Notches 14a and 14b are formed. On the other hand, the notches 14a and 14b are not formed in the plurality of dielectric layers 11b2 serving as the second cover layer. The first internal electrode 12a is disposed so as to be in contact with one short side on one main surface of the first dielectric layer 11a1 having a substantially rectangular shape, and cuts the internal electrode lead-out region LE. A margin region M1 in which no internal electrode exists is provided around the notch 14a so as to be separated from the notch by a predetermined distance or more. Similarly, the second internal electrode 12b is disposed so as to be in contact with one short side on one main surface of the substantially rectangular second dielectric layer 11a2, and the internal electrode lead-out A margin region M2 in which no internal electrode exists is provided around the notch 14b in the region LE so as to be separated from the notch by a predetermined distance or more.

As described above, the multilayer ceramic capacitor 10 of the present embodiment has the internal electrodes 12a and 12b connected to the external electrodes 16a and 16b different from each other in the chip body 15, as shown in a cross-sectional view in FIG. A notch 14a is formed in the internal electrode lead-out region LE where one internal electrode 12a of the internal electrode facing region OP facing each other across the dielectric layers 11a1 and 11a2 is drawn out to the external electrode 16a. A notch 14b is formed in the internal electrode extraction region LE where the other internal electrode 12b of the internal electrode facing region OP is extracted to the external electrode 16b.

Since the multilayer ceramic capacitor 10 of the present embodiment is configured as described above, when an AC voltage is applied between the external electrodes 16a and 16b of the multilayer ceramic capacitor 10, the internal electrode opposing region OP faces the internal electrode. Even if the dielectric layers 11a1 and 11a2 between the electrodes 12a and 12b repeatedly expand and contract alternately in the plane direction of the dielectric layers 11a1 and 11a2, the displacement in the plane direction due to the expansion and contraction causes the notches 14a and 14b. And the displacement of the external electrodes 16a and 16b in the surface direction is suppressed.

Next, an example of a method for manufacturing the multilayer ceramic capacitor 10 of the present embodiment will be described with reference to FIG. The first manufacturing flow shown in FIG. 3 is a typical example of the method for manufacturing the multilayer ceramic capacitor 10 of the present embodiment. First, a ceramic material powder mainly composed of barium titanate, an organic binder such as PVB (polyvinyl butyral), and an organic solvent such as ethanol are mixed at a predetermined ratio to prepare a ceramic slurry. After forming into a predetermined thickness by the sheet forming means, it is cut into a predetermined dimension to obtain a plurality of ceramic green sheets. Next, using a Ni electrode material paste, a Cu electrode material paste, or the like, a part of the plurality of ceramic green sheets obtained above has a substantially rectangular shape, and the electrode in the internal electrode lead-out region LE is A plurality of internal electrode patterns in which missing portions corresponding to the nonexistent margin region M are formed are formed by a screen printing method or the like. The obtained ceramic green sheets are alternately reversed and laminated so that the internal electrode facing area OP and the internal electrode lead area LE are provided, and the remaining ceramic green sheets are laminated on both ends, and are crimped. As shown to 3 (a), the ceramic green sheet laminated body 11 is obtained. In addition, it is preferable to print and form simultaneously the cut line which shows the cutting position at the time of cut | disconnecting to an individual laminated body chip | tip at the time of the printing formation of the said internal electrode on the ceramic green sheet surface. Next, as shown in FIG. 3B, a plurality of laminated chips 13 having a substantially rectangular parallelepiped shape are obtained by cutting along the cut line by pushing or the like. Next, chamfering is performed on the corners and ridges of the obtained laminate chip 13 as shown in FIG. Next, one of the four side surfaces extending in the longitudinal direction of the obtained laminated chip 13 is subjected to cutting with a drill or the like on one side surface which is one end in the stacking direction, and is shown in FIG. Thus, notches 14a and 14b continuous in the thickness direction are provided in a ceramic green sheet on which at least the internal electrode is printed and formed inside the multilayer chip 13. Next, the laminated chip 13 obtained above is fired at a predetermined temperature profile in a reducing atmosphere, and further subjected to re-oxidation heat treatment in a neutral or oxidizing atmosphere to obtain the chip body 15. Next, an external electrode material paste such as a Cu electrode material is applied by a dipping method or the like in the vicinity of both end surfaces in the longitudinal direction of the chip body 15 and four end surfaces extending in the longitudinal direction in contact with the end surfaces by a dipping method or the like. The multilayer ceramic capacitor 10 is obtained as shown in FIG. In the present invention, a Pd electrode paste, an Ag—Pd electrode paste, or the like may be used, and when these pastes are used, they may be fired in an air atmosphere.

Next, another example of the method for manufacturing the multilayer ceramic capacitor 10 of this embodiment will be described with reference to FIG. The second manufacturing flow shown in FIG. 3 is another example of the method for manufacturing the multilayer ceramic capacitor 10 of the present embodiment. First, the ceramic green sheet laminate 11 shown in FIG. 3A is obtained in the same manner as in the first manufacturing flow. Next, as shown in FIG. 3 (b ′), one main surface that is one end in the stacking direction of the obtained ceramic green sheet laminate 11 is cut by a drill or the like as described above, A plurality of notches 14, 14 are formed. The obtained ceramic green sheet laminate 11 is cut along a cut line in the same manner as described above, and a plurality of laminate chips 13 in which a pair of notches 14 and 14 are formed as shown in FIG. obtain. Next, chamfering is performed on the corners and ridges of the laminate chip 13 as shown in FIG. 3E using a rotating barrel, a sandblasting method, or the like. After firing the obtained multilayer chip 13 in the same manner as described above, the electrode material paste is applied and baked in the same manner as described above to obtain the multilayer ceramic capacitor 10 in the same manner as described above.

Next, a preferred embodiment of the dielectric layers 11a1 and 11a2 is as follows. That is, the dielectric layers 11a1 and 11a2 are preferably made of a dielectric ceramic mainly composed of barium titanate or the like. A ceramic green sheet is prepared from a ceramic slurry containing the dielectric ceramic material powder and an organic binder by a doctor blade method or the like, laminated as necessary, and then fired at a temperature at which the dielectric ceramic is sintered. It is done. The dielectric layers 11a1 and 11a2 are not limited to this, and other known ferroelectrics can be used.

Next, a preferred embodiment of the internal electrodes 12a and 12b is as follows. That is, the internal electrodes 12a and 12b may be a metal such as Ni or Cu or an alloy containing at least one of the metals. The internal electrodes 12a and 12b may be obtained by adding a small amount of the dielectric ceramic powder into the internal electrodes for the purpose of improving the adhesion to the dielectric layers 11a1 and 11a2. The internal electrodes 12a and 12b are preferably formed so as to be in contact with one short side of one main surface of the substantially rectangular dielectric layers 11a1 and 11a2.

Next, a preferred embodiment of the chip body 15 is as follows. That is, the chip body 15 is preferably in the shape of a substantially rectangular parallelepiped, but is not limited thereto, and may be, for example, a flat plate having a height smaller than the width and length.

Next, preferred embodiments of the external electrodes 16a and 16b are as follows. That is, the external electrodes 16a and 16b are preferably provided in the vicinity of the end surface of the chip body in the length direction and the end surfaces of the four side surfaces extending in contact with the length direction, but are not limited thereto. Instead, it may be provided only on the end face. The external electrodes 16a and 16b are preferably formed on the surface of the chip body 15 so as to be connected to the internal electrodes 12a and 12b. As a forming method, an electrode material paste such as Ni or Cu is applied and baked. It is preferably formed by coating and curing a conductive resin paste containing Ag powder, sputtering of an electrode material, or the like. Further, it is preferable to form Ni plating, Cu plating, solder plating or the like on the surfaces of the external electrodes 16a and 16b, if necessary.

Next, a preferred embodiment of the internal electrode facing region OP is as follows. That is, the internal electrode facing region OP is preferably disposed at the center in the longitudinal direction of the chip body.

Next, a preferred embodiment of the internal electrode lead-out region LE is as follows. That is, the internal electrode lead-out region LE is preferably disposed between the internal electrode facing region OP and the end surface of the chip body 15 where the external electrodes 16a and 16b are formed.

Next, a preferred embodiment of the notches 14a and 14b is as follows. That is, the notches 14a and 14b are preferably formed in the internal electrode lead-out region LE of the chip body 15. The notches 14a and 14b are preferably formed from one end side in the stacking direction of the dielectric layer, but are not limited thereto, and may be formed from the other end side in the stacking direction. Moreover, it may penetrate from one end side to the other end side in the stacking direction. The notches 14a and 14b are preferably formed so as to avoid positions where the external electrodes 16a and 16b on the surface of the chip body 15 are provided. Further, the notches 14a and 14b are preferably formed symmetrically on the center line extending in the length direction of the chip body 15, but the present invention is not limited to this. It may be formed at a biased position. In this case, it is preferable to form a point object across the internal electrode facing region OP. However, the present invention is not limited to this, and for example, a plurality of notches may be provided symmetrically on the left and right lines across a center line extending in the length direction of the chip body 15. The shape of the notches 14a and 14b is preferably a rectangular opening shape having long sides along the internal electrode facing region and the external electrode, but is not limited to this, and R is formed at the corners of both ends. The formed long hole shape may be sufficient and a round hole shape may be sufficient. The notches 14a and 14b may be filled with an insulating resin. In addition to using a jig such as a syringe, other methods may be used for filling the resin. The insulating resin filled in the notches 14a and 14b is preferably selected from silicone resin, epoxy resin and other insulating resins. Moreover, the said insulating resin is not limited to single, For example, you may contain an inorganic filler, a coloring agent, etc.

Next, a preferred embodiment of the margin areas M1 and M2 is as follows. In other words, the margin regions M1 and M2 are preferably provided as regions where no internal electrode exists in advance at a predetermined interval around the position where the notches 14a and 14b are formed when the internal electrode is formed.

Next, a first embodiment of the capacitor-mounted circuit board of the present invention using the multilayer ceramic capacitor 10 of the present embodiment will be described with reference to FIGS. FIG. 4 is a perspective view for explaining a state in which the multilayer ceramic capacitor 10 of the present embodiment is mounted on the land electrodes 23 a and 23 b of the circuit board 21. FIG. 5 is a diagram showing the capacitor-mounted circuit board 20 of the first embodiment using the multilayer ceramic capacitor 10 of the present embodiment, and FIG. 5C is an external perspective view of the main part. (D) is sectional drawing in the DD line | wire of the said FIG.5 (C).

The circuit board 21 used for the capacitor-mounted circuit board 20 of the present embodiment includes wirings 22a and 22b on at least one surface thereof, and includes land electrodes 23a and 23b connected to the wirings 22a and 22b. When mounting the multilayer ceramic capacitor 10 of this embodiment, as shown in FIG. 4, paste-like solders 24a and 24b are printed on the surfaces of the land electrodes 23a and 23b in advance using a metal mask or the like. Is preferred. Then, mounting is performed using an electronic component automatic mounting device (not shown) such that the external electrodes 16a and 16b of the multilayer ceramic capacitor 10 are in contact with the paste-like solders 24a and 24b applied on the land electrodes 23a and 23b. The external electrodes 16a and 16b of the multilayer ceramic capacitor 10 are conductively fixed to the land electrodes 23a and 23b of the circuit board 21 by solders 24a and 24b by heat treatment in a reflow soldering furnace.

In the capacitor-mounted circuit board 20 of this embodiment, as shown in FIG. 5C, the external electrodes 16a and 16b of the multilayer ceramic capacitor 10 of the first embodiment are connected to the wirings 22a and 22b of the circuit board 21. The land electrodes 23a and 23b are conductively fixed via solders 24a and 24b, respectively.

Then, as shown in FIG. 5D, the multilayer ceramic capacitor 10 of the capacitor-mounted circuit board 20 of the present embodiment includes external electrodes 16a electrically fixed to the land electrodes 23a and 23b of the circuit board 21 by solder. Since notches 14a and 14b are formed between 16b and the internal electrode facing region OP of the chip body 15, the wirings 22a and 22b and the land electrodes 23a and 23b of the circuit board 21 and the solders 24a and 24b are formed. When an AC voltage is applied to the pair of external electrodes 16a and 16b through the dielectric layers 11a1 and 11a2 between the opposing internal electrodes 12a and 12b of the internal electrode facing region OP, the dielectric layers 11a1 and 11a2 Even if the expansion and contraction are repeated alternately in the surface direction, the displacement in the surface direction due to the expansion and contraction is caused by the notches 14a and 14b. Is collision, the external electrodes 16a, is displaced to the surface direction of 16b is suppressed. And the change of the space | interval dimension of a pair of land electrode 23a, 23b electroconductively fixed to the said external electrode 16a, 16b with solder etc. is suppressed. For this reason, generation | occurrence | production of the bending vibration of the thickness direction of the said capacitor | condenser mounting circuit board 20 is suppressed, and generation | occurrence | production of the noise accompanying the bending vibration of this circuit board 21 is suppressed.

Next, a preferred embodiment of the circuit board 21 is as follows. That is, as the circuit board, wiring 22a made of a highly conductive metal such as Cu or the like on at least one principal surface of a paper phenolic resin board, a glass epoxy resin board, or other known resin board material, Those having 22b are preferred. Further, the present invention is not limited to this. For example, the wiring may be formed by applying and baking an electrode material paste containing Ag, Cu or the like on the surface of a ceramic substrate mainly composed of alumina or the like. Good.

Next, a preferred embodiment of the land electrodes 23a and 23b is as follows. That is, the land electrodes 23a and 23b are preferably formed on the resin substrate 21 in the same manner as the wirings 22a and 22b. In addition, the present invention is not limited to this, and as described above, for example, an electrode material paste such as Ag or Cu is applied and baked on the surface of a ceramic substrate made of alumina ceramic or the like, and formed simultaneously with the wiring. Also good.

(Example) Next, an example of the multilayer ceramic capacitor 10 of the first embodiment of the present invention will be described. The outer dimensions of the multilayer ceramic capacitor 10 are a width of 2.5 mm, a length of 3.2 mm, and a height of 2.5 mm. The length dimension of the internal electrode facing area OP is 2.6 mm, and the length dimension of the internal electrode lead area LE is 0.3 mm. On one side surface of the chip body 15 of the multilayer ceramic capacitor 10, notches 14a and 14b having a rectangular opening in which the length of a pair of opposing sides is longer than the length of the other pair of sides are formed. . The notches 14a and 14b have a width of 0.24 mm, a length of 1.52 mm, and a depth of 2.2 mm, and penetrate all the dielectric layers 11a1 and 11a2 having the internal electrodes of the internal electrode lead-out region LE. It is formed as follows. (Comparative Example) For the multilayer ceramic capacitor of the comparative example, which is the same as the multilayer ceramic capacitor 10 of the above example except that the notches 14a and 14b are not provided, the amplitude amount in the end face direction of the external electrode is obtained by simulation calculation. As a result of comparison, the amplitude of the end face of the ceramic capacitor 10 of this example was reduced by 25.4% compared to the amplitude of the end face of the multilayer ceramic capacitor of the comparative example. Further, land electrodes made of Cu foil having a width of 3 mm, a length of 5 mm, and a thickness of 35 μm are opposed to each other with a distance of 2 mm between the electrodes on the surface of a glass epoxy resin substrate having a width of 40 mm, a length of 100 mm, and a thickness of 1.6 mm. The above comparative example in which a solder paste is printed in advance on the land electrode of the evaluation circuit board using a metal mask, and the dielectric constant, the thickness of one layer, and the number of stacked layers of the dielectric layer in the internal electrode facing region OP are different. Each of the ceramic capacitors was mounted so that the external electrodes face the land electrodes, and a reflow soldering process was performed to prepare a capacitor-mounted circuit board sample. The capacitor mounted circuit board sample obtained above is set in a noise measuring device of model NL-14 manufactured by Rion Co., Ltd., and an AC voltage of DC20V, AC5V, 5Hz is applied between the land electrodes of the capacitor mounted circuit board sample. The noise generated by the flexural vibration of the substrate was measured with NL-14 placed at a position 10 mm apart. As a result, the noise generated from the capacitor-mounted circuit board of this example in which the amplitude amount in the end face direction of the external electrode 16a or 16b of the comparative example is reduced by 25.4% is the noise generated from the capacitor-mounted circuit board of the comparative example. It was confirmed that it was reduced by about 7%.

Next, a second embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to FIG. FIG. 6 is a view for explaining the entire structure of the multilayer ceramic capacitor 30 of the second embodiment, and FIG. 6E is an external perspective view showing an example of the multilayer ceramic capacitor 30, and FIG. ) Is a cross-sectional view of the multilayer ceramic capacitor 30 taken along line FF in FIG.

As shown in FIG. 6, the multilayer ceramic capacitor 30 according to the present embodiment is formed by alternately laminating a plurality of dielectric layers and a plurality of substantially rectangular internal electrodes 32a and 32b, as in the first embodiment. A chip body 35 and a pair of external electrodes 36a and 36b formed on the surface of the chip body 35 and connected to the land electrodes of an external circuit board, and the plurality of internal electrodes 32a and 32b are The pair of external electrodes 36a and 36b are electrically connected alternately. As in the first embodiment, the internal electrode facing region in which the internal electrodes 32a and 32b connected to the different external electrodes 36a and 36b in the chip body 35 face each other with the dielectric layer interposed therebetween. Of the OP and the internal electrode extraction region LE in which the internal electrodes 32a and 32b of the internal electrode facing region OP are alternately extracted to the external electrodes 36a and 36b, notches 34a are respectively formed in the internal electrode extraction region LE. , 34b are formed. The multilayer ceramic capacitor 30 according to this embodiment is different from the first embodiment in that insulating resins 37a and 37b are filled in the notches 34a and 34b of the internal electrode lead-out region LE. .

Specifically, as shown in FIG. 6 (E), a partial electrode is formed in the vicinity of the end face of each of the end face in the longitudinal direction of the substantially rectangular parallelepiped chip body 35 and four side faces extending in the longitudinal direction adjacent to the end face. 36a and 36b are provided, and the length of a pair of sides facing each other in the vicinity of the external electrodes 36a and 36b on one of the four side surfaces of the chip body 35 is longer than that of the other pair of sides. Long rectangular opening-shaped notches 34a and 34b are formed. As schematically shown in FIG. 6F, the chip body 35 has a first internal electrode 32a having a substantially rectangular shape on one main surface side, as in the first embodiment. And the second dielectric layer provided with the substantially rectangular second internal electrode 32b on one main surface side are alternately stacked and connected to different external electrodes 36a and 36b. An internal electrode facing region OP in which the internal electrodes 32a and 32b are opposed to each other with the dielectric layer in between, and the internal electrodes 32a and 32b in the internal electrode facing region OP are alternately drawn out to the external electrodes 36a and 36b. An electrode lead-out region LE is configured. Cutouts 34a and 34b are formed in the internal electrode lead-out region LE, respectively. A plurality of dielectric layers serving as a first cover layer are disposed on one end side in the stacking direction of the plurality of dielectric layers provided with the internal electrodes 32a and 32b, and on the other end side. A plurality of dielectric layers serving as a second cover layer; Similarly, the plurality of dielectric layers serving as the first cover layer have notches 34a, 34a, 34a, 34b, respectively, at positions overlapping the respective notches 34a, 34b of the dielectric layer having the internal electrodes 32a, 32b in the stacking direction. 34b is formed. The first internal electrode 32a is disposed so as to be in contact with one short side on one main surface of the first dielectric layer having a substantially rectangular shape as in the first embodiment, A margin region M3 in which no internal electrode exists is provided around the notch 34a of the internal electrode lead-out region LE so as to be separated from the notch by a predetermined distance or more. Similarly, the second internal electrode 32b is disposed so as to be in contact with one short side on one main surface of the substantially rectangular second dielectric layer, and the internal electrode lead-out region A margin region M4 where no internal electrode exists is provided around the notch 34b of the LE so as to be separated from the notch by a predetermined distance or more.

As described above, the multilayer ceramic capacitor 30 of the present embodiment has the internal electrodes 32a and 32b connected to the external electrodes 36a and 36b different from each other in the chip body 35, as shown in the sectional view of FIG. A notch 34a is formed in the internal electrode lead region LE in which one internal electrode 32a of the internal electrode facing region OP facing each other across the dielectric layer is drawn to the external electrode 36a, and the internal electrode A cutout 34b is formed in the internal electrode lead-out region LE where the other internal electrode 32b of the electrode facing region OP is drawn out to the external electrode 36b, and insulating resin 37a, 37b is filled. For this reason, the strength of the chip body 35 of the multilayer ceramic capacitor 30 is prevented from lowering, and the occurrence of a suction error due to the nozzle during mounting is prevented, thereby facilitating handling.

Next, a second embodiment of the capacitor-mounted circuit board of the present invention using the multilayer ceramic capacitor 30 of the second embodiment will be described with reference to FIG. FIG. 7 is a diagram showing a capacitor-mounted circuit board 40 of the second embodiment using the multilayer ceramic capacitor 30 of the present embodiment. FIG. 7G is an external perspective view of the main part, and FIG. ) Is a cross-sectional view taken along the line H-H in FIG.

As shown in FIG. 7G, the circuit board 41 used in the capacitor-mounted circuit board 40 of the present embodiment is wired on at least one main surface in the same manner as the circuit board 21 of the first embodiment. 42a and 42b, and land electrodes 43a and 43b connected to the wirings 42a and 42b.

In the capacitor-mounted circuit board 40 of this embodiment, the external electrodes 36a and 36b of the multilayer ceramic capacitor 30 of the second embodiment are connected to the wirings 42a and 42b of the circuit board 41, as shown in FIG. The land electrodes 43a and 43b are conductively fixed via solders 44a and 44b, respectively.

Then, as shown in FIG. 7H, the multilayer ceramic capacitor 30 of the capacitor-mounted circuit board 40 of the present embodiment has external electrodes 36a electrically conductively fixed to the land electrodes 43a and 43b of the circuit board 41 by solder. Notches 34a, 34b are formed between the chip 36b and the internal electrode facing region OP of the chip body 35, and the notches 34a, 34b are filled with insulating resins 37a, 37b, respectively. When an AC voltage is applied to the pair of external electrodes 36a and 36b via the wirings 42a and 42b of the substrate 41, the land electrodes 43a and 43b, and the solders 44a and 44b, the internal electrodes facing each other in the internal electrode facing region OP Even if the dielectric layer between 32a and 32b repeatedly expands and contracts alternately in the surface direction of the dielectric layer, the surface direction due to the expansion and contraction The displacement is buffered by the notches 34a and 34b filled with the insulating resins 37a and 37b having flexibility compared to the chip body 35, and the displacement of the external electrodes 36a and 36b in the surface direction is suppressed. The And the change of the space | interval dimension of a pair of land electrode 43a, 43b electrically fixed to the said external electrodes 36a, 36b with solder | solder etc. is suppressed. For this reason, generation | occurrence | production of the bending vibration of the thickness direction of the said capacitor | condenser mounting circuit board 40 is suppressed, and generation | occurrence | production of the noise accompanying the bending vibration of this circuit board 41 is suppressed.

Next, a third embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 8 is a cross-sectional view for explaining the overall structure of the multilayer ceramic capacitor 50 of the third embodiment. FIG. 9 is an exploded perspective view for explaining the internal structure of the chip body 55 of the multilayer ceramic capacitor 50.

As shown in FIGS. 8 and 9, the multilayer ceramic capacitor 50 according to the present embodiment includes a plurality of dielectric layers 51 a 1, 51 a 2, 51 b 1, 51 b 2 and a plurality of substantially rectangular internal electrodes 52 a, 52 b that are alternately stacked. A chip body 55 and a pair of external electrodes 56a and 56b formed on the surface of the chip body 55 and connected to a land electrode of an external circuit board, and the plurality of internal electrodes 52a and 52b are the pair of external electrodes. The external electrodes 56a and 56b are electrically connected alternately. In the chip body 55, the internal electrodes 52a and 52b connected to the different external electrodes 56a and 56b are opposed to each other with the dielectric layers 51a1 and 51a2 interposed therebetween, and the internal electrode facing region. Of the internal electrode extraction regions LE in which the internal electrodes 52a and 52b of the OP are alternately extracted to the external electrodes 56a and 56b, notches 54a and 54b are formed in the internal electrode extraction region LE. is there.

Specifically, as shown in FIG. 8, external electrodes 56a and 56b are provided in the vicinity of the end surfaces of the end surface in the longitudinal direction of the substantially rectangular parallelepiped chip body 55 and the four side surfaces extending in the longitudinal direction adjacent to the end surfaces. And a pair of sides facing each other in the vicinity of the external electrodes 56a and 56b so as to reach from one of the four sides of the chip body 55 to the other side facing the side. A rectangular opening-shaped notch 54a, 54b having a length longer than that of the other pair of sides is formed. As in the first embodiment, the chip body 55 includes a first dielectric having a substantially rectangular first internal electrode 52a on one main surface side, as shown in FIGS. The body layers 51a1 and the second dielectric layers 51a2 provided with the substantially rectangular second internal electrodes 52b on one main surface side are alternately stacked and connected to different external electrodes 56a and 56b. The internal electrodes 52a and 52b are opposed to each other with the dielectric layers 51a1 and 51a2 interposed therebetween, and the internal electrodes 52a and 52b of the internal electrode facing region OP are alternately arranged on the external electrodes 56a and 56b. An internal electrode extraction region LE to be extracted is configured. Cutouts 54a and 54b are formed in the internal electrode lead-out region LE, respectively. In addition, a plurality of dielectric layers 51b1 serving as a first cover layer are disposed on one end side in the stacking direction of the plurality of dielectric layers 51a1 and 51a2 provided with the internal electrodes 52a and 52b. A plurality of dielectric layers 51b2 serving as a second cover layer are provided on the end side. The plurality of dielectric layers 51b1 serving as the first cover layer are similar to the positions overlapping the respective notches 54a and 54b of the dielectric layers 51a1 and 51a2 having the internal electrodes 52a and 52b, respectively. Notches 54a and 54b are formed in the upper and lower portions. Further, unlike the first embodiment, each of the plurality of dielectric layers 51b2 serving as the second cover layer is also provided with the respective notches 54a of the dielectric layers 51a1 and 51a2 having the internal electrodes 52a and 52b. , 54b are similarly formed with notches 54a, 54b at positions overlapping with the stacking direction. The first internal electrode 52a is disposed so as to be in contact with one short side on one main surface of the first dielectric layer 51a1 having a substantially rectangular shape, and cuts the internal electrode lead-out region LE. A margin region M5 in which no internal electrode exists is provided around the notch 54a so as to be separated from the notch by a predetermined distance or more. Similarly, the second internal electrode 52b is disposed so as to be in contact with one short side on one main surface of the substantially rectangular second dielectric layer 51a2, and the internal electrode lead-out A margin region M6 in which no internal electrode exists is provided around the notch 54b in the region LE so as to be separated from the notch by a predetermined distance or more.

As described above, in the multilayer ceramic capacitor 50 of the present embodiment, the internal electrodes 52a and 52b connected to the different external electrodes 56a and 56b in the chip body 55 are the same as shown in FIG. A notch 54a is formed in the internal electrode lead-out region LE in which one internal electrode 52a of the internal electrode facing region OP facing each other across the dielectric layers 51a1 and 51a2 is drawn out to the external electrode 56a. A notch 54b is formed in the internal electrode extraction region LE where the other internal electrode 52b of the electrode facing region OP is extracted to the external electrode 56b. Since the operational effects of this embodiment are the same as those of the first embodiment, description thereof is omitted.

Next, a fourth embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 10 is an external perspective view for explaining the overall structure of the multilayer ceramic capacitor 60 of the fourth embodiment. FIG. 11 is an exploded perspective view for explaining the internal structure of the chip body 65 of the multilayer ceramic capacitor 60.

As shown in FIGS. 10 and 11, the multilayer ceramic capacitor 60 of the present embodiment includes a plurality of dielectric layers 61 a 1, 61 a 2, 61 b 1, 61 b 2 and a plurality of substantially rectangular internal electrodes 62 a, 62 b that are alternately stacked. A chip body 65 and a pair of external electrodes 66a and 66b formed on the surface of the chip body 65 and connected to a land electrode of an external circuit board, and the plurality of internal electrodes 62a and 62b are the pair of external electrodes. The external electrodes 66a and 66b are alternately electrically connected. In the chip body 65, the internal electrodes 62a and 62b connected to the different external electrodes 66a and 66b are opposed to each other with the dielectric layers 61a1 and 61a2 interposed therebetween, and the internal electrode facing region. Of the internal electrode extraction regions LE in which the internal electrodes 62a and 62b of the OP are alternately extracted to the external electrodes 66a and 66b, notches 64a and 64b are formed in the internal electrode extraction region LE. is there.

Specifically, as shown in FIG. 10, external electrodes 66a and 66b are disposed in the vicinity of the end surfaces of the end surface in the longitudinal direction of the substantially rectangular parallelepiped chip body 65 and the four side surfaces adjacent to the end surfaces in the longitudinal direction. In the vicinity of the external electrodes 66a and 66b on one of the four side surfaces of the chip body 65, notches 64a, 64a, 64b and 64b having circular openings are formed on the chip body. A plurality of lines are formed symmetrically with respect to a center line extending in the longitudinal direction. As in the first embodiment, the chip body 65 has a first dielectric having a substantially rectangular first internal electrode 62a on one main surface side, as shown in FIGS. The body layers 61a1 and the second dielectric layers 61a2 provided with the substantially rectangular second internal electrodes 62b on one main surface side are alternately stacked and connected to different external electrodes 66a and 66b. The internal electrode facing region OP in which the internal electrodes 62a and 62b face each other with the dielectric layers 61a1 and 61a2 interposed therebetween, and the internal electrodes 62a and 62b in the internal electrode facing region OP alternate with the external electrodes 66a and 66b. An internal electrode extraction region LE to be extracted is configured. A pair of notches 64a, 64a, 64b and 64b are formed in the internal electrode lead-out region LE. A plurality of dielectric layers 61b1 serving as a first cover layer are disposed on one end side in the stacking direction of the plurality of dielectric layers 61a1 and 61a2 provided with the internal electrodes 62a and 62b. A plurality of dielectric layers 61b2 serving as a second cover layer are provided on the end side. The plurality of dielectric layers 61b1 serving as the first cover layer are respectively similar to the positions overlapping the respective notches 64a and 64b of the dielectric layers 61a1 and 61a2 having the internal electrodes 62a and 62b in the stacking direction. Cutouts 64a and 64b are formed in the upper part. On the other hand, the notches are not formed in the plurality of dielectric layers 61b2 serving as the second cover layer. The first internal electrode 62a is disposed so as to be in contact with one short side on one main surface of the first dielectric layer 61a1 having a substantially rectangular shape, and cuts the internal electrode lead-out region LE. A margin region M7 in which no internal electrode exists is provided around the notch 64a so as to be separated from the notch by a predetermined distance or more. Similarly, the second internal electrode 62b is disposed so as to be in contact with one short side on one main surface of the substantially rectangular second dielectric layer 61a2, and the internal electrode lead-out A margin region M8 in which no internal electrode exists is provided around the notch 64b of the region LE so as to be separated from the notch by a predetermined distance or more.

As described above, the multilayer ceramic capacitor 60 according to the present embodiment includes an internal electrode 62a connected to different external electrodes 66a and 66b in the chip body 65 as shown in an exploded perspective view of the chip body 65 in FIG. , 62b are opposed to each other with the dielectric layers 61a1 and 61a2 interposed therebetween, and a notch 64a is formed in the internal electrode lead region LE in which one internal electrode 62a of the internal electrode facing region OP is drawn to the external electrode 66a. In addition, a notch 64b is formed in the internal electrode extraction region LE where the other internal electrode 62b of the internal electrode facing region OP is extracted to the external electrode 66b. This embodiment is suitable for a multilayer ceramic capacitor in which the mechanical strength of the chip body is relatively low.

Next, a fifth embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 12 is an external perspective view for explaining the overall structure of the multilayer ceramic capacitor 70 of the fifth embodiment. FIG. 13 is an exploded perspective view for explaining the internal structure of the chip body 75 of the multilayer ceramic capacitor 70.

As shown in FIGS. 12 and 13, the multilayer ceramic capacitor 70 of this embodiment has a plurality of dielectric layers 71 a 1, 71 a 2, 71 b 1, 71 b 2 and a plurality of substantially rectangular internal electrodes 72 a, 72 b that are alternately stacked. A chip body 75 and a pair of external electrodes 76a and 76b formed on the surface of the chip body 75 and connected to land electrodes of an external circuit board, and the plurality of internal electrodes 72a and 72b are the pair of external electrodes. The external electrodes 76a and 76b are alternately electrically connected. In the chip body 75, the internal electrodes 72a and 72b connected to the different external electrodes 76a and 76b are opposed to each other with the dielectric layers 71a1 and 71a2 interposed therebetween, and the internal electrode facing region. Of the internal electrode extraction regions LE in which the internal electrodes 72a and 72b of the OP are alternately extracted to the external electrodes 76a and 76b, notches 74a and 74b are formed in the internal electrode extraction region LE, respectively. It is.

Specifically, as shown in FIG. 12, external electrodes 76a and 76b are disposed in the vicinity of the end surfaces of the end surface in the longitudinal direction of the substantially rectangular parallelepiped chip body 75 and the four side surfaces adjacent to the end surfaces in the longitudinal direction. In the vicinity of the external electrodes 76a and 76b on one of the four side surfaces of the chip body 75, notches 74a and 74b each having a long hole shape are formed in the longitudinal direction of the chip body 75. It is formed point-symmetrically across the internal electrode facing region OP at a position deviated to one side from a center line extending in the direction. As in the first embodiment, the chip body 75 has a first dielectric having a substantially rectangular first internal electrode 72a on one main surface side, as shown in FIGS. The body layer 71a1 and the second dielectric layer 71a2 provided with the substantially rectangular second internal electrode 72b on one main surface side are alternately stacked and connected to different external electrodes 76a and 76b. The internal electrodes 72a and 72b are opposed to each other with the dielectric layers 71a1 and 71a2 interposed therebetween, and the internal electrodes 72a and 72b in the internal electrode facing region OP are alternately arranged on the external electrodes 76a and 76b. An internal electrode extraction region LE to be extracted is configured. Cutouts 74a and 74b are formed in the internal electrode lead-out region LE, respectively. A plurality of dielectric layers 71b1 serving as a first cover layer are disposed on one end side in the stacking direction of the plurality of dielectric layers 71a1 and 71a2 provided with the internal electrodes 72a and 72b. A plurality of dielectric layers 71b2 serving as a second cover layer are provided on the end side. The plurality of dielectric layers 71b1 serving as the first cover layer are respectively similar to the positions overlapping the respective notches 74a and 74b of the dielectric layers 71a1 and 71a2 having the internal electrodes 72a and 72b in the stacking direction. Notches 74a and 74b are formed in the upper and lower portions. On the other hand, the notches are not formed in the plurality of dielectric layers 71b2 serving as the second cover layer. The first internal electrode 72a is disposed so as to be in contact with one short side on one main surface of the first dielectric layer 71a1 having a substantially rectangular shape, and cuts the internal electrode lead-out region LE. A margin region M9 in which no internal electrode exists is provided around the notch 74a so as to be separated from the notch by a predetermined distance or more. Similarly, the second internal electrode 72b is disposed so as to be in contact with one short side on one main surface of the substantially rectangular second dielectric layer 71a2, and the internal electrode lead-out A margin region M10 in which no internal electrode exists is provided around the notch 74b in the region LE so as to be separated from the notch by a predetermined distance or more.

As described above, the multilayer ceramic capacitor 70 according to the present embodiment includes an internal electrode 72a connected to different external electrodes 76a and 76b in the chip body 75, as shown in an exploded perspective view of the chip body 75 in FIG. 72b is formed in the internal electrode lead-out region LE where one of the internal electrodes 72a of the internal electrode facing region OP facing each other across the dielectric layers 71a1 and 71a2 is drawn out to the external electrode 76a. In addition, a notch 74b is formed in the internal electrode extraction region LE where the other internal electrode 72b of the internal electrode facing region OP is extracted to the external electrode 76b. Since the operational effects of this embodiment are the same as those of the first embodiment, description thereof is omitted.

The present invention is suitable for multilayer ceramic capacitors and capacitor-mounted circuit boards used in various thin electronic devices.

1A and 1B are an external perspective view and a cross-sectional view showing an overall structure of a first embodiment of a multilayer ceramic capacitor of the present invention. It is a disassembled perspective view which shows the internal structure of the multilayer ceramic capacitor of the said 1st Embodiment. It is a perspective view for demonstrating the example of the manufacturing method of the multilayer ceramic capacitor of the said 1st Embodiment. It is a perspective view of the principal part for demonstrating the method to mount the multilayer ceramic capacitor of the said 1st Embodiment on a circuit board. It is the perspective view and sectional drawing which show the structure of the principal part of 1st Embodiment of the capacitor | condenser mounting circuit board of this invention using the multilayer ceramic capacitor of the said 1st Embodiment. It is the external appearance perspective view and sectional drawing which show the whole structure of 2nd Embodiment of the multilayer ceramic capacitor of this invention. It is the perspective view and sectional drawing which show the structure of the principal part of 2nd Embodiment of the capacitor | condenser mounting circuit board of this invention using the multilayer ceramic capacitor of the said 2nd Embodiment. It is sectional drawing which shows the whole structure of 3rd Embodiment of the multilayer ceramic capacitor of this invention. It is a disassembled perspective view for demonstrating the internal structure of the multilayer ceramic capacitor of the said 3rd Embodiment. It is an external appearance perspective view which shows the whole structure of 4th Embodiment of the multilayer ceramic capacitor of this invention. It is a disassembled perspective view for demonstrating the internal structure of the multilayer ceramic capacitor of the said 4th Embodiment. It is an external appearance perspective view which shows the whole structure of 5th Embodiment of the multilayer ceramic capacitor of this invention. It is a disassembled perspective view for demonstrating the internal structure of the multilayer ceramic capacitor of the said 5th Embodiment. It is an external appearance perspective view which shows an example of background art.

Explanation of symbols

10: multilayer ceramic capacitor 11: ceramic green sheet laminates 11a1, 11a2, 11b1, 11b2: dielectric layers 12a, 12b: internal electrodes 13: laminate chips 14, 14a, 14b: notches 15: chip bodies 16a, 16b: External electrode 20: Capacitor-mounted circuit board 21: Circuit boards 22a, 22b: Wirings 23a, 23b: Land electrodes 24a, 24b: Solder 30: Multilayer ceramic capacitors 32a, 32b: Internal electrodes 34a, 34b: Notches 35: Chip body 36a 36b: External electrodes 37a, 37b: Insulating resin 40: Capacitor-mounted circuit board 41: Circuit boards 42a, 42b: Wiring 43a, 43b: Land electrodes 44a, 44b: Solder 50: Multilayer ceramic capacitors 51a1, 51a2, 51b1, 51b2 : Dielectric layer 5 a, 52b: internal electrodes 54a, 54b: notches 55: chip bodies 56a, 56b: external electrodes 60: multilayer ceramic capacitors 61a1, 61a2, 61b1, 61b2: dielectric layers 62a, 62b: internal electrodes 64a, 64b: notches 65: Chip bodies 66a, 66b: External electrodes 70: Multilayer ceramic capacitors 71a1, 71a2, 71b1, 71b2: Dielectric layers 72a, 72b: Internal electrodes 74a, 74b: Notches 75: Chip bodies 76a, 76b: External electrodes OP: Internal electrode facing region LE: Internal electrode lead-out region M1, M2, M3, M4, M5, M6, M7, N8, N9, M10: Margin region

Claims (4)

A chip body formed by alternately laminating a plurality of dielectric layers and a plurality of substantially rectangular internal electrodes, and a pair of external electrodes formed on the surface of the chip body and connected to a land electrode of an external circuit board In the multilayer ceramic capacitor in which the plurality of internal electrodes are alternately electrically connected to the pair of external electrodes, the chip body is connected to different external electrodes of the pair of external electrodes. Of the internal electrode facing region in which the internal electrodes face each other with the dielectric layer in between, and the internal electrode leading region in which the internal electrodes in the internal electrode facing region are alternately pulled out to the external electrode, the internal electrode A multilayer ceramic capacitor, wherein a notch is formed in each of the drawing regions. 2. The multilayer ceramic capacitor according to claim 1, wherein a margin region in which each internal electrode does not exist is provided around the notch in the internal electrode lead-out region. The multilayer ceramic capacitor according to claim 1, wherein an insulating resin is filled in the cutout in the internal electrode lead-out region. 4. A capacitor-mounted circuit board, wherein the external electrode of the multilayer ceramic capacitor according to claim 1 is conductively fixed to a land electrode of the circuit board.

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