JP2004296936A - Ceramic electronic component - Google Patents

Ceramic electronic component Download PDF

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Publication number
JP2004296936A
JP2004296936A JP2003089363A JP2003089363A JP2004296936A JP 2004296936 A JP2004296936 A JP 2004296936A JP 2003089363 A JP2003089363 A JP 2003089363A JP 2003089363 A JP2003089363 A JP 2003089363A JP 2004296936 A JP2004296936 A JP 2004296936A
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JP
Japan
Prior art keywords
conductive resin
layers
component
ceramic electronic
electronic component
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JP2003089363A
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Japanese (ja)
Inventor
Harunori Tanda
晴規 反田
Tsutomu Iemura
努 家村
Tadakatsu Asano
忠克 浅野
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Kyocera Corp
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Kyocera Corp
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Priority to JP2003089363A priority Critical patent/JP2004296936A/en
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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic electronic component having an impact strength capability when surface-mounted onto a wiring board, and capable of preventing both excess creeping of solder up to an external electrode and a crack caused by an unnecessary stress. <P>SOLUTION: The ceramic component includes a component main body 1 of a rectangular parallelepiped, constituted of a ceramic member having internal conductors 3, 4 formed thereon; underlaying conductive layers 5a, 6a connected to the internal conductors 3, 4 and formed in such a way as bridging between the end surface and the main surface of the component main body 1; and external electrodes 5, 6 constituted of conductive resin layers 5b, 6b formed on a ridge between the end surface and the main surface of the component main body 1, so as to cover the underlaying conductive layers 5a, 6a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、セラミック電子部品に関し、特に直方体の部品本体の一方の端面に複数の外部電極を有するセラミック電子部品の外部電極の構造に関するものである。
【0002】
【従来の技術】
代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。
【0003】
図3は、従来の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【0004】
図に示すように、多連型コンデンサ30の積層体31(部品本体)は、誘電体層32を複数積層して形成されている。
【0005】
また、積層体31の各誘電体層32間に、例えば複数の第1及び第2の内部電極(内部導体)33、34が対向形成され、第1の内部電極33は積層体31の一端面に、第2の内部電極34は積層体31の他端面に延出している。
【0006】
さらに、複数の外部電極35、36は、積層体31の端面及びこの端面に接する主面にまたがって形成されている。これにより、外部電極35、36の端面部分で、第1及び第2の内部電極33、34と接続している。また、外部電極35、36の主面部分(実装面)は、配線基板との実装が確実のものとしている。
【0007】
また、外部電極35、36の表面には、必要に応じて、表面メッキ層(図示せず)が形成されている。
【0008】
このような多連型コンデンサ30は、一方の主面(実装面)を下にして配線基板上の配線パターンに半田や導電性接着剤などの接合材により表面実装される。
【0009】
ここで、近年、多連型コンデンサ30は、携帯型電話機や携帯型コンピュータなどの携帯型電子機器への需要が増えてきている。
【0010】
しかしながら、携帯型電子機器は、使用時や携帯時において、落下などによる衝撃が、機器内部の配線基板に実装されている多連型コンデンサ30に加わり、図3に示すように、多連型コンデンサ30にクラック38が発生するという問題点があった。
【0011】
そこで、図4に示すように、複数積層された誘電体層42間に内部電極(内部導体)43、44が形成された直方体の積層体(部品本体)41と、内部電極43、44に接続するとともに、積層体41の端面と主面とにまたがるように形成された下地導体層45a、46aと、下地導体層45a、46aの主面部及び積層体41主面にまたがるように形成された導電性樹脂層45b、46bとからなる外部電極45、46とを備えた多連型コンデンサ40が特開2003−7567号公報に開示されている。
【0012】
【特許文献1】
特開2003−7567号公報 (3−5頁、図1−13)
【0013】
【発明が解決しようとする課題】
しかしながら、近年、発明者の調査によれば、積層体41の稜線部と外部電極45、46と接合材13が接している部分を起点としてクラック38が発生し、積層体41の側面に進行することがわかってきている。このため、図4に示す多連型コンデンサ40では、落下などによる衝撃が厳しくなった場合、クラック38の発生を防止するには限界があった。
【0014】
本発明は上述の問題点に鑑みて案出されたものであり、その目的は、耐衝撃性に優れたセラミック電子部品を提供することにある。
【0015】
【課題を解決するための手段】
本発明は、内部導体が形成されたセラミックス部材からなる直方体の部品本体と、前記内部導体に接続するとともに、前記部品本体の端面と主面とにまたがるように形成された下地導体層と、前記部品本体の端面と主面との稜線部上に形成された導電性樹脂層とからなる外部電極とを備えている。
【0016】
【作用】
本発明のセラミック電子部品によれば、内部導体が形成されたセラミックス部材からなる直方体の部品本体と、内部導体に接続するとともに、部品本体の端面と主面とにまたがるように形成された下地導体層と、下地導体層を被覆するように、部品本体の端面と主面との稜線部上に形成された導電性樹脂層とからなる外部電極とを備えてなる。即ち、端面下地導体層の中央部分が露出するように形成されている。このため、セラミック電子部品を半田などの接合材により配線基板上に表面実装した状態で、落下などによる衝撃がセラミック電子部品に加わっても、クラックの発生を低減できる。
【0017】
すなわち、落下などによる衝撃により、セラミック電子部品にねじり方向の応力が加わる場合が多い。そしてこのとき、部品本体の稜線と外部電極と接合材が接している部分を起点としてクラックが発生し、部品本体の側面に進行すると考えられるが、下地導体層を被覆するように、部品本体の端面と主面との稜線部上に導電性樹脂層が形成されているため、部品本体の稜線を被覆する外部電極の厚みが大きくなっており、ねじり方向の応力から部品本体を保護することから、クラックの発生を低減できると考えられる。また、導電性樹脂層が適度に変形するため、ねじり方向の応力が上記起点に伝わることを防ぐことができ、このことによっても、クラックの発生を低減できると考えられる。
【0018】
また、導電性樹脂層は部品本体の端面と主面との稜線部上のみに形成されているため、セラミック電子部品を接合材により配線基板上に表面実装した場合、半田は実装面と反対側の導電性樹脂層を乗り越えてはい上がることはなく、積層体において応力が発生する位置が低くなる。さらに、セラミック電子部品の寸法ばらつきを抑制できる。
【0019】
【発明の実施の形態】
以下、本発明のセラミック電子部品を図面に基づいて説明する。
【0020】
代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。
【0021】
図1は、本発明の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)は縦断面図である。図2は、図1の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。
【0022】
図において、10は多連型コンデンサ(セラミック電子部品)、1は誘電体セラミックから積層体(部品本体)、2は誘電体層、3、4は内部電極、5、6は外部電極である。また、11は配線基板、12は配線パターン、13は半田(接合材)である。
【0023】
図1に示すように、多連型コンデンサ10の積層体1は、誘電体層2を複数積層して形成されている。
【0024】
誘電体層2は、チタン酸バリウム(BaTiO)を主成分とする非還元性誘電体材料、及びガラス成分を含む誘電体材料からなり、その形状は、2.0mm×1.2mmなどであり、その厚みは高容量化のために1〜5μmとしている。この誘電体層2が図上、上方向に積層して積層体1が構成される。なお、誘電体層2の形状、厚み、積層数は容量値によって任意に変更することができる。
【0025】
積層体1の各誘電体層2間に、例えば複数の内部電極3、4が対向形成され、それぞれ積層体1の両端面に延出している。内部電極3、4は、例えばNiを主成分とする材料から構成され、その厚みは1〜2μmとしている。
【0026】
外部電極5、6は、積層体1の一対の長辺側端面に被着形成され、且つ内部電極3、4にそれぞれ接続されている。さらに、外部電極5、6の表面には、表面メッキ層(図示せず)が形成されている。表面メッキ層は、例えばNiメッキ、Snメッキ、半田メッキなどが例示できる
本発明の特徴的なことは、外部電極5、6は、内部電極3、4に接続するとともに、積層体1の端面と主面とにまたがるように形成された下地導体層5a、6aと、下地導体層5a、6aを被覆するように、積層体1の端面に形成された端面下地導体層5a、6aの中央部分を露出させて、積層体1の端面と主面との稜線部上に形成された導電性樹脂層5b、6bとからなることである。
【0027】
下地導体層5a、6aは、例えばCu、Ni、あるいはこれらの合金などの卑金属成分及びガラス成分からなり、長辺側の端面及びそれに隣接する2つの主面(一方は実装面となる)の3面にわたって形成される。
【0028】
導電性樹脂層5b、6bは、エポキシ樹脂、フェノール樹脂、アクリル樹脂等の熱硬化性樹脂に、Cu、Ni、Agなどの導電性粉末が含有させて構成されている。
【0029】
ここで、導電性樹脂層5b、6bが夫々積層体1主面から積層体1の端面に回り込む量ybは、多連型コンデンサ10の高さ方向の寸法をTとした場合、0.05≦yb/T≦0.3の範囲にあることが望ましい。すなわち、yb/Tが0.05未満の場合、落下などによる衝撃が多連型コンデンサ10に加わった際に、クラック38の発生を低減する効果が十分現れない。一方、yb/Tが0.3未満の場合、実装面側(あるいは反対側)の一対の導電性樹脂層5b、6bを形成した後、実装面と反対側(あるいは実装面側)の一対の導電性樹脂層5b、6bを形成する方法により、精度良く導電性樹脂層5b、6bを形成することができず、多連型コンデンサ10のW方向の寸法ばらつきが大きくなる。
【0030】
また、クラック38の発生を効果的に低減するためには、稜線を被覆する外部電極5、6の厚みをrt、積層体1の稜線の部分の丸みの曲率半径をr1とした場合、rt/r1比は0.25以上であることが望ましい。
【0031】
以下、本発明の多連型コンデンサ10の製造方法について説明する。なお、各符号は焼成の前後で区別しないものとする。
【0032】
まず、誘電体層となるセラミックグリーンシート2上に、導電ペーストをスクリーン印刷で形成し、内部電極となる導体膜3、4を形成する。
【0033】
そして、このようなセラミックグリーンシート2を、導体膜3、4が互いに対向し、且つ導体膜3、4が互いに異なる端面に延出するように所定の積層枚数重ねた後、切断して各コンデンサユニットNを含む未焼成状態の積層体1とし、所定の雰囲気、温度、時間を加えて焼成する。これにより、積層体1の一対の端面には、各コンデンサユニットN毎に内部電極3、4が露出している。
【0034】
その後、各コンデンサユニットNを外部と電気的に接続するために、外部電極の下地導体層となる導体膜5a、6aを積層体1の端面及びそれに隣接する2つの面に、スクリーン印刷法、ローラからの転写法などにより塗布する。そして、導電膜5a、6aは、250℃〜400℃の大気中でバインダ成分を除いた後、800〜900℃で中性または還元性雰囲気で焼き付けによって、下地導体層5a、6aが形成される。
【0035】
その後、下地導体層5a、6aを被覆するように、積層体1の端面と主面との稜線部上に夫々導電性のエポキシ系熱硬化性導電性樹脂層5b、6bを塗布、乾燥、硬化の各工程を順次経て形成する。塗布方法としては、スクリーン印刷法、ディスペンサからの滴下法などが用いられる。このとき、積層体1の一方の端面に導電性樹脂層5b(あるいは6b)を形成した後、積層体1の他方の端面に導電性樹脂層6b(あるいは5b)を形成する方法では、下地導体層5a、6aの形成ばらつきにより、傾斜した面に導電性樹脂層5b、6bを形成することになるため、精度良く形成することができないが、実装面側(あるいは反対側)の一対の導電性樹脂層5b、6bを形成した後、実装面と反対側(あるいは実装面側)の一対の導電性樹脂層5b、6bを形成する方法により、平坦な面に導電性樹脂層5b、6bを形成することになるため、精度良く形成することができる。
【0036】
このようにして、下地導体層5a、6aと導電性樹脂層5b、6bとからなる外部電極5、6が形成される。
【0037】
その後、外部電極5、6は、電解メッキや無電解メッキによって表面メッキ層(図示せず)が形成される。
【0038】
このようにして、本発明の多連型コンデンサ10が得られる。
【0039】
かくして、本発明の多連型コンデンサ10によれば、外部電極5、6は、内部電極3、4に接続するとともに、積層体1の端面と主面とにまたがるように形成された下地導体層5a、6aと、下地導体層5a、6aを被覆するように、積層体1の端面と主面との稜線部上に形成された導電性樹脂層5b、6bとからなる。このため、多連型コンデンサ10を半田13により配線基板11上の配線パターン12に表面実装した状態において、落下などによる衝撃が多連型コンデンサ10に加わっても、クラック38の発生を低減できる。
【0040】
すなわち、落下などによる衝撃により、多連型コンデンサ10にねじり方向の応力が加わる場合が多い。そしてこのとき、積層体1の稜線と外部電極5、6と半田13が接している部分を起点としてクラック38が発生し、積層体1の側面に進行すると考えられるが、導電性樹脂層5b、6bの存在により、積層体1の稜線を被覆する外部電極5、6の厚みrtが大きくなっており、ねじり方向の応力から積層体1を保護することから、クラック38の発生を低減できると考えられる。また、導電性樹脂層が適度に変形するため、ねじり方向の応力が上記起点に伝わることを防ぐことができ、このことによっても、クラック38の発生を低減できると考えられる。
【0041】
また、導電性樹脂層5b、6bは、積層体1の端面と主面との稜線部上のみに形成されているため、多連型コンデンサ10を半田13により配線基板11上の配線パターン12に表面実装した場合、半田13は実装面と反対側の導電性樹脂層5b、6bを乗り越えてはい上がることはなく、積層体1において応力が発生する位置が低くなる。
【0042】
さらに、実装面側(あるいは反対側)の一対の導電性樹脂層5b、6bを形成した後、実装面と反対側(あるいは実装面側)の一対の導電性樹脂層5b、6bを形成する方法を用いることができるため、導電性樹脂層5b、6bを精度良く形成することができ、多連型コンデンサ10の寸法ばらつきを抑制できる。
【0043】
なお、本発明は上記の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲内での種々の変更や改良などは何ら差し支えない。
【0044】
例えば、上記実施の形態ではセラミック電子部品として多連型コンデンサ10を用いて説明したが、本発明は、外部電極5、6が部品本体1の端面からそれに隣接する3面または4面にまたがるように形成された通常の積層セラミックコンデンサにも適用できる。また、外部電極5、6が、部品本体1の端面からそれに隣接する1面にのみまたがるように形成されたセラミック電子部品にも適用できる。さらに、本発明は、他の電子部品や、半導体部品などの他のセラミック電子部品にも適用できる。
【0045】
また、上記実施の形態では、積層体1主面に形成された下地導体層5a、6aの幅naと導電性樹脂層5b、6bの幅nbが略同一であるとともに、下地導体層5a、6a、導電性樹脂層5b、6bが夫々積層体1端面から積層体1の主面に形成された部分との間の距離xa、xbが略同一であるが、na<nb、あるいはxa<xbとなるようにしても良い。このことにより、導電性樹脂層5b、6bと積層体1の接合強度は、下地導体層5a、6aと積層体1の接合強度より大きいことから、積層体1主面に形成された外部電極5、6の剥離を低減できる。また逆に、na>nb、あるいはxa>xbとなるようにしても良い。このことにより、高価な導電性樹脂の材料費を少なくできるとともに、下地導体層5a、6aの表面に凹凸があった場合も、導電性樹脂層5b、6bを精度良く形成できる。ここで、nb/na比は、0.2≦nb/na≦2、好ましくは0.5≦nb/na≦1.25であることが望ましく、xb/xa比は、0.1≦xb/xa≦4、好ましくは0.3≦xb/xa≦2であることが望ましい。すなわち、nb/na比が0.2未満である場合、あるいはxb/xa比が0.1未満である場合、落下などによる衝撃が多連型コンデンサ10に加わった際に、クラック38の発生を低減する効果が十分現れない。一方、nb/naが2より大きい場合、半田13付けにより、隣接するコンデンサユニット(N−N)間の不必要な導通が問題になる。また、xb/xa比が4より大きい場合、半田13付けにより、異なる極の外部電極(5−6)間の不必要な導通が問題になる。
【0046】
本発明者は、上記方法により、図1に示すように、外部電極5、6が下地導体層5a、6aと導電性樹脂層5b、6bとからなる多連型コンデンサ10を作製した。ここで、多連型コンデンサ10の寸法は、2.0mm×1.2mmとした。
【0047】
比較例として、図3に示すように、外部電極35、36が下地導体層35a、35bのみからなる多連型コンデンサ30、及び図4に示すように、外部電極45、46が、積層体41の端面と主面とにまたがるように形成された下地導体層45a、46aと、下地導体層45a、46aの主面部及び積層体41主面にまたがるように形成された導電性樹脂層45b、46bとからなる多連型コンデンサ40を作製した。また、図5に示すように、外部電極55、56が、積層体1の端面と主面とにまたがるように形成された下地導体層55a、56aと、下地導体層55a、56a全体を被覆するように形成された導電性樹脂層55b、56bとからなる多連型コンデンサ50も作製した。なお、図5において、52は誘電体層、53、54は内部電極である。
【0048】
得られた試料について、W方向の寸法の測定及び落下試験を行った。
【0049】
幅方向の寸法については、試料10個をノギスで測定し、最も大きい値とした。
【0050】
落下試験方法は、図2に示すように、試料100個を1.6mm厚のガラスエポキシ基板(配線基板)11上の配線パターン12に、半田13付けにより表面実装した。そして、基板11を樹脂ケースの中にセットし、2mの高さよりコンクリート板上に落下させ、金属顕微鏡によりクラック38の発生率を求めた。
【0051】
測定の結果、図1に示すように、外部電極5、6が、内部電極3、4に接続するとともに、積層体1の端面と主面とにまたがるように形成された下地導体層5a、6aと、下地導体層5a、6aを被覆するように、積層体1の端面と主面との稜線部上に形成された導電性樹脂層5b、6bとからなる本実施例10では、W方向の寸法が1.4mm以下であるとともに、2mの高さよりコンクリート板上に落下させた場合のクラック38の発生率は0%以下となった。
【0052】
これに対し、図3に示すように、外部電極35、36が下地導体層35a、35bのみからなる比較例30では、2mの高さよりコンクリート板上に落下させた場合、クラック38が40%発生した。
【0053】
また、図4に示すように、外部電極45、46が、積層体41の端面と主面とにまたがるように形成された下地導体層45a、46aと、下地導体層45a、46aの主面部及び積層体41主面にまたがるように形成された導電性樹脂層45b、46bとからなる比較例40では、2mの高さよりコンクリート板上に落下させた場合、クラック38が2%発生した。
【0054】
一方、図5に示すように、外部電極55、56が、積層体51の端面と主面とにまたがるように形成された下地導体層55a、56aと、下地導体層55a、56a全体を被覆するように形成された導電性樹脂層55b、56bとからなる比較例50では、導電性樹脂層55b(あるいは56b)を形成した後、導電性樹脂層56b(あるいは55b)を形成する方法により、外部電極55、56を形成したため、W方向の寸法ばらつきが大きくなり、W方向の寸法の最大値が1.47mmより大きくなった。
【0055】
これらの結果から、本発明の多連型コンデンサ10は、外部電極5、6が、内部電極3、4に接続するとともに、積層体1の端面と主面とにまたがるように形成された下地導体層5a、6aと、下地導体層5a、6aを被覆するように、積層体1の端面と主面との稜線部上に形成された導電性樹脂層5b、6bとからなるため、W方向の寸法ばらつきを抑制しつつ、配線基板11に表面実装した際に、落下などによる衝撃が加わっても、クラック38の発生を低減できるとともに、外部電極5、6への半田13の過剰なはい上がりを防止し、不必要な応力によるクラック38を防止できることがわかった。
【0056】
【発明の効果】
本発明のセラミック電子部品によれば、外部電極が、内部導体に接続するとともに、部品本体の端面と主面とにまたがるように形成された下地導体層と、下地導体層を被覆するように、部品本体の端面と主面との稜線部上に形成された導電性樹脂層とからなるため、耐衝撃性に優れている。
【0057】
また、導電性樹脂層は部品本体の端面と主面との稜線部上のみに形成されているため、セラミック電子部品を接合材により配線基板上に表面実装した場合、半田は実装面と反対側の導電性樹脂層を乗り越えてはい上がることはなく、積層体において応力が発生する位置が低くなる。さらに、セラミック電子部品の寸法ばらつきを抑制できる。
【図面の簡単な説明】
【図1】本発明の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【図2】本発明の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。
【図3】従来の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【図4】従来の他の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【図5】比較例の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【符号の説明】
10 多連型コンデンサ(セラミック電子部品)
1 積層体(部品本体)
2 誘電体層
3、4 内部電極(内部導体)
5、6 外部電極
5a、6a 下地導体層
5b、6b 導電性樹脂層
11 配線基板
12 配線パターン
13 半田
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ceramic electronic component, and more particularly to a structure of an external electrode of a ceramic electronic component having a plurality of external electrodes on one end surface of a rectangular parallelepiped component body.
[0002]
[Prior art]
A description will be given of a multiple capacitor as an example of a typical ceramic electronic component.
[0003]
3A and 3B are views showing a conventional multiple capacitor, in which FIG. 3A is an external perspective view, and FIG. 3B is a sectional view taken along line XX.
[0004]
As shown in the figure, the multilayer body 31 (component body) of the multiple capacitor 30 is formed by laminating a plurality of dielectric layers 32.
[0005]
For example, a plurality of first and second internal electrodes (internal conductors) 33 and 34 are formed opposite to each other between the dielectric layers 32 of the multilayer body 31, and the first internal electrode 33 is provided on one end surface of the multilayer body 31. Further, the second internal electrode 34 extends to the other end surface of the multilayer body 31.
[0006]
Further, the plurality of external electrodes 35 and 36 are formed over the end surface of the multilayer body 31 and the main surface in contact with the end surface. Thereby, the end surfaces of the external electrodes 35 and 36 are connected to the first and second internal electrodes 33 and 34. The main surfaces (mounting surfaces) of the external electrodes 35 and 36 are securely mounted on the wiring board.
[0007]
A surface plating layer (not shown) is formed on the surfaces of the external electrodes 35 and 36 as necessary.
[0008]
Such a multiple capacitor 30 is surface-mounted on a wiring pattern on a wiring board with one main surface (mounting surface) down using a bonding material such as solder or a conductive adhesive.
[0009]
Here, in recent years, the demand for the multiple capacitors 30 for portable electronic devices such as portable telephones and portable computers has been increasing.
[0010]
However, in a portable electronic device, when used or carried, an impact due to a drop or the like is applied to the multiple capacitor 30 mounted on the wiring board inside the device, and as shown in FIG. 30 has a problem that a crack 38 is generated.
[0011]
Therefore, as shown in FIG. 4, a rectangular parallelepiped laminated body (component body) 41 in which internal electrodes (internal conductors) 43 and 44 are formed between a plurality of laminated dielectric layers 42 and internal electrodes 43 and 44 are connected. At the same time, the underlying conductor layers 45a and 46a formed so as to extend over the end surface and the main surface of the multilayer body 41, and the conductive layers formed so as to extend over the main surface portions of the underlying conductor layers 45a and 46a and the main surface of the multilayer body 41 Japanese Unexamined Patent Application Publication No. 2003-7567 discloses a multiple capacitor 40 including external electrodes 45 and 46 composed of conductive resin layers 45b and 46b.
[0012]
[Patent Document 1]
JP-A-2003-7567 (page 3-5, FIG. 1-13)
[0013]
[Problems to be solved by the invention]
However, in recent years, according to a study by the inventor, a crack 38 occurs starting from a portion where the ridge of the laminate 41 is in contact with the external electrodes 45 and 46 and the bonding material 13, and the crack 38 progresses to the side surface of the laminate 41. I know that. Therefore, in the multiple capacitor 40 shown in FIG. 4, there is a limit in preventing the occurrence of the crack 38 when the impact due to the drop or the like becomes severe.
[0014]
The present invention has been devised in view of the above problems, and an object of the present invention is to provide a ceramic electronic component having excellent impact resistance.
[0015]
[Means for Solving the Problems]
The present invention provides a rectangular parallelepiped component body made of a ceramic member having an internal conductor formed thereon, and a base conductor layer connected to the internal conductor and formed so as to extend over an end surface and a main surface of the component main body, An external electrode comprising a conductive resin layer formed on a ridge line between the end surface and the main surface of the component body is provided.
[0016]
[Action]
According to the ceramic electronic component of the present invention, a rectangular parallelepiped component body made of a ceramic member having an internal conductor formed thereon, and a base conductor connected to the internal conductor and formed so as to straddle the end surface and the main surface of the component main body And an external electrode formed of a conductive resin layer formed on a ridge line between the end surface and the main surface of the component body so as to cover the base conductor layer. That is, it is formed so that the central portion of the end face underlying conductor layer is exposed. For this reason, cracks can be reduced even if an impact due to dropping or the like is applied to the ceramic electronic component in a state where the ceramic electronic component is surface-mounted on a wiring board with a bonding material such as solder.
[0017]
That is, in many cases, a stress in the torsional direction is applied to the ceramic electronic component due to an impact due to a drop or the like. Then, at this time, cracks are generated from the part where the ridge line of the component body and the external electrode are in contact with the bonding material, and it is considered that the crack proceeds and proceeds to the side surface of the component body. Since the conductive resin layer is formed on the ridge line between the end face and the main surface, the thickness of the external electrode covering the ridge line of the component body is increased, and the component body is protected from torsional stress. It is considered that the occurrence of cracks can be reduced. In addition, since the conductive resin layer is appropriately deformed, it is possible to prevent the stress in the torsional direction from being transmitted to the starting point, and it is considered that this can also reduce the occurrence of cracks.
[0018]
In addition, since the conductive resin layer is formed only on the ridgeline between the end surface and the main surface of the component body, when the ceramic electronic component is surface-mounted on a wiring board with a bonding material, the solder is opposite to the mounting surface. Does not climb over the conductive resin layer, and the position where the stress is generated in the laminate is lowered. Further, dimensional variations of the ceramic electronic component can be suppressed.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a ceramic electronic component of the present invention will be described with reference to the drawings.
[0020]
A description will be given of a multiple capacitor as an example of a typical ceramic electronic component.
[0021]
1A and 1B are views showing a multiple capacitor of the present invention, wherein FIG. 1A is an external perspective view, and FIG. 1B is a longitudinal sectional view. FIG. 2 is a sectional view showing a state in which the multiple capacitor of FIG. 1 is surface-mounted on a wiring board.
[0022]
In the figure, 10 is a multiple capacitor (ceramic electronic component), 1 is a laminated body (component body) made of dielectric ceramic, 2 is a dielectric layer, 3 and 4 are internal electrodes, and 5 and 6 are external electrodes. Reference numeral 11 denotes a wiring board, 12 denotes a wiring pattern, and 13 denotes a solder (joining material).
[0023]
As shown in FIG. 1, the multilayer body 1 of the multiple capacitor 10 is formed by laminating a plurality of dielectric layers 2.
[0024]
The dielectric layer 2 is made of a non-reducing dielectric material containing barium titanate (BaTiO 3 ) as a main component and a dielectric material containing a glass component, and has a shape of 2.0 mm × 1.2 mm or the like. The thickness is set to 1 to 5 μm to increase the capacity. The dielectric layer 2 is stacked in the upward direction in the drawing to form the laminate 1. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed according to the capacitance value.
[0025]
For example, a plurality of internal electrodes 3, 4 are formed facing each other between the dielectric layers 2 of the multilayer body 1, and extend to both end surfaces of the multilayer body 1, respectively. The internal electrodes 3 and 4 are made of, for example, a material mainly containing Ni, and have a thickness of 1 to 2 μm.
[0026]
The external electrodes 5 and 6 are attached to the pair of long side end surfaces of the multilayer body 1 and are connected to the internal electrodes 3 and 4, respectively. Further, a surface plating layer (not shown) is formed on the surfaces of the external electrodes 5 and 6. The surface plating layer can be exemplified by, for example, Ni plating, Sn plating, solder plating, and the like. A feature of the present invention is that the external electrodes 5 and 6 are connected to the internal electrodes 3 and 4 and are connected to the end surfaces of the laminate 1. The base conductor layers 5a and 6a formed so as to straddle the main surface, and the center portions of the end face base conductor layers 5a and 6a formed on the end faces of the laminate 1 so as to cover the base conductor layers 5a and 6a. It consists of conductive resin layers 5b and 6b which are exposed and formed on the ridge line between the end surface and the main surface of the laminate 1.
[0027]
The base conductor layers 5a and 6a are made of a base metal component such as Cu, Ni, or an alloy thereof, and a glass component, and have an end surface on the long side and two main surfaces adjacent to the end surface (one of which is a mounting surface). Formed over the surface.
[0028]
The conductive resin layers 5b and 6b are formed by mixing a thermosetting resin such as an epoxy resin, a phenol resin, and an acrylic resin with a conductive powder such as Cu, Ni, and Ag.
[0029]
Here, the amount yb of each of the conductive resin layers 5b and 6b wrapping around from the main surface of the multilayer body 1 to the end face of the multilayer body 1 is 0.05 ≦ when the dimension in the height direction of the multiple capacitor 10 is T. It is desirable that yb / T ≦ 0.3. That is, when yb / T is less than 0.05, the effect of reducing the occurrence of cracks 38 when impact due to dropping or the like is applied to the multiple capacitor 10 is not sufficiently exhibited. On the other hand, when yb / T is less than 0.3, a pair of conductive resin layers 5b and 6b on the mounting surface side (or the opposite side) are formed, and then a pair of conductive resin layers on the opposite side (or the mounting surface side). According to the method of forming the conductive resin layers 5b and 6b, the conductive resin layers 5b and 6b cannot be formed with high accuracy, and the dimensional variation in the W direction of the multiple capacitor 10 increases.
[0030]
In addition, in order to effectively reduce the occurrence of cracks 38, when the thickness of the external electrodes 5 and 6 covering the ridge line is rt and the radius of curvature of the ridge line portion of the multilayer body 1 is r1, rt / The r1 ratio is desirably 0.25 or more.
[0031]
Hereinafter, a method for manufacturing the multiple capacitor 10 of the present invention will be described. Each code is not distinguished before and after firing.
[0032]
First, a conductive paste is formed on a ceramic green sheet 2 serving as a dielectric layer by screen printing, and conductive films 3 and 4 serving as internal electrodes are formed.
[0033]
Then, after stacking a predetermined number of such ceramic green sheets 2 so that the conductor films 3 and 4 face each other and the conductor films 3 and 4 extend to different end faces, the ceramic green sheets 2 are cut and each capacitor is cut. The unfired laminate 1 including the unit N is fired under a predetermined atmosphere, temperature and time. Thus, the internal electrodes 3 and 4 are exposed on the pair of end surfaces of the multilayer body 1 for each capacitor unit N.
[0034]
Then, in order to electrically connect each capacitor unit N to the outside, the conductor films 5a and 6a serving as the base conductor layers of the external electrodes are formed on the end face of the laminate 1 and two faces adjacent thereto by a screen printing method and a roller. It is applied by a transfer method or the like. Then, the conductive films 5a and 6a are formed by removing the binder components in the air at 250 ° C. to 400 ° C. and then baking at 800 to 900 ° C. in a neutral or reducing atmosphere to form the base conductor layers 5a and 6a. .
[0035]
Thereafter, conductive epoxy-based thermosetting conductive resin layers 5b and 6b are applied on the ridge line between the end surface and the main surface of the laminate 1 so as to cover the base conductor layers 5a and 6a, respectively, and dried and cured. Are sequentially formed. As a coating method, a screen printing method, a dropping method from a dispenser, or the like is used. At this time, in the method of forming the conductive resin layer 5b (or 6b) on one end surface of the laminate 1 and then forming the conductive resin layer 6b (or 5b) on the other end surface of the laminate 1, Since the conductive resin layers 5b and 6b are formed on the inclined surface due to the variation in the formation of the layers 5a and 6a, the conductive resin layers 5b and 6b cannot be formed accurately. After forming the resin layers 5b and 6b, the conductive resin layers 5b and 6b are formed on a flat surface by a method of forming a pair of conductive resin layers 5b and 6b on the opposite side (or the mounting surface side) from the mounting surface. Therefore, it can be formed with high accuracy.
[0036]
In this way, the external electrodes 5, 6 composed of the base conductor layers 5a, 6a and the conductive resin layers 5b, 6b are formed.
[0037]
Thereafter, surface plating layers (not shown) are formed on the external electrodes 5 and 6 by electrolytic plating or electroless plating.
[0038]
Thus, the multiple capacitor 10 of the present invention is obtained.
[0039]
Thus, according to the multiple capacitor 10 of the present invention, the external electrodes 5, 6 are connected to the internal electrodes 3, 4, and are formed so as to extend over the end surface and the main surface of the multilayer body 1. 5a, 6a, and conductive resin layers 5b, 6b formed on the ridges between the end surfaces and the main surface of the laminate 1 so as to cover the base conductor layers 5a, 6a. For this reason, in a state where the multiple capacitor 10 is surface-mounted on the wiring pattern 12 on the wiring board 11 by the solder 13, the occurrence of cracks 38 can be reduced even if an impact due to a drop or the like is applied to the multiple capacitor 10.
[0040]
That is, in many cases, a stress in the torsional direction is applied to the multiple capacitor 10 by an impact due to a drop or the like. At this time, it is considered that a crack 38 occurs starting from a portion where the ridge line of the laminate 1 is in contact with the external electrodes 5 and 6 and the solder 13 and proceeds to the side surface of the laminate 1, but the conductive resin layer 5b, It is thought that the presence of 6b increases the thickness rt of the external electrodes 5 and 6 covering the ridge line of the laminated body 1 and protects the laminated body 1 from the stress in the torsional direction, so that the occurrence of cracks 38 can be reduced. Can be In addition, since the conductive resin layer is appropriately deformed, it is possible to prevent the stress in the torsional direction from being transmitted to the starting point, and it is considered that the generation of the cracks 38 can be reduced also by this.
[0041]
Further, since the conductive resin layers 5 b and 6 b are formed only on the ridge line between the end surface and the main surface of the multilayer body 1, the multiple capacitors 10 are connected to the wiring pattern 12 on the wiring board 11 by the solder 13. In the case of surface mounting, the solder 13 does not climb over the conductive resin layers 5b and 6b on the side opposite to the mounting surface, and the position where the stress occurs in the laminate 1 is reduced.
[0042]
Furthermore, a method of forming a pair of conductive resin layers 5b and 6b on the mounting surface side (or the opposite side), and then forming a pair of conductive resin layers 5b and 6b on the opposite side (or the mounting surface side) of the mounting surface. Therefore, the conductive resin layers 5b and 6b can be formed with high accuracy, and the dimensional variation of the multiple capacitor 10 can be suppressed.
[0043]
It should be noted that the present invention is not limited to the above embodiments, and various changes and improvements may be made without departing from the spirit of the present invention.
[0044]
For example, in the above embodiment, the description has been made using the multiple capacitor 10 as the ceramic electronic component. However, in the present invention, the external electrodes 5 and 6 extend from the end surface of the component main body 1 to three or four surfaces adjacent thereto. The present invention can also be applied to ordinary multilayer ceramic capacitors formed in the above. Further, the present invention can be applied to a ceramic electronic component in which the external electrodes 5 and 6 are formed so as to extend from the end face of the component body 1 to only one face adjacent thereto. Further, the present invention can be applied to other electronic components and other ceramic electronic components such as semiconductor components.
[0045]
Further, in the above embodiment, the width na of the underlying conductor layers 5a and 6a formed on the main surface of the laminate 1 and the width nb of the conductive resin layers 5b and 6b are substantially the same, and the underlying conductor layers 5a and 6a are formed. The distances xa and xb between the end surfaces of the conductive resin layers 5b and 6b and the portions formed on the main surface of the multilayer body 1 are substantially the same, but na <nb or xa <xb. You may make it. As a result, the bonding strength between the conductive resin layers 5b, 6b and the laminate 1 is greater than the bonding strength between the base conductor layers 5a, 6a and the laminate 1, so that the external electrodes 5 formed on the main surface of the laminate 1 are formed. , 6 can be reduced. Conversely, na> nb or xa> xb may be satisfied. As a result, the material cost of the expensive conductive resin can be reduced, and the conductive resin layers 5b, 6b can be formed accurately even when the surfaces of the base conductor layers 5a, 6a have irregularities. Here, the nb / na ratio is desirably 0.2 ≦ nb / na ≦ 2, preferably 0.5 ≦ nb / na ≦ 1.25, and the xb / xa ratio is 0.1 ≦ xb / It is desirable that xa ≦ 4, preferably 0.3 ≦ xb / xa ≦ 2. That is, when the nb / na ratio is less than 0.2 or the xb / xa ratio is less than 0.1, the generation of the crack 38 when an impact due to a drop or the like is applied to the multiple capacitor 10 is reduced. The effect of reducing does not appear sufficiently. On the other hand, if nb / na is larger than 2, unnecessary conduction between adjacent capacitor units (NN) becomes a problem due to soldering. If the xb / xa ratio is larger than 4, unnecessary conduction between the external electrodes (5-6) of different polarities due to the soldering 13 becomes a problem.
[0046]
As shown in FIG. 1, the present inventor produced a multiple capacitor 10 in which the external electrodes 5 and 6 were composed of the underlying conductor layers 5a and 6a and the conductive resin layers 5b and 6b, as shown in FIG. Here, the dimensions of the multiple capacitor 10 were 2.0 mm × 1.2 mm.
[0047]
As a comparative example, as shown in FIG. 3, external capacitors 35 and 36 are formed of multiple capacitors 30 composed of only underlying conductor layers 35a and 35b, and as shown in FIG. And conductive resin layers 45b and 46b formed so as to extend over the main surfaces of the base conductor layers 45a and 46a and the main surface of the laminated body 41. The multiple capacitor 40 composed of In addition, as shown in FIG. 5, the external electrodes 55 and 56 cover the base conductor layers 55a and 56a formed so as to extend over the end surface and the main surface of the multilayer body 1, and cover the entire base conductor layers 55a and 56a. The multiple capacitor 50 including the conductive resin layers 55b and 56b formed as described above was also manufactured. In FIG. 5, 52 is a dielectric layer, and 53 and 54 are internal electrodes.
[0048]
About the obtained sample, the measurement of the dimension of W direction and the drop test were performed.
[0049]
Regarding the dimension in the width direction, ten samples were measured with calipers, and the largest value was obtained.
[0050]
In the drop test method, as shown in FIG. 2, 100 samples were surface-mounted on a wiring pattern 12 on a 1.6 mm thick glass epoxy substrate (wiring board) 11 by soldering. Then, the substrate 11 was set in a resin case, dropped on a concrete plate from a height of 2 m, and the incidence of cracks 38 was determined by a metallographic microscope.
[0051]
As a result of the measurement, as shown in FIG. 1, the external electrodes 5, 6 are connected to the internal electrodes 3, 4, and the underlying conductor layers 5a, 6a formed so as to extend over the end face and the main face of the laminate 1. In the tenth embodiment, the conductive resin layers 5b and 6b formed on the ridge line between the end surface and the main surface of the laminate 1 so as to cover the base conductor layers 5a and 6a. The size was 1.4 mm or less, and the incidence of cracks 38 when dropped on a concrete plate from a height of 2 m was 0% or less.
[0052]
On the other hand, as shown in FIG. 3, in the comparative example 30 in which the external electrodes 35 and 36 consist only of the base conductor layers 35a and 35b, when dropped on a concrete plate from a height of 2 m, cracks 38% occur. did.
[0053]
Also, as shown in FIG. 4, the external conductors 45 and 46 are formed so as to extend over the end surface and the main surface of the multilayer body 41, and the main surfaces of the base conductor layers 45a and 46a and In Comparative Example 40 including the conductive resin layers 45b and 46b formed so as to straddle the main surface of the laminate 41, when dropped on a concrete plate from a height of 2 m, cracks 38% occurred.
[0054]
On the other hand, as shown in FIG. 5, the external electrodes 55 and 56 cover the base conductor layers 55a and 56a formed so as to extend over the end face and the main face of the multilayer body 51, and cover the entire base conductor layers 55a and 56a. In Comparative Example 50 including the conductive resin layers 55b and 56b formed as described above, after the conductive resin layer 55b (or 56b) is formed, the external resin is formed by a method of forming the conductive resin layer 56b (or 55b). Since the electrodes 55 and 56 were formed, the dimensional variation in the W direction became large, and the maximum value of the dimension in the W direction became larger than 1.47 mm.
[0055]
From these results, the multiple capacitor 10 of the present invention is characterized in that the external electrodes 5 and 6 are connected to the internal electrodes 3 and 4 and the base conductor formed so as to extend over the end face and the main face of the multilayer body 1. It is composed of the layers 5a and 6a and the conductive resin layers 5b and 6b formed on the ridge line between the end surface and the main surface of the laminate 1 so as to cover the base conductor layers 5a and 6a. The cracks 38 can be reduced even if an impact due to a drop or the like is applied during surface mounting on the wiring board 11 while suppressing the dimensional variation, and the excessive rise of the solder 13 to the external electrodes 5 and 6 can be prevented. It was found that cracks 38 due to unnecessary stress can be prevented.
[0056]
【The invention's effect】
According to the ceramic electronic component of the present invention, the external electrode is connected to the internal conductor, and the base conductor layer formed so as to straddle the end surface and the main surface of the component body, so as to cover the base conductor layer. Since it is made of the conductive resin layer formed on the ridge line between the end face and the main face of the component body, it has excellent impact resistance.
[0057]
In addition, since the conductive resin layer is formed only on the ridgeline between the end surface and the main surface of the component body, when the ceramic electronic component is surface-mounted on a wiring board with a bonding material, the solder is opposite to the mounting surface. Does not climb over the conductive resin layer, and the position where the stress is generated in the laminate is lowered. Further, dimensional variations of the ceramic electronic component can be suppressed.
[Brief description of the drawings]
FIG. 1 is a view showing a multiple capacitor of the present invention, wherein (a) is an external perspective view and (b) is a cross-sectional view taken along line XX.
FIG. 2 is a cross-sectional view showing a state where the multiple capacitor of the present invention is surface-mounted on a wiring board.
3A and 3B are views showing a conventional multiple capacitor, in which FIG. 3A is an external perspective view, and FIG. 3B is a sectional view taken along line XX.
FIGS. 4A and 4B are diagrams showing another conventional multiple capacitor, in which FIG. 4A is an external perspective view, and FIG. 4B is a sectional view taken along line XX.
5A and 5B are diagrams illustrating a multiple capacitor of a comparative example, in which FIG. 5A is an external perspective view, and FIG. 5B is a cross-sectional view taken along line XX.
[Explanation of symbols]
10 Multiple capacitors (ceramic electronic components)
1 laminated body (part body)
2 Dielectric layers 3, 4 Internal electrode (internal conductor)
5, 6 External electrodes 5a, 6a Base conductor layers 5b, 6b Conductive resin layer 11 Wiring board 12 Wiring pattern 13 Solder

Claims (1)

内部導体が形成されたセラミックス部材からなる直方体の部品本体と、
前記内部導体に接続するとともに、前記部品本体の端面と主面とに跨がるように形成された下地導体層と、前記部品本体の端面と主面との稜線部上に形成された導電性樹脂層とからなる外部電極とを備えてなることを特徴とするセラミック電子部品。
A rectangular parallelepiped component body made of a ceramic member having an internal conductor formed thereon,
A base conductor layer connected to the internal conductor and straddling the end face and the main surface of the component main body; and a conductive layer formed on a ridge line between the end face and the main face of the component main body. A ceramic electronic component, comprising: an external electrode comprising a resin layer.
JP2003089363A 2003-03-27 2003-03-27 Ceramic electronic component Pending JP2004296936A (en)

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