JP2004235377A - Ceramic electronic component - Google Patents

Ceramic electronic component Download PDF

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Publication number
JP2004235377A
JP2004235377A JP2003021211A JP2003021211A JP2004235377A JP 2004235377 A JP2004235377 A JP 2004235377A JP 2003021211 A JP2003021211 A JP 2003021211A JP 2003021211 A JP2003021211 A JP 2003021211A JP 2004235377 A JP2004235377 A JP 2004235377A
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Japan
Prior art keywords
thickness
external electrodes
ceramic electronic
component
electronic component
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JP2003021211A
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Japanese (ja)
Inventor
Masahiro Sadakane
昌宏 貞金
Masatoshi Satou
匡敏 佐藤
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Kyocera Corp
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Kyocera Corp
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Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003021211A priority Critical patent/JP2004235377A/en
Publication of JP2004235377A publication Critical patent/JP2004235377A/en
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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic electronic component whose impact resistivity is excellent. <P>SOLUTION: This ceramic electronic component 10 is constituted of a component main body 1 constituted of ceramics formed with an internal conductor and a plurality of external electrodes 5 and 6 formed across the edge faces and main faces of the component main body 1. In this case, the external electrodes 5 and 6 are formed so that the thickness of the ridges of the edge faces and main faces of the component main body 1 can be made thick. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、セラミック電子部品に関し、特に直方体の部品本体の一方の端面に複数の外部電極を有するセラミック電子部品の外部電極の構造に関するものである。
【0002】
【従来の技術】
代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。
【0003】
図4は、従来の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【0004】
図において、30は多連型コンデンサ、31は積層体であり、32は積層体31を構成する誘電体層、33、34は積層体31内部に形成した内部電極であり、35、36は外部電極である。
【0005】
図に示すように、多連型コンデンサ30の積層体31は、誘電体層32を複数積層して形成されている。
【0006】
また、積層体31の各誘電体層32間に、例えば複数の第1及び第2の内部電極33、34が対向形成され、第1の内部電極33は積層体31の一端面に、第2の内部電極34は積層体31の他端面に延出している。
【0007】
さらに、複数の外部電極35、36は、積層体31の端面及びこの端面に接する主面に跨がって形成されている。これにより、外部電極25、26の端面部分で、第1及び第2の内部電極33、34と接続している。また、外部電極25、26の主面部分(実装面)は、配線基板との実装が確実のものとしている。
【0008】
また、外部電極35、36の表面には、必要に応じて、表面メッキ層(図示せず)が形成されている。
【0009】
このような多連型コンデンサ30は、一方の主面(実装面)を下にして配線基板上の配線パターンに半田や導電性接着剤などの接合材により表面実装される。
【0010】
【特許文献1】
特開2002−57059号公報 (2頁、図1)
【0011】
【発明が解決しようとする課題】
近年、多連型コンデンサ30は、携帯型電話機や携帯型コンピュータなどの携帯型電子機器への需要が増えてきている。
【0012】
しかしながら、携帯型電子機器は、使用時や携帯時において、落下などによる衝撃が、機器内部の配線基板に実装されている多連型コンデンサ30に加わり、図4に示すように、多連型コンデンサ30にクラック38が発生するという問題点があった。
【0013】
本発明は上述の問題点に鑑みて案出されたものであり、その目的は、耐衝撃性に優れたセラミック電子部品を提供することにある。
【0014】
【課題を解決するための手段】
本発明は、内部導体が形成されたセラミックス部材からなる直方体の部品本体と、前記内部導体に接続し、且つ該部品本体の端面と主面とに跨がるように形成された外部電極とを備えてなるセラミック電子部品において、前記外部電極は、前記部品本体の端面と主面との稜線部の導体厚みが、前記部品本体の端面の中央部分に形成された導体厚みに比して厚くなっている。
【0015】
また、外部電極の稜線部の導体厚みをnbとし、前記端面に形成された導体厚みをnaとした時、nb/na値が1.1〜3.0である。
【0016】
【作用】
本発明のセラミック電子部品によれば、外部電極は部品本体の端面と主面とに跨がるように形成され、端面と主面との稜線部分には、導体膜の厚みが厚くなっている。即ち、外部電極の形成領域のうち、部品本体の端面の略中央部分での導体膜よりも、稜線部での導体厚みが厚くなっている。尚、この稜線部を外部電極の凸部といい、導体膜が薄い領域を凸部に対して平坦部という。
【0017】
そして、外部電極の凸部が、部品本体の端面と主面との稜線部に跨がって凸部が形成されているため、セラミック電子部品をはんだなどの接合材により配線基板上に表面実装した状態で、落下などによる衝撃がセラミック電子部品に加わっても、クラックの発生を低減できる。
【0018】
すなわち、落下などによる衝撃により、セラミック電子部品にねじり方向の応力が加わる場合が多い。そしてこのとき、部品本体の稜線と外部電極と接合材が接している部分を起点としてクラックが発生し、部品本体の側面に進行すると考えられるが、凸部の存在により、部品本体の稜線を被覆する外部電極の厚みが大きくなっており、ねじり方向の応力から部品本体を保護することから、クラックの発生を低減できると考えられる。
【0019】
また、部品本体の端面の略中央に外部電極の平坦部が形成されているため、部品本体の稜線を被覆する外部電極の厚みが大きくなった場合も、セラミック電子部品の寸法を大きくせずに済むことから、小型大容量化を実現できる。また、外部電極全体の厚みを大きくせずに済むため、有機バインダ樹脂の除去が容易に行われ、ブリスタを発生させることがなく、その結果、例えば静電容量などの電気的特性の低下を抑制できる。さらに、セラミック電子部品を接合材により配線基板上に表面実装した場合、接合材は平坦部の高さまでしかはい上がらないため、部品本体において応力が発生する位置が低くなる。
【0020】
【発明の実施の形態】
以下、本発明のセラミック電子部品を図面に基づいて説明する。
【0021】
代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。
【0022】
図1は、本発明の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)は縦断面図である。図2は、図1の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。
【0023】
図において、10は多連型コンデンサ(セラミック電子部品)、1は誘電体セラミックから積層体(部品本体)、2は誘電体層、3、4は内部電極、5、6は外部電極である。また、11は配線基板、12は配線パターン、13は半田(接合材)である。
【0024】
図1に示すように、多連型コンデンサ10の積層体1は、誘電体層2を複数積層して形成されている。
【0025】
誘電体層2は、チタン酸バリウム(BaTiO)を主成分とする非還元性誘電体材料、及びガラス成分を含む誘電体材料からなり、その形状は、2.0mm×1.2mmなどであり、その厚みは高容量化のために1〜5μmとしている。この誘電体層2が図上、上方向に積層して積層体1が構成される。なお、誘電体層2の形状、厚み、積層数は容量値によって任意に変更することができる。
【0026】
積層体1の各誘電体層2間に、例えば複数の内部電極3、4が対向形成され、それぞれ積層体1の両端面に延出している。内部電極3、4は、例えばNiを主成分とする材料から構成され、その厚みは1〜2μmとしている。
【0027】
外部電極5、6は、積層体1の一対の長辺側端面に被着形成され、且つ内部電極3、4にそれぞれ接続されている。外部電極5、6は、例えばCu、Ni、あるいはこれらの合金などの卑金属成分及びガラス成分からなり、長辺側の端面及びそれに隣接する2つの主面(一方は実装面となる)の3面にわたって形成される。さらに、外部電極5、6の表面には、表面メッキ層(図示せず)が形成されている。表面メッキ層は、例えばNiメッキ、Snメッキ、半田メッキなどが例示できる。
【0028】
本発明の特徴的なことは、外部電極5、6の積層体1の端面と主面との稜線部の導体厚みが、積層体1の端面の中央部分に形成された導体厚みに比して厚くなっている。即ち、外部電極5、6は、積層体1の端面の略中央に形成された平坦部5a、6aと、平坦部5a、6aに隣接するとともに、主面にまたがる凸部5b、6bとからなることである。
【0029】
ここで、平坦部5a、6aの厚みnaは、最大値と最小値の比率が1.5以下、好ましくは1.2以下であることが望ましい。また、凸部5b、6bの形状は、ドーム状であることが望ましい。
【0030】
以下、本発明の多連型コンデンサ10の製造方法について説明する。なお、各符号は焼成の前後で区別しないものとする。
【0031】
まず、誘電体層となるセラミックグリーンシート2上に、導電ペーストをスクリーン印刷で形成し、内部電極となる導体膜3、4を形成する。
【0032】
そして、このようなセラミックグリーンシート2を、導体膜3、4が互いに対向し、且つ導体膜3、4が互いに異なる端面に延出するように所定の積層枚数重ねた後、切断して各コンデンサユニットNを含む未焼成状態の積層体1とし、所定の雰囲気、温度、時間を加えて焼成する。これにより、積層体1の一対の端面には、各コンデンサユニットN毎に内部電極3、4が露出している。
【0033】
その後、各コンデンサユニットNを外部と電気的に接続するために、外部電極となる導体膜5、6を積層体1の端面及びそれに隣接する2つの面に、スクリーン印刷法、ローラからの転写法などにより塗布する。
【0034】
このとき、導体膜5、6は、積層体1の端面の略中央に平坦部5a、6aが形成されるとともに、エッジ効果により、平坦部5a、6aに隣接するとともに、主面にまたがる凸部5b、6bが形成される。
【0035】
そして、導電膜5、6は、250℃〜400℃の大気中でバインダ成分を除いた後、800〜900℃で中性または還元性雰囲気で焼き付けによって、外部電極5、6が形成される。
【0036】
その後、外部電極5、6は、電解メッキや無電解メッキによって表面メッキ層(図示せず)が形成される。このとき、外部電極5、6の凸部5b、6bは、平坦部5a、6aに比べてメッキがかかりにくいため、平坦部5a、6aの厚みnaと凸部5b、6bの厚みnbの差をさらに累積させることができる。
【0037】
このようにして、本発明の多連型コンデンサ10が得られる。
【0038】
かくして、本発明の多連型コンデンサ10によれば、外部電極5、6は、積層体1の端面の略中央に形成された平坦部5a、6aと、平坦部5a、6aの周辺に形成されるとともに、端面と主面との稜線部にまたがる凸部5b、6bとからなる。このため、多連型コンデンサ10を半田13により配線基板11上の配線パターン12に表面実装した状態において、落下などによる衝撃が多連型コンデンサ10に加わっても、クラック38の発生を低減できる。
【0039】
すなわち、落下などによる衝撃により、多連型コンデンサ10にねじり方向の応力が加わる場合が多い。そしてこのとき、積層体1の稜線と外部電極5、6と半田13が接している部分を起点としてクラック38が発生し、積層体1の側面に進行すると考えられるが、凸部5b、6bの存在により、積層体1の稜線を被覆する外部電極5、6の厚みrtが大きくなっており、ねじり方向の応力から積層体1を保護することから、クラック38の発生を低減できると考えられる。
【0040】
また、積層体1の端面の略中央に外部電極5、6の平坦部5a、6aが形成されているため、積層体1の稜線を被覆する外部電極5、6の厚みrtが大きくなった場合も、多連型コンデンサ10の幅方向(W方向)の寸法を大きくせずに済むことから、小型大容量化を実現できる。また、外部電極5、6全体の厚みを大きくせずに済むため、有機バインダ樹脂の除去が容易に行われ、ブリスタを発生させることがなく、その結果、例えば静電容量などの電気的特性の低下を抑制できる。さらに、多連型コンデンサ10を半田13により配線基板11上の配線パターン12に表面実装した場合、半田13は平坦部の高さまでしかはい上がらないため、積層体1において応力が発生する位置が低くなる。
【0041】
ここで、図1(b)に示すように、クラック38の発生を効果的に低減するためには、積層体1の稜線の部分の丸みの曲率半径をr1とした場合、rt/r1比は0.25以上であることが望ましい。
【0042】
また、平坦部5a、6aの高さ方向の寸法maと積層体1の高さ方向の寸法Tの比ma/Tは0.2〜0.8、好ましくは0.3〜0.5の範囲にあることが望ましい。すなわち、ma/T比が0.2未満である場合、上記小型大容量化などの効果が十分に現れない。一方、ma/T比が0.8を超える場合、落下などによる衝撃によるクラック38の発生を低減する効果が十分に現れない。
【0043】
また、平坦部5a、6aの厚みnaと凸部5b、6bの厚みnb(平坦部5a、6aと比較するために積層体1の端面側での厚みを用いた)との比nb/naは、1.1〜3.0、好ましくは、1.5〜2.4の範囲にあることが望ましい。すなわち、nb/na比が1.1未満の場合、上記小型大容量化などの効果を現しつつ、落下などによる衝撃によるクラック38の発生を低減する効果が十分に現れない。一方、nb/na値比が3.0を超える場合、精度良く平坦部5a、6a及び凸部5b、6bを形成することが困難となり、外部からの衝撃により破損し凸部5b、6bに欠けが発生してしまう。このため、実際の使用ができないものとなる。
【0044】
なお、本発明は上記の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲内での種々の変更や改良などは何ら差し支えない。
【0045】
例えば、上記実施の形態ではセラミック電子部品として多連型コンデンサを用いて説明したが、本発明は、外部電極が部品本体の端面からそれに隣接する3面または4面にまたがるように形成された通常の積層セラミックコンデンサにも適用できる。また、外部電極が、部品本体の端面からそれに隣接する1面にのみまたがるように形成されたセラミック電子部品にも適用できる。さらに、本発明は、他の電子部品や、半導体部品などの他のセラミック電子部品にも適用できる。
【0046】
図3は、本発明の多連型コンデンサ10の他の実施形態を示す外観斜視図である。図のように、外部電極5、6の平坦部5a、6aは、図面中左右方向の略中央のみに形成されるようにしても良い。このことにより、凸部5b、6bが外部からの衝撃により破損しにくくなる。
【0047】
また、外部電極5、6の平坦部5a、6a及び凸部5b、6bを形成する方法として、スクリーン製版のメッシュの開き目を平坦部5a、6aとなる部分に比べて、凸部5b、6bとなる部分の方が大きくなるようにしても良い。さらに、外部電極5、6となる導電性ペーストの所定形状に塗布、焼き付けを夫々2回以上行っても良い。即ち、平坦部5a、6aの厚みnaと凸部5b、6bの厚みnbの差が累積されて、さらに大きくできる。またこのとき、2回目以降の導電性ペーストの塗布は、1回目の塗布とは異なるスクリーン製版を用いて、凸部5b、6bとなる部分のみに行うようにしても良い。このことによっても、平坦部5a、6aの厚みnaと凸部5b、6bの厚みnbの差をさらに大きくできる。
【0048】
【実施例】
本発明者は、上記方法により、外部電極5、6が平坦部5a、6a及び凸部5b、6bからなる多連型コンデンサ10を作製した。ここで、多連型コンデンサ10の寸法は、2.0mm×1.2mmとした。また、導電性ペーストの固形分、粘度などの性状、スクリーン製版のメッシュの開き目を調節することにより、rt/r1≧0.25の範囲に入るようにしつつ、ma/T比、nb/na比を変化させた。(試料番号2〜6、8〜11)さらに、平坦部5a、6aの厚みnaは10〜35μm、凸部5b、6bの厚みnbは、20〜60μmの範囲に入り、且つna<nbとなるようにした。そして、これらの厚みna、nbは、多連型コンデンサ10の破断面のSEM像から確認した。
【0049】
比較例として、外部電極5、6に凸部5b、6bを形成しない(外部電極5、6全体の厚みが10〜35μmの範囲にある)多連型コンデンサ30(試料番号7)や、外部電極5、6に凹部5a、6aを形成しない(外部電極5、6全体の厚みが20〜60μmの範囲にある)多連型コンデンサ30(試料番号1)も作製した。
【0050】
得られた試料について、W方向の寸法の測定及び落下試験を行った。
【0051】
幅方向の寸法については、試料10個をノギスで測定し、最も大きい値とした。
【0052】
落下試験方法は、図2に示すように、試料100個を1.6mm厚のガラスエポキシ基板(配線基板)11上の配線パターン12に、半田13付けにより表面実装した。そして、基板11を樹脂ケースの中にセットし、2mの高さよりコンクリート板上に落下させ、金属顕微鏡によりクラック38の発生率を求めた。
【0053】
評価基準は、W方向の寸法が1.47mm以下であるとともに、2mの高さより落下させてもクラック38の発生率が5%以下である場合を良品として丸印とした。また良品の内、W方向の寸法が1.4mm以下であるとともに、クラック38の発生率が0%である場合を二重丸印とした。一方、W方向の寸法が1.47mmを超える場合や、クラック38の発生率が5%を超える場合を不良品としてバツ印とした。
【0054】
結果を表1に示す。
【0055】
【表1】

Figure 2004235377
【0056】
表に示すように、外部電極5、6が平坦部5a、6a及び凸部5b、6bからなる本実施例(試料番号2〜6、8〜11)は、rt/r1≧0.25の範囲に入るようにした場合も、W方向の寸法が1.47mm以下であるとともに、2mの高さよりコンクリート板上に落下させた場合のクラック38の発生率は5%以下となった。特に、ma/T比が0.3以上であり、且つnb/na比が1.5以上である場合(試料番号3〜5、9〜11)は、W方向の寸法が1.4mm以下であるとともに、クラック38の発生率は0%以下となった。
【0057】
これに対し、外部電極5、6に凸部5b、6bを形成しない比較例(試料番号7)は、rt/r1<0.25となり、また2mの高さよりコンクリート板上に落下させた場合、クラック38が40%発生した。
【0058】
一方、外部電極5、6に凹部5a、6aを形成しない比較例(試料番号1)は、rt/r1≧0.25の範囲に入るようにした場合、W方向の寸法が1.47mmより大きくなった。
【0059】
これらの結果から、本発明の多連型コンデンサ10は、外部電極5、6は、部品本体1の端面の略中央に形成された平坦部5a、6aと、平坦部5a、6aに隣接するとともに、主面にまたがる凸部5b、6bとからなるため、W方向の寸法を大きくせずに、実装状態において、落下などによる衝撃が加わっても、クラック38の発生を低減できることがわかった。
【0060】
【発明の効果】
本発明のセラミック電子部品によれは、部品本体の端面と主面との稜線部分の外部電極の厚みを厚くしたため、耐衝撃性に優れている。
【0061】
また、部品本体の端面の略中央に外部電極の平坦部が形成されており、外部電極全体の厚みを大きくせずに済むため、小型大容量化、有機バインダ樹脂の除去が容易に行われる、接合材のはい上がる高さを低くするなどの効果がある。
【図面の簡単な説明】
【図1】本発明の多連型コンデンサを示す図であり、(a)は外観斜視図、(b)はX−X線断面図である。
【図2】図1の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。
【図3】本発明の多連型コンデンサの他の実施形態を示す外観斜視図である。
【図4】従来の多連型コンデンサを示す図であり、(a)は一部透視状態の外観斜視図、(b)はX−X線断面図である。
【符号の説明】
10 多連型コンデンサ(セラミック電子部品)
1 積層体(部品本体)
2 誘電体層
3、4 内部電極
5、6 外部電極
5a、6a 平坦部
5b、6b 凸部
11 配線基板
12 配線パターン
13 半田[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ceramic electronic component, and more particularly to a structure of an external electrode of a ceramic electronic component having a plurality of external electrodes on one end surface of a rectangular parallelepiped component body.
[0002]
[Prior art]
A description will be given of a multiple capacitor as an example of a typical ceramic electronic component.
[0003]
4A and 4B are views showing a conventional multiple capacitor, in which FIG. 4A is an external perspective view, and FIG. 4B is a sectional view taken along line XX.
[0004]
In the figure, 30 is a multiple capacitor, 31 is a laminated body, 32 is a dielectric layer constituting the laminated body 31, 33 and 34 are internal electrodes formed inside the laminated body 31, and 35 and 36 are external electrodes. Electrodes.
[0005]
As shown in the figure, the multilayer body 31 of the multiple capacitor 30 is formed by stacking a plurality of dielectric layers 32.
[0006]
Further, for example, a plurality of first and second internal electrodes 33 and 34 are formed between the dielectric layers 32 of the multilayer body 31 so as to face each other. The internal electrode 34 extends to the other end surface of the multilayer body 31.
[0007]
Further, the plurality of external electrodes 35 and 36 are formed so as to straddle the end surface of the multilayer body 31 and the main surface in contact with the end surface. Thereby, the end faces of the external electrodes 25 and 26 are connected to the first and second internal electrodes 33 and 34. In addition, the main surfaces (mounting surfaces) of the external electrodes 25 and 26 are securely mounted on the wiring board.
[0008]
A surface plating layer (not shown) is formed on the surfaces of the external electrodes 35 and 36 as necessary.
[0009]
Such a multiple capacitor 30 is surface-mounted on a wiring pattern on a wiring board with one main surface (mounting surface) down using a bonding material such as solder or a conductive adhesive.
[0010]
[Patent Document 1]
JP-A-2002-57059 (page 2, FIG. 1)
[0011]
[Problems to be solved by the invention]
In recent years, the demand for the multiple capacitors 30 for portable electronic devices such as portable telephones and portable computers has been increasing.
[0012]
However, in a portable electronic device, when used or carried, an impact due to a drop or the like is applied to a multiple capacitor 30 mounted on a wiring board inside the device, and as shown in FIG. 30 has a problem that a crack 38 is generated.
[0013]
The present invention has been devised in view of the above problems, and an object of the present invention is to provide a ceramic electronic component having excellent impact resistance.
[0014]
[Means for Solving the Problems]
The present invention provides a rectangular parallelepiped component body made of a ceramic member having an internal conductor formed thereon, and an external electrode connected to the internal conductor and formed so as to straddle an end surface and a main surface of the component body. In the ceramic electronic component provided, the external electrode has a conductor thickness at a ridge portion between an end surface and a main surface of the component body that is thicker than a conductor thickness formed at a central portion of the end surface of the component body. ing.
[0015]
When the conductor thickness at the ridge of the external electrode is nb and the conductor thickness formed on the end face is na, the nb / na value is 1.1 to 3.0.
[0016]
[Action]
According to the ceramic electronic component of the present invention, the external electrode is formed so as to straddle the end surface and the main surface of the component main body, and the ridge portion between the end surface and the main surface has a thicker conductor film. . In other words, the conductor thickness at the ridge portion is larger than the conductor film at the substantially central portion of the end surface of the component body in the external electrode formation region. The ridge line portion is called a convex portion of the external electrode, and a region where the conductive film is thin is called a flat portion with respect to the convex portion.
[0017]
Since the projection of the external electrode is formed so as to extend over the ridgeline between the end surface and the main surface of the component body, the ceramic electronic component is surface-mounted on a wiring board with a bonding material such as solder. In this state, even if an impact due to a drop or the like is applied to the ceramic electronic component, the occurrence of cracks can be reduced.
[0018]
That is, in many cases, a stress in the torsional direction is applied to the ceramic electronic component due to an impact due to a drop or the like. At this time, cracks are thought to occur starting from the part where the ridgeline of the component body and the external electrode are in contact with the bonding material, and proceed to the side surfaces of the component body.However, the presence of the projection covers the ridgeline of the component body. Since the thickness of the external electrode is increased and the component body is protected from the stress in the torsional direction, it is considered that the occurrence of cracks can be reduced.
[0019]
In addition, since the flat portion of the external electrode is formed substantially at the center of the end surface of the component body, even when the thickness of the external electrode covering the ridge line of the component body is increased, the size of the ceramic electronic component is not increased. As a result, it is possible to realize a small size and a large capacity. In addition, since the thickness of the entire external electrode does not need to be increased, the organic binder resin can be easily removed, and blisters are not generated. As a result, a decrease in electrical characteristics such as capacitance is suppressed. it can. Furthermore, when a ceramic electronic component is surface-mounted on a wiring board with a bonding material, the bonding material only goes up to the height of the flat portion, so that the position where stress is generated in the component body is reduced.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a ceramic electronic component of the present invention will be described with reference to the drawings.
[0021]
A description will be given of a multiple capacitor as an example of a typical ceramic electronic component.
[0022]
1A and 1B are views showing a multiple capacitor of the present invention, wherein FIG. 1A is an external perspective view, and FIG. 1B is a longitudinal sectional view. FIG. 2 is a sectional view showing a state in which the multiple capacitor of FIG. 1 is surface-mounted on a wiring board.
[0023]
In the figure, 10 is a multiple capacitor (ceramic electronic component), 1 is a laminated body (component body) made of dielectric ceramic, 2 is a dielectric layer, 3 and 4 are internal electrodes, and 5 and 6 are external electrodes. Reference numeral 11 denotes a wiring board, 12 denotes a wiring pattern, and 13 denotes a solder (joining material).
[0024]
As shown in FIG. 1, the multilayer body 1 of the multiple capacitor 10 is formed by laminating a plurality of dielectric layers 2.
[0025]
The dielectric layer 2 is made of a non-reducing dielectric material containing barium titanate (BaTiO 3 ) as a main component and a dielectric material containing a glass component, and has a shape of 2.0 mm × 1.2 mm or the like. The thickness is set to 1 to 5 μm to increase the capacity. The dielectric layer 2 is stacked in the upward direction in the drawing to form the laminate 1. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed according to the capacitance value.
[0026]
For example, a plurality of internal electrodes 3, 4 are formed facing each other between the dielectric layers 2 of the multilayer body 1, and extend to both end surfaces of the multilayer body 1, respectively. The internal electrodes 3 and 4 are made of, for example, a material mainly containing Ni, and have a thickness of 1 to 2 μm.
[0027]
The external electrodes 5 and 6 are attached to the pair of long side end surfaces of the multilayer body 1 and are connected to the internal electrodes 3 and 4, respectively. The external electrodes 5 and 6 are made of a base metal component such as Cu, Ni, or an alloy thereof, and a glass component, and have three surfaces including an end surface on the long side and two main surfaces adjacent to the end surface (one is a mounting surface). Formed over Further, a surface plating layer (not shown) is formed on the surfaces of the external electrodes 5 and 6. Examples of the surface plating layer include Ni plating, Sn plating, and solder plating.
[0028]
A feature of the present invention is that the conductor thickness of the ridge portion between the end surface and the main surface of the laminate 1 of the external electrodes 5 and 6 is smaller than the conductor thickness formed at the center of the end surface of the laminate 1. It is getting thicker. That is, the external electrodes 5 and 6 include flat portions 5a and 6a formed substantially at the center of the end face of the multilayer body 1 and convex portions 5b and 6b adjacent to the flat portions 5a and 6a and extending over the main surface. That is.
[0029]
Here, as for the thickness na of the flat portions 5a and 6a, the ratio of the maximum value to the minimum value is preferably 1.5 or less, more preferably 1.2 or less. Also, it is desirable that the shapes of the convex portions 5b and 6b are dome shapes.
[0030]
Hereinafter, a method for manufacturing the multiple capacitor 10 of the present invention will be described. Each code is not distinguished before and after firing.
[0031]
First, a conductive paste is formed on a ceramic green sheet 2 serving as a dielectric layer by screen printing, and conductive films 3 and 4 serving as internal electrodes are formed.
[0032]
Then, after stacking a predetermined number of such ceramic green sheets 2 so that the conductor films 3 and 4 face each other and the conductor films 3 and 4 extend to different end faces, the ceramic green sheets 2 are cut and each capacitor is cut. The unfired laminate 1 including the unit N is fired under a predetermined atmosphere, temperature and time. Thus, the internal electrodes 3 and 4 are exposed on the pair of end surfaces of the multilayer body 1 for each capacitor unit N.
[0033]
Thereafter, in order to electrically connect each capacitor unit N to the outside, the conductor films 5 and 6 serving as external electrodes are applied to the end face of the laminate 1 and two adjacent faces by a screen printing method and a transfer method from a roller. It is applied by, for example.
[0034]
At this time, the conductor films 5 and 6 have flat portions 5a and 6a formed substantially at the center of the end surface of the multilayer body 1 and have a convex portion which is adjacent to the flat portions 5a and 6a by the edge effect and straddles the main surface. 5b and 6b are formed.
[0035]
After removing the binder component from the conductive films 5 and 6 in the air at 250 ° C. to 400 ° C., the external electrodes 5 and 6 are formed by baking at 800 to 900 ° C. in a neutral or reducing atmosphere.
[0036]
Thereafter, surface plating layers (not shown) are formed on the external electrodes 5 and 6 by electrolytic plating or electroless plating. At this time, since the protrusions 5b, 6b of the external electrodes 5, 6 are less likely to be plated than the flat portions 5a, 6a, the difference between the thickness na of the flat portions 5a, 6a and the thickness nb of the protrusions 5b, 6b is determined. It can be further accumulated.
[0037]
Thus, the multiple capacitor 10 of the present invention is obtained.
[0038]
Thus, according to the multiple capacitor 10 of the present invention, the external electrodes 5, 6 are formed at the flat portions 5 a, 6 a formed substantially at the center of the end face of the multilayer body 1, and around the flat portions 5 a, 6 a. And convex portions 5b and 6b extending over the ridge line between the end surface and the main surface. For this reason, in a state where the multiple capacitor 10 is surface-mounted on the wiring pattern 12 on the wiring board 11 by the solder 13, the occurrence of cracks 38 can be reduced even if an impact due to a drop or the like is applied to the multiple capacitor 10.
[0039]
That is, in many cases, a stress in the torsional direction is applied to the multiple capacitor 10 by an impact due to a drop or the like. At this time, it is considered that a crack 38 is generated starting from a portion where the ridgeline of the laminate 1 is in contact with the external electrodes 5 and 6 and the solder 13 and proceeds to the side surface of the laminate 1, but the protrusions 5b and 6b It is considered that the presence thereof increases the thickness rt of the external electrodes 5 and 6 covering the ridge line of the multilayer body 1 and protects the multilayer body 1 from the stress in the torsional direction, so that the occurrence of cracks 38 can be reduced.
[0040]
In addition, since the flat portions 5a and 6a of the external electrodes 5 and 6 are formed substantially at the center of the end surface of the multilayer body 1, the thickness rt of the external electrodes 5 and 6 covering the ridge line of the multilayer body 1 increases. However, the size of the multiple capacitor 10 in the width direction (W direction) does not need to be increased, so that a large-sized capacitor can be realized. In addition, since it is not necessary to increase the thickness of the external electrodes 5 and 6 as a whole, the organic binder resin can be easily removed, and no blister is generated. As a result, for example, electric characteristics such as capacitance can be reduced. Reduction can be suppressed. Furthermore, when the multiple capacitor 10 is surface-mounted on the wiring pattern 12 on the wiring board 11 by the solder 13, the solder 13 rises only up to the height of the flat portion, so that the position where the stress occurs in the laminate 1 is low. Become.
[0041]
Here, as shown in FIG. 1B, in order to effectively reduce the occurrence of cracks 38, when the radius of curvature of the ridge line portion of the laminate 1 is r1, the rt / r1 ratio is Desirably, it is 0.25 or more.
[0042]
Further, the ratio ma / T of the dimension ma in the height direction of the flat portions 5a and 6a to the dimension T in the height direction of the laminate 1 is in the range of 0.2 to 0.8, preferably 0.3 to 0.5. Is desirable. That is, when the ma / T ratio is less than 0.2, the above-mentioned effects such as the reduction in size and the capacity are not sufficiently exhibited. On the other hand, when the ma / T ratio exceeds 0.8, the effect of reducing the occurrence of cracks 38 due to impact due to dropping or the like does not sufficiently appear.
[0043]
The ratio nb / na between the thickness na of the flat portions 5a and 6a and the thickness nb of the convex portions 5b and 6b (the thickness at the end face side of the laminate 1 is used for comparison with the flat portions 5a and 6a) is , 1.1-3.0, preferably 1.5-2.4. That is, when the nb / na ratio is less than 1.1, the effect of reducing the occurrence of cracks 38 due to an impact due to a drop or the like while sufficiently exhibiting the effects of the above-described small size and large capacity is not sufficiently exhibited. On the other hand, when the nb / na value ratio exceeds 3.0, it becomes difficult to accurately form the flat portions 5a and 6a and the convex portions 5b and 6b, and the flat portions 5a and 6a are damaged by an external impact, and the convex portions 5b and 6b are chipped. Will occur. For this reason, it cannot be actually used.
[0044]
It should be noted that the present invention is not limited to the above embodiments, and various changes and improvements may be made without departing from the spirit of the present invention.
[0045]
For example, in the above embodiments, a multiple capacitor was used as the ceramic electronic component. However, the present invention is applied to a case where the external electrode is formed so as to extend from the end face of the component body to three or four faces adjacent thereto. It can also be applied to the multilayer ceramic capacitor. Further, the present invention can be applied to a ceramic electronic component in which an external electrode is formed so as to extend from an end surface of the component main body to only one surface adjacent thereto. Further, the present invention can be applied to other electronic components and other ceramic electronic components such as semiconductor components.
[0046]
FIG. 3 is an external perspective view showing another embodiment of the multiple capacitor 10 of the present invention. As shown, the flat portions 5a and 6a of the external electrodes 5 and 6 may be formed only at substantially the center in the horizontal direction in the drawing. This makes it difficult for the protrusions 5b and 6b to be damaged by an external impact.
[0047]
Further, as a method of forming the flat portions 5a, 6a and the convex portions 5b, 6b of the external electrodes 5, 6, the mesh of the screen plate is made to have an opening larger than that of the flat portions 5a, 6a. May be made larger. Further, the application and baking of the conductive paste to be the external electrodes 5 and 6 in a predetermined shape may be performed two or more times. That is, the difference between the thickness na of the flat portions 5a and 6a and the thickness nb of the convex portions 5b and 6b is accumulated and can be further increased. At this time, the second and subsequent application of the conductive paste may be performed only on the portions that become the protruding portions 5b and 6b by using a screen plate different from that of the first application. This also makes it possible to further increase the difference between the thickness na of the flat portions 5a and 6a and the thickness nb of the convex portions 5b and 6b.
[0048]
【Example】
The present inventor produced a multiple capacitor 10 in which the external electrodes 5 and 6 had flat portions 5a and 6a and convex portions 5b and 6b by the above method. Here, the dimensions of the multiple capacitor 10 were 2.0 mm × 1.2 mm. Further, by adjusting the properties of the conductive paste such as solid content and viscosity, and the size of the mesh of the screen plate, the ma / T ratio and the nb / na ratio are adjusted so as to fall within the range of rt / r1 ≧ 0.25. The ratio was varied. (Sample Nos. 2 to 6, 8 to 11) Further, the thickness na of the flat portions 5a and 6a is in the range of 10 to 35 μm, and the thickness nb of the convex portions 5b and 6b is in the range of 20 to 60 μm, and na <nb. I did it. And these thicknesses na and nb were confirmed from the SEM image of the fracture surface of the multiple capacitor 10.
[0049]
As comparative examples, the multiple capacitors 30 (sample No. 7) in which the projections 5b and 6b are not formed on the external electrodes 5 and 6 (the total thickness of the external electrodes 5 and 6 is in the range of 10 to 35 μm), and the external electrodes A multiple capacitor 30 (sample No. 1) in which the concave portions 5a and 6a are not formed in 5 and 6 (the total thickness of the external electrodes 5 and 6 is in the range of 20 to 60 μm) was also manufactured.
[0050]
About the obtained sample, the measurement of the dimension of W direction and the drop test were performed.
[0051]
Regarding the dimension in the width direction, ten samples were measured with calipers, and the largest value was obtained.
[0052]
In the drop test method, as shown in FIG. 2, 100 samples were surface-mounted on a wiring pattern 12 on a 1.6 mm thick glass epoxy substrate (wiring board) 11 by soldering. Then, the substrate 11 was set in a resin case, dropped on a concrete plate from a height of 2 m, and the incidence of cracks 38 was determined by a metallographic microscope.
[0053]
The evaluation criteria are circles as non-defective products in which the dimension in the W direction is 1.47 mm or less and the rate of occurrence of cracks 38 is 5% or less even when dropped from a height of 2 m. Further, among the non-defective products, the case where the dimension in the W direction is 1.4 mm or less and the occurrence rate of the crack 38 is 0% is indicated by a double circle. On the other hand, a case where the dimension in the W direction exceeds 1.47 mm or a case where the occurrence rate of the crack 38 exceeds 5% is marked with a cross as a defective product.
[0054]
Table 1 shows the results.
[0055]
[Table 1]
Figure 2004235377
[0056]
As shown in the table, in this embodiment (sample numbers 2 to 6 and 8 to 11) in which the external electrodes 5 and 6 include the flat portions 5a and 6a and the convex portions 5b and 6b, the range of rt / r1 ≧ 0.25 is satisfied. Also, when it was made to enter, the dimension in the W direction was 1.47 mm or less, and the incidence of cracks 38 when dropped on a concrete plate from a height of 2 m was 5% or less. In particular, when the ma / T ratio is 0.3 or more and the nb / na ratio is 1.5 or more (sample numbers 3 to 5 and 9 to 11), the dimension in the W direction is 1.4 mm or less. At the same time, the incidence of cracks 38 became 0% or less.
[0057]
On the other hand, in the comparative example (sample No. 7) in which the projections 5b and 6b are not formed on the external electrodes 5 and 6, rt / r1 <0.25, and when the sample is dropped on a concrete plate from a height of 2 m, 40% of cracks 38 occurred.
[0058]
On the other hand, in the comparative example (sample No. 1) in which the concave portions 5a and 6a are not formed in the external electrodes 5 and 6, the dimension in the W direction is larger than 1.47 mm when rt / r1 ≧ 0.25. became.
[0059]
From these results, in the multiple capacitor 10 of the present invention, the external electrodes 5, 6 are adjacent to the flat portions 5 a, 6 a formed substantially at the center of the end face of the component body 1 and the flat portions 5 a, 6 a. Since the projections 5b and 6b straddle the main surface, the size of the cracks 38 can be reduced even if an impact due to a drop or the like is applied in a mounted state without increasing the dimension in the W direction.
[0060]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the ceramic electronic component of this invention, since the thickness of the external electrode of the edge part of the end surface of a component main body and the main surface was thickened, it is excellent in impact resistance.
[0061]
Further, a flat portion of the external electrode is formed substantially at the center of the end surface of the component body, and it is not necessary to increase the thickness of the entire external electrode. This has the effect of reducing the height at which the joining material rises.
[Brief description of the drawings]
FIG. 1 is a view showing a multiple capacitor of the present invention, wherein (a) is an external perspective view and (b) is a cross-sectional view taken along line XX.
FIG. 2 is a sectional view showing a state in which the multiple capacitor of FIG. 1 is surface-mounted on a wiring board.
FIG. 3 is an external perspective view showing another embodiment of the multiple capacitor of the present invention.
4A and 4B are views showing a conventional multiple capacitor, in which FIG. 4A is an external perspective view in a partially transparent state, and FIG. 4B is a sectional view taken along line XX.
[Explanation of symbols]
10 Multiple capacitors (ceramic electronic components)
1 laminated body (part body)
2 Dielectric layer 3, 4 Internal electrode 5, 6 External electrode 5a, 6a Flat portion 5b, 6b Convex portion 11 Wiring board 12 Wiring pattern 13 Solder

Claims (2)

内部導体が形成されたセラミックス部材からなる直方体の部品本体と、前記内部導体に接続し、且つ該部品本体の端面と主面とに跨がるように形成された外部電極とを備えてなるセラミック電子部品において、
前記外部電極は、前記部品本体の端面と主面との稜線部の導体厚みが、前記部品本体の端面の中央部分に形成された導体厚みに比して厚くなっていることを特徴とするセラミック電子部品。
A ceramic comprising: a rectangular parallelepiped component body made of a ceramic member having an internal conductor formed thereon; and external electrodes connected to the internal conductor and formed so as to extend over an end face and a main surface of the component body. In electronic components,
The external electrode, wherein a conductor thickness at a ridge portion between an end surface and a main surface of the component body is thicker than a conductor thickness formed at a central portion of an end surface of the component body. Electronic components.
前記外部電極の稜線部の導体厚みをnbとし、前記端面に形成された導体厚みをnaとした時、nb/na値が1.1〜3.0であることを特徴となる請求項1記載のセラミック電子部品。The nb / na value is 1.1 to 3.0, where nb is the conductor thickness of the ridge portion of the external electrode and na is the conductor thickness formed on the end face. Ceramic electronic components.
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