JP2008205073A - Ceramic capacitor - Google Patents
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- JP2008205073A JP2008205073A JP2007037554A JP2007037554A JP2008205073A JP 2008205073 A JP2008205073 A JP 2008205073A JP 2007037554 A JP2007037554 A JP 2007037554A JP 2007037554 A JP2007037554 A JP 2007037554A JP 2008205073 A JP2008205073 A JP 2008205073A
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電子機器等に用いられるセラミックコンデンサに関する。 The present invention relates to a ceramic capacitor used in electronic equipment and the like.
従来のセラミックコンデンサの構成を説明する。 The configuration of a conventional ceramic capacitor will be described.
図5は、従来のセラミックコンデンサの断面図である。図5において、内部電極11と誘電体層12を交互に積層して構成された積層体13の両端面に一対の外部電極14が形成されており、前記内部電極11は、前記一対の外部電極14と電気的に交互に接続されてセラミックコンデンサ15を構成している。
FIG. 5 is a cross-sectional view of a conventional ceramic capacitor. In FIG. 5, a pair of
近年の電子機器の小型化により、セラミックコンデンサにおいても小型化が要望されている。上述したセラミックコンデンサ15を小型化する場合、誘電体層12、内部電極11および外部電極14をそれぞれ薄層化する方法が考えられるが、単にこの方法で小型化を図った場合、プリント基板等に実装するときセラミックコンデンサが破損する恐れがある。
Due to the recent miniaturization of electronic devices, ceramic capacitors are also required to be miniaturized. In the case of downsizing the
すなわち、積層体13と外部電極14による段差は外部電極14を薄層化したとしてもなくなることはなく、また、積層体の薄層化による強度低下も合わさることで実装時の機械的ストレスによりセラミックコンデンサが破損する恐れがある。
That is, the step between the laminated
ここで、少なくとも実装面の外部電極を積層体側に押し込んで外部電極と積層体とを面一にすれば上述した段差をなくすことができるので、前記破損を低減することはできる。 Here, at least the external electrode on the mounting surface is pushed into the laminated body side so that the external electrode and the laminated body are flush with each other, so that the above-described step can be eliminated, so that the damage can be reduced.
なお、本出願の発明に関連する先行技術文献情報としては、特許文献1が知られている。
しかしながら、実装面の外部電極を積層体側に押し込むことで積層方向から見て外部電極と重なる内部電極部分の電極間距離が狭くなってしまい、その結果、ショートしやすくなるという問題があった。 However, when the external electrode on the mounting surface is pushed into the laminated body, the distance between the electrodes of the internal electrode portion that overlaps the external electrode when viewed from the stacking direction becomes narrow, and as a result, there is a problem that short-circuiting easily occurs.
そこで、本発明は、セラミックコンデンサの破損を低減するとともにショートの発生を低減することを目的とする。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the occurrence of a short circuit while reducing breakage of a ceramic capacitor.
この目的を達成するために、本発明は、誘電体と内部電極を交互に積層した積層体と、この積層体の少なくとも両端面から実装面にかけて設け前記内部電極と交互に接続された一対の外部電極とを有するセラミックコンデンサにおいて、前記積層体および前記一対の外部電極は、実装面において略面一であるとともに、前記積層体の積層方向における少なくとも最外位置の一対の内部電極のそれぞれと、この一対の内部電極のそれぞれと電気的に非接続の外部電極のそれぞれが積層方向から見て重ならない構成としたものである。 In order to achieve this object, the present invention provides a laminate in which dielectrics and internal electrodes are alternately laminated, and a pair of external electrodes provided alternately from at least both end faces to the mounting surface of the laminate and connected to the internal electrodes. In the ceramic capacitor having an electrode, the laminate and the pair of external electrodes are substantially flush with each other on the mounting surface, and each of the pair of internal electrodes at least at the outermost position in the stacking direction of the laminate, Each of the pair of internal electrodes and each of the external electrodes that are not electrically connected do not overlap each other when viewed from the stacking direction.
本発明の構成によれば、積層体および一対の外部電極が実装面において略面一としていることで、積層体と実装面の外部電極との段差を抑制することができ、これにより実装時の機械的ストレスによるセラミックコンデンサの破損を低減することができる。 According to the configuration of the present invention, since the laminate and the pair of external electrodes are substantially flush with each other on the mounting surface, a step between the laminate and the external electrode on the mounting surface can be suppressed. Breakage of the ceramic capacitor due to mechanical stress can be reduced.
加えて、積層体の積層方向における少なくとも最外位置の一対の内部電極のそれぞれと、この最外位置の一対の内部電極が電気的に非接続の外部電極のそれぞれが積層方向から見て重ならないようにすることで、ショートの発生を抑制することができる。 In addition, each of the pair of internal electrodes at least at the outermost position in the stacking direction of the stacked body and each of the external electrodes that are not electrically connected to the pair of internal electrodes at the outermost position do not overlap each other when viewed from the stacking direction. By doing so, the occurrence of a short circuit can be suppressed.
すなわち、従来の構成のように実装面の外部電極を積層体側に押し込む構成とした場合、積層方向から見て外部電極と重なる内部電極部分の電極間距離が狭くなってしまい、この部分でショートが発生しやすかったが、本発明の構成によればこの電極間距離が狭くなる内部電極部分がなくなるため、ショートの発生を抑制することができる。 In other words, when the external electrode on the mounting surface is pushed into the laminate as in the conventional configuration, the distance between the electrodes of the internal electrode that overlaps the external electrode as viewed from the stacking direction becomes narrow, and a short circuit occurs in this portion. Although it was easy to generate | occur | produce, according to the structure of this invention, since the internal electrode part in which this distance between electrodes becomes narrow is lost, generation | occurrence | production of a short circuit can be suppressed.
以下、本発明のセラミックコンデンサについて一実施の形態および図面を用いて説明する。 Hereinafter, a ceramic capacitor of the present invention will be described with reference to an embodiment and drawings.
図1は本発明のセラミックコンデンサの斜視図、図2は同断面図、図3は同積層体の分解斜視図である。 FIG. 1 is a perspective view of a ceramic capacitor of the present invention, FIG. 2 is a sectional view thereof, and FIG. 3 is an exploded perspective view of the laminate.
図1〜図3において、誘電体1と内部電極2を交互に積層して積層体3を構成している。この積層体3の両端面には外部電極4、5がそれぞれ形成されており、前記内部電極2が交互に前記外部電極4、5に電気的にそれぞれ接続されている。そして、前記外部電極4、5と積層体3は実装面(本一実施の形態においては実装面の対向面も)において略面一となっている。
1 to 3, a dielectric 3 and
また、積層方向における最外位置の一対の内部電極2bは、積層方向の中央部に位置する一対の内部電極2aと比較して長手方向に短く形成することで最外位置の一対の内部電極2bが電気的に接続される外部電極と対向する外部電極(電気的に非接続の外部電極)とが積層方向から見て重ならないように構成されている。すなわち、図2において、A線は外部電極5の端から積層方向に引いた線を示しており、最外位置の一対の内部電極2bのうち外部電極5と非接続の内部電極2baが前記A線を横切らないように形成する。他方の内部電極2bbも同様である。
In addition, the pair of
このように内部電極を構成することで、積層方向から見て外部電極と重なる内部電極部分の電極間距離を外部電極と重ならない内部電極部分の電極間距離と同程度に確保することができ、その結果、ショートの発生を抑制することができる。 By configuring the internal electrodes in this way, the distance between the electrodes of the internal electrode portion that overlaps with the external electrode when viewed from the stacking direction can be secured to the same level as the distance between the electrodes of the internal electrode portion that does not overlap with the external electrode, As a result, occurrence of a short circuit can be suppressed.
すなわち、本発明のセラミックコンデンサは、積層方向から見て外部電極と重なる部分と重ならない部分とで内部電極の電極間距離が一定であるという特徴を有するものである。 That is, the ceramic capacitor of the present invention is characterized in that the distance between the electrodes of the internal electrode is constant between the portion that overlaps the external electrode and the portion that does not overlap when viewed from the stacking direction.
以上のように、本発明のセラミックコンデンサは、誘電体と内部電極を交互に積層した積層体と、この積層体の少なくとも両端面から実装面にかけて設け前記内部電極と交互に接続された一対の外部電極とを有するセラミックコンデンサにおいて、前記積層体および前記一対の外部電極は、実装面において略面一であるとともに、前記積層体の積層方向における少なくとも最外位置の一対の内部電極のうちの一方の内部電極とこの一方の内部電極と非接続の外部電極が積層方向から見て重ならないようにし、前記最外位置の一対の内部電極のうちの他方の内部電極とこの他方の内部電極と非接続の外部電極が積層方向から見て重ならないよう構成されている。 As described above, the ceramic capacitor of the present invention includes a laminated body in which dielectrics and internal electrodes are alternately laminated, and a pair of external electrodes provided alternately from at least both end faces to the mounting surface of the laminated body and connected to the internal electrodes. In the ceramic capacitor having an electrode, the stacked body and the pair of external electrodes are substantially flush with each other on a mounting surface, and one of at least the outermost pair of internal electrodes in the stacking direction of the stacked body. An internal electrode and an external electrode that is not connected to one internal electrode are not overlapped when viewed from the stacking direction, and the other internal electrode of the pair of internal electrodes at the outermost position is not connected to the other internal electrode The external electrodes are configured not to overlap each other when viewed from the stacking direction.
本発明のセラミックコンデンサ6の製造方法としては、従来の製造方法を用いることができる。すなわち、セラミックグリーンシートと内部電極を交互に積層して焼成前積層体を形成する。このとき、図3に示すように、内部電極2のパターンを最外位置の内部電極2bと非最外位置の内部電極2aとで変えればよい。
As a method for manufacturing the ceramic capacitor 6 of the present invention, a conventional manufacturing method can be used. That is, a ceramic green sheet and internal electrodes are alternately laminated to form a pre-fired laminate. At this time, as shown in FIG. 3, the pattern of the
このような内部電極の構成にて作製した焼成前積層体は、図2に示すように、積層時のプレスにより最外位置の内部電極2bに起因する段差Bが形成される。したがって、この段差Bを利用して外部電極を形成する。すなわち、前記焼成前積層体の両端面から実装面にかけて、焼成後に外部電極となるように電極ペーストでこの段差Bを埋めるようにして形成し、乾燥する。これにより積層体と外部電極が実装面においてほぼ面一とすることができる。これにより積層体と外部電極による段差が抑制されるので、実装時の機械的ストレスによるセラミックコンデンサの破損を低減することができる。
As shown in FIG. 2, in the pre-fired laminate produced with such an internal electrode configuration, a step B caused by the outermost
また、焼成前に、外部電極を形成した積層体を必要に応じて積層方向にプレスしてもよい。これにより、積層体と外部電極が実装面においてより面一とすることができる。 Moreover, you may press the laminated body in which the external electrode was formed in the lamination direction as needed before baking. Thereby, a laminated body and an external electrode can be made more flush with a mounting surface.
次に、外部電極を形成した積層体を焼成して本発明のセラミックコンデンサを得ることができる。 Next, the laminated body in which the external electrode is formed can be fired to obtain the ceramic capacitor of the present invention.
以上のように本発明のセラミックコンデンサの作製は、新たな製造装置を用いる必要はなく、従来の製造装置を用いることができる。また、各構成にて使用する各材料についても従来のものを用いることができる。 As described above, the production of the ceramic capacitor of the present invention does not require use of a new manufacturing apparatus, and a conventional manufacturing apparatus can be used. In addition, conventional materials can be used for each material used in each configuration.
また、他の一実施の形態としては、図4に示すように、最外内部電極2bのさらに外側(積層方向側)に外部電極4、5に接続されていない捨て電極7を設けることも可能である。このように捨て電極7を設けることで、積層方向から見て外部電極と重なる部分と重ならない部分とで内部電極の電極間距離を一定としながら、積層体と外部電極が実装面において同一面とすることができる。また、製造方法においても新たな工程を加えることなく電極パターンを変えてこれを捨て電極7とすればよく、簡便に実施することができるという利点がある。
As another embodiment, as shown in FIG. 4, it is also possible to provide a
なお、上述した一実施の形態においては、最外位置の一対の内部電極を長手方向に短くした構成を説明したが、このような構成の内部電極は最外位置のみに限定されず、そのすぐ内層に位置する一対の内部電極も併せて同様の構成にすることも可能である。図2、3では、最外位置の一対の内部電極と、そのすぐ内層に位置する一対の内部電極を長手方向にそれぞれ短くし、図4では最外位置の一対の内部電極を長手方向に短くした。このような構成の内部電極の数は外部電極の厚み、内部電極の厚み、誘電体の厚みに応じて適宜設定すればよい。 In the above-described embodiment, the configuration in which the pair of internal electrodes at the outermost position is shortened in the longitudinal direction has been described. However, the internal electrode having such a configuration is not limited to the outermost position, but immediately The pair of internal electrodes located in the inner layer can also be configured similarly. 2 and 3, the pair of inner electrodes at the outermost position and the pair of internal electrodes located immediately in the inner layer are shortened in the longitudinal direction, and the pair of inner electrodes at the outermost position are shortened in the longitudinal direction in FIG. 4. did. What is necessary is just to set the number of the internal electrodes of such a structure suitably according to the thickness of an external electrode, the thickness of an internal electrode, and the thickness of a dielectric material.
本発明は、耐機械的ストレス性および耐ショート性が向上するという特徴を有し、電子機器等に有用である。 The present invention is characterized by improved mechanical stress resistance and short-circuit resistance, and is useful for electronic devices and the like.
1 誘電体
2、2a、2b、2ba、2bb 内部電極
3 積層体
4、5 外部電極
6 セラミックコンデンサ
7 捨て電極
1 Dielectric 2, 2a, 2b, 2ba, 2bb
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JP2009253010A (en) * | 2008-04-07 | 2009-10-29 | Panasonic Corp | Multilayer ceramic electronic component |
JP2012028458A (en) * | 2010-07-21 | 2012-02-09 | Murata Mfg Co Ltd | Ceramic electronic component |
JP2012038917A (en) * | 2010-08-06 | 2012-02-23 | Murata Mfg Co Ltd | Ceramic electronic component and method for manufacturing the same |
JP2012044149A (en) * | 2010-07-21 | 2012-03-01 | Murata Mfg Co Ltd | Ceramic electronic component |
JP2012256947A (en) * | 2012-09-28 | 2012-12-27 | Murata Mfg Co Ltd | Multilayer ceramic electronic component and manufacturing method therefor |
US20130229748A1 (en) * | 2012-02-17 | 2013-09-05 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic electronic component and method of manufacturing the same |
JP2013183028A (en) * | 2012-03-01 | 2013-09-12 | Ibiden Co Ltd | Electronic component built-in wiring board, chip capacitor, and manufacturing method of electronic component built-in wiring board |
JP2014236215A (en) * | 2013-05-31 | 2014-12-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Multilayer ceramic electronic component and mounting board of multilayer ceramic electronic component |
US9129729B2 (en) | 2012-11-07 | 2015-09-08 | Murata Manufacturing Co., Ltd. | Ceramic electronic component |
US9148954B2 (en) | 2013-03-26 | 2015-09-29 | Murata Manufacturing Co., Ltd. | Ceramic electronic component and wiring board having built-in ceramic electronic component |
JP2018067565A (en) * | 2016-10-17 | 2018-04-26 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
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JP2014236215A (en) * | 2013-05-31 | 2014-12-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Multilayer ceramic electronic component and mounting board of multilayer ceramic electronic component |
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JP2018067565A (en) * | 2016-10-17 | 2018-04-26 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
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